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-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini2
-rwxr-xr-xtests/long/se/10.mcf/ref/arm/linux/o3-timing/simout8
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt1171
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini2
-rwxr-xr-xtests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout8
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt78
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini2
-rwxr-xr-xtests/long/se/10.mcf/ref/arm/linux/simple-timing/simout8
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt315
-rw-r--r--tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini2
-rwxr-xr-xtests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout8
-rw-r--r--tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt221
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini2
-rwxr-xr-xtests/long/se/10.mcf/ref/x86/linux/o3-timing/simout8
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt1022
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini2
-rwxr-xr-xtests/long/se/10.mcf/ref/x86/linux/simple-timing/simout8
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt302
18 files changed, 1571 insertions, 1598 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
index dcc46b583..354c87304 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
@@ -507,7 +507,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
-cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
+cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing
egid=100
env=
errout=cerr
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
index 60efd00ac..e2beccd27 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 4 2012 12:14:06
-gem5 started Jun 4 2012 17:32:09
+gem5 compiled Jun 28 2012 22:10:14
+gem5 started Jun 29 2012 00:41:22
gem5 executing on zizzer
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -23,4 +23,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 25988864000 because target called exit()
+Exiting @ tick 25878583500 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
index 90f8077ba..507566fcc 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -1,39 +1,32 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.025989 # Number of seconds simulated
-sim_ticks 25988864000 # Number of ticks simulated
-final_tick 25988864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.025879 # Number of seconds simulated
+sim_ticks 25878583500 # Number of ticks simulated
+final_tick 25878583500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 141606 # Simulator instruction rate (inst/s)
-host_op_rate 142623 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 40620332 # Simulator tick rate (ticks/s)
-host_mem_usage 364696 # Number of bytes of host memory used
-host_seconds 639.80 # Real time elapsed on the host
-sim_insts 90599356 # Number of instructions simulated
-sim_ops 91249910 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 46144 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 952896 # Number of bytes read from this memory
-system.physmem.bytes_read::total 999040 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 46144 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 46144 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 2048 # Number of bytes written to this memory
-system.physmem.bytes_written::total 2048 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 721 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 14889 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15610 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 32 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 32 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1775530 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 36665550 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 38441080 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1775530 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1775530 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 78803 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 78803 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 78803 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1775530 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 36665550 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 38519883 # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate 220420 # Simulator instruction rate (inst/s)
+host_op_rate 222002 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 62960153 # Simulator tick rate (ticks/s)
+host_mem_usage 367872 # Number of bytes of host memory used
+host_seconds 411.03 # Real time elapsed on the host
+sim_insts 90599358 # Number of instructions simulated
+sim_ops 91249911 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 45504 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 947456 # Number of bytes read from this memory
+system.physmem.bytes_read::total 992960 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 45504 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 45504 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 711 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 14804 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15515 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1758365 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 36611587 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 38369952 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1758365 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1758365 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1758365 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 36611587 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 38369952 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@@ -77,322 +70,322 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
-system.cpu.numCycles 51977729 # number of cpu cycles simulated
+system.cpu.numCycles 51757168 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 27100787 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 22324909 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 913851 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 11625204 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 11498872 # Number of BTB hits
+system.cpu.BPredUnit.lookups 26984015 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 22232491 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 888214 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 11580024 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 11447482 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 61157 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 10323 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 14508615 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 130146910 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 27100787 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 11560029 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 24493529 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4999674 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 8879281 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 50 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 14156722 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 388066 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 51938784 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.527703 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.247354 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 71474 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 416 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 14414928 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 129560918 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 26984015 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 11518956 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 24378433 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4928329 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 8911472 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 24 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 14076190 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 379999 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 51715551 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.525564 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.245999 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 27487299 52.92% 52.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 3456218 6.65% 59.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 2037280 3.92% 63.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1594827 3.07% 66.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1702478 3.28% 69.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2979904 5.74% 75.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1536396 2.96% 78.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1112311 2.14% 80.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 10032071 19.32% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 27375149 52.93% 52.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 3448740 6.67% 59.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 2025913 3.92% 63.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1592010 3.08% 66.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1693129 3.27% 69.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2969374 5.74% 75.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1533811 2.97% 78.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1107315 2.14% 80.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 9970110 19.28% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 51938784 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.521392 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.503898 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 17258666 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 6822276 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 22930941 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 878432 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 4048469 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 4484484 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 8960 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 128309268 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 42973 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 4048469 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 19038937 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 2026641 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 195067 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 21988132 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 4641538 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 124853766 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 286024 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 3901771 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 441 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 145615724 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 543819179 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 543813062 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 6117 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 107429479 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 38186245 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 20008 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 20006 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 11296413 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 29738779 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 5601526 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 2062082 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1203344 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 119239629 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 22672 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 105633795 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 86270 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 27804178 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 69103102 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 12544 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 51938784 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.033813 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.918657 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 51715551 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.521358 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.503246 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 17151536 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 6845661 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 22836822 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 879705 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 4001827 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 4473928 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 9005 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 127743952 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 42919 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 4001827 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 18918146 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 2041479 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 194552 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 21908799 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 4650748 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 124387508 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 37 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 285864 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 3910791 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 369 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 145115578 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 541729246 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 541723014 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 6232 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 107429482 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 37686096 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 18180 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 18178 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 11273342 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 29662115 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 5564551 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 2120620 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 1233720 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 118944023 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 22020 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 105456921 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 87203 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 27512358 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 68343356 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 11890 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 51715551 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.039172 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.917652 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 14084713 27.12% 27.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 11449450 22.04% 49.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 8003608 15.41% 64.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 6710442 12.92% 77.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 5305637 10.22% 87.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2900837 5.59% 93.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 2546575 4.90% 98.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 460556 0.89% 99.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 476966 0.92% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 13904878 26.89% 26.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 11456546 22.15% 49.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7969137 15.41% 64.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 6724396 13.00% 77.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 5314058 10.28% 87.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2865211 5.54% 93.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 2534987 4.90% 98.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 474000 0.92% 99.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 472338 0.91% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 51938784 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 51715551 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 33927 5.08% 5.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 27 0.00% 5.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 5.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 5.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 5.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 5.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 354815 53.12% 58.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 279170 41.80% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 33403 5.02% 5.02% # attempts to use FU when none available
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+system.cpu.iq.fu_full::IntDiv 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 354808 53.31% 58.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 277311 41.67% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 74740578 70.75% 70.75% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 10525 0.01% 70.76% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.76% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.76% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.76% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.76% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.76% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.76% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 195 0.00% 70.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 237 0.00% 70.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.76% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 25722669 24.35% 95.12% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 5159588 4.88% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 74629419 70.77% 70.77% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 10524 0.01% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 188 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 232 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 25677872 24.35% 95.13% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 5138682 4.87% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 105633795 # Type of FU issued
-system.cpu.iq.rate 2.032290 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 667939 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.006323 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 263959647 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 147067415 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 102938725 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 936 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1347 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 404 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 106301267 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 467 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 423068 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 105456921 # Type of FU issued
+system.cpu.iq.rate 2.037533 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 665549 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.006311 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 263381228 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 146480266 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 102833498 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 917 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 1333 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 399 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 106122017 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 453 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 424644 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 7162902 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 8413 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 3100 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 854772 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 7086237 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 8981 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 4129 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 817795 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 39235 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 39333 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 4048469 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 193737 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 33246 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 119298911 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 399459 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 29738779 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 5601526 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 18769 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 13636 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 1014 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 3100 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 499711 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 490212 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 989923 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 104558374 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 25377273 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1075421 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 4001827 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 198669 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 33921 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 119002430 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 339181 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 29662115 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 5564551 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 18117 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 13618 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 1230 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 4129 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 473445 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 489320 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 962765 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 104433557 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 25350982 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1023364 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 36610 # number of nop insts executed
-system.cpu.iew.exec_refs 30470186 # number of memory reference insts executed
-system.cpu.iew.exec_branches 21355608 # Number of branches executed
-system.cpu.iew.exec_stores 5092913 # Number of stores executed
-system.cpu.iew.exec_rate 2.011600 # Inst execution rate
-system.cpu.iew.wb_sent 103258351 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 102939129 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 62202150 # num instructions producing a value
-system.cpu.iew.wb_consumers 103963576 # num instructions consuming a value
+system.cpu.iew.exec_nop 36387 # number of nop insts executed
+system.cpu.iew.exec_refs 30425523 # number of memory reference insts executed
+system.cpu.iew.exec_branches 21334984 # Number of branches executed
+system.cpu.iew.exec_stores 5074541 # Number of stores executed
+system.cpu.iew.exec_rate 2.017760 # Inst execution rate
+system.cpu.iew.wb_sent 103141450 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 102833897 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 62142858 # num instructions producing a value
+system.cpu.iew.wb_consumers 103855994 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.980447 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.598307 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.986853 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.598356 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 90611965 # The number of committed instructions
-system.cpu.commit.commitCommittedOps 91262519 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 28037719 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 10128 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 916929 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 47890316 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.905657 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.507554 # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts 90611967 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 91262520 # The number of committed instructions
+system.cpu.commit.commitSquashedInsts 27741223 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 10130 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 891236 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 47713725 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.912710 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.511102 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 17540600 36.63% 36.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13534361 28.26% 64.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4502880 9.40% 74.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 3873758 8.09% 82.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1516151 3.17% 85.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 799389 1.67% 87.21% # Number of insts commited each cycle
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@@ -401,246 +394,246 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu.dcache.writebacks::total 942908 # number of writebacks
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-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3671.245091 # average overall mshr miss latency
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-system.cpu.l2cache.replacements 770 # number of replacements
-system.cpu.l2cache.tagsinuse 10017.166349 # Cycle average of tags in use
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-system.cpu.l2cache.occ_blocks::writebacks 9634.775304 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 182.147356 # Average occupied blocks per requestor
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-system.cpu.l2cache.overall_avg_miss_latency::total 34347.279129 # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 9660.066682 # Average occupied blocks per requestor
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+system.cpu.l2cache.occ_blocks::cpu.data 230.921571 # Average occupied blocks per requestor
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+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34275.983146 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34244.604317 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34267.171717 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34341.944139 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34341.944139 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34275.983146 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34340.117456 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34337.176349 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34275.983146 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34340.117456 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34337.176349 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -649,61 +642,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 32 # number of writebacks
-system.cpu.l2cache.writebacks::total 32 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits
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system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 721 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 355 # number of ReadReq MSHR misses
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-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000393 # mshr miss rate for ReadReq accesses
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-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015711 # mshr miss rate for overall accesses
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-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31087.378641 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31195.774648 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31123.141264 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31101.726985 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31101.726985 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31087.378641 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31103.969373 # average overall mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31103.969373 # average overall mshr miss latency
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+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964722 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015621 # mshr miss rate for demand accesses
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+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015621 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.016359 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31092.827004 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31208.955224 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31124.616956 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31103.364062 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31103.364062 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31092.827004 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31105.275601 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31104.705124 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31092.827004 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31105.275601 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31104.705124 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
index 394878465..0837df787 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
@@ -95,7 +95,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
-cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic
+cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic
egid=100
env=
errout=cerr
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
index 6025dc422..f567cacf4 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 4 2012 12:14:06
-gem5 started Jun 4 2012 17:36:14
+gem5 compiled Jun 28 2012 22:10:14
+gem5 started Jun 29 2012 00:44:35
gem5 executing on zizzer
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -23,4 +23,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 54240666000 because target called exit()
+Exiting @ tick 54240661000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
index cb9066ccb..6111a0118 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
@@ -1,38 +1,38 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.054241 # Number of seconds simulated
-sim_ticks 54240666000 # Number of ticks simulated
-final_tick 54240666000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 54240661000 # Number of ticks simulated
+final_tick 54240661000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2223712 # Simulator instruction rate (inst/s)
-host_op_rate 2239678 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1331261387 # Simulator tick rate (ticks/s)
-host_mem_usage 354056 # Number of bytes of host memory used
-host_seconds 40.74 # Real time elapsed on the host
-sim_insts 90602415 # Number of instructions simulated
-sim_ops 91252969 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 431323116 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 90016599 # Number of bytes read from this memory
-system.physmem.bytes_read::total 521339715 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 431323116 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 431323116 # Number of instructions bytes read from this memory
+host_inst_rate 3184418 # Simulator instruction rate (inst/s)
+host_op_rate 3207282 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1906403630 # Simulator tick rate (ticks/s)
+host_mem_usage 357244 # Number of bytes of host memory used
+host_seconds 28.45 # Real time elapsed on the host
+sim_insts 90602407 # Number of instructions simulated
+sim_ops 91252960 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 431323080 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 90016598 # Number of bytes read from this memory
+system.physmem.bytes_read::total 521339678 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 431323080 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 431323080 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 18908138 # Number of bytes written to this memory
system.physmem.bytes_written::total 18908138 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 107830779 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 22553295 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 130384074 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 107830770 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 22553294 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 130384064 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 4738868 # Number of write requests responded to by this memory
system.physmem.num_writes::total 4738868 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 7952024704 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1659577687 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 9611602391 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 7952024704 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 7952024704 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 348597084 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 348597084 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 7952024704 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2008174771 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 9960199475 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 7952024773 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1659577821 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 9611602595 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 7952024773 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 7952024773 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 348597116 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 348597116 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 7952024773 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2008174937 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 9960199711 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@@ -76,26 +76,26 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
-system.cpu.numCycles 108481333 # number of cpu cycles simulated
+system.cpu.numCycles 108481323 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 90602415 # Number of instructions committed
-system.cpu.committedOps 91252969 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses
+system.cpu.committedInsts 90602407 # Number of instructions committed
+system.cpu.committedOps 91252960 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 72525674 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
-system.cpu.num_func_calls 96832 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 15548926 # number of instructions that are conditional controls
-system.cpu.num_int_insts 72525682 # number of integer instructions
+system.cpu.num_func_calls 112245 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 15548925 # number of instructions that are conditional controls
+system.cpu.num_int_insts 72525674 # number of integer instructions
system.cpu.num_fp_insts 48 # number of float instructions
-system.cpu.num_int_register_reads 396912516 # number of times the integer registers were read
-system.cpu.num_int_register_writes 106840370 # number of times the integer registers were written
+system.cpu.num_int_register_reads 396912478 # number of times the integer registers were read
+system.cpu.num_int_register_writes 106840357 # number of times the integer registers were written
system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
-system.cpu.num_mem_refs 27318811 # number of memory refs
-system.cpu.num_load_insts 22573967 # Number of load instructions
+system.cpu.num_mem_refs 27318810 # number of memory refs
+system.cpu.num_load_insts 22573966 # Number of load instructions
system.cpu.num_store_insts 4744844 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 108481333 # Number of busy cycles
+system.cpu.num_busy_cycles 108481323 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
index 227acc83b..8e4e9dec7 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
@@ -176,7 +176,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
-cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing
+cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing
egid=100
env=
errout=cerr
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
index b972e2aeb..78b502a64 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 4 2012 12:14:06
-gem5 started Jun 4 2012 17:37:05
+gem5 compiled Jun 28 2012 22:10:14
+gem5 started Jun 29 2012 00:44:41
gem5 executing on zizzer
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -23,4 +23,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 148086239000 because target called exit()
+Exiting @ tick 148083373000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
index dd28872f6..63806d746 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
@@ -1,39 +1,32 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.148086 # Number of seconds simulated
-sim_ticks 148086239000 # Number of ticks simulated
-final_tick 148086239000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.148083 # Number of seconds simulated
+sim_ticks 148083373000 # Number of ticks simulated
+final_tick 148083373000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1056603 # Simulator instruction rate (inst/s)
-host_op_rate 1064179 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1727464138 # Simulator tick rate (ticks/s)
-host_mem_usage 363220 # Number of bytes of host memory used
-host_seconds 85.72 # Real time elapsed on the host
-sim_insts 90576869 # Number of instructions simulated
-sim_ops 91226321 # Number of ops (including micro ops) simulated
+host_inst_rate 1433979 # Simulator instruction rate (inst/s)
+host_op_rate 1444261 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2344399916 # Simulator tick rate (ticks/s)
+host_mem_usage 365828 # Number of bytes of host memory used
+host_seconds 63.16 # Real time elapsed on the host
+sim_insts 90576861 # Number of instructions simulated
+sim_ops 91226312 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 949120 # Number of bytes read from this memory
-system.physmem.bytes_read::total 986112 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 944768 # Number of bytes read from this memory
+system.physmem.bytes_read::total 981760 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 36992 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 36992 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 2048 # Number of bytes written to this memory
-system.physmem.bytes_written::total 2048 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 578 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 14830 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15408 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 32 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 32 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 249800 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 6409238 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 6659039 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 249800 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 249800 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 13830 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 13830 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 13830 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 249800 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 6409238 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6672869 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::cpu.data 14762 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 249805 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 6379974 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 6629779 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 249805 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 249805 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 249805 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 6379974 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 6629779 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@@ -77,43 +70,43 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
-system.cpu.numCycles 296172478 # number of cpu cycles simulated
+system.cpu.numCycles 296166746 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 90576869 # Number of instructions committed
-system.cpu.committedOps 91226321 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses
+system.cpu.committedInsts 90576861 # Number of instructions committed
+system.cpu.committedOps 91226312 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 72525674 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
-system.cpu.num_func_calls 96832 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 15548926 # number of instructions that are conditional controls
-system.cpu.num_int_insts 72525682 # number of integer instructions
+system.cpu.num_func_calls 112245 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 15548925 # number of instructions that are conditional controls
+system.cpu.num_int_insts 72525674 # number of integer instructions
system.cpu.num_fp_insts 48 # number of float instructions
-system.cpu.num_int_register_reads 464563396 # number of times the integer registers were read
-system.cpu.num_int_register_writes 106840370 # number of times the integer registers were written
+system.cpu.num_int_register_reads 464563355 # number of times the integer registers were read
+system.cpu.num_int_register_writes 106840357 # number of times the integer registers were written
system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
-system.cpu.num_mem_refs 27318811 # number of memory refs
-system.cpu.num_load_insts 22573967 # Number of load instructions
+system.cpu.num_mem_refs 27318810 # number of memory refs
+system.cpu.num_load_insts 22573966 # Number of load instructions
system.cpu.num_store_insts 4744844 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 296172478 # Number of busy cycles
+system.cpu.num_busy_cycles 296166746 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 2 # number of replacements
-system.cpu.icache.tagsinuse 510.335448 # Cycle average of tags in use
-system.cpu.icache.total_refs 107830181 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 510.334547 # Cycle average of tags in use
+system.cpu.icache.total_refs 107830172 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 599 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 180016.996661 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 180016.981636 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 510.335448 # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst 510.334547 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.249187 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.249187 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 107830181 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 107830181 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 107830181 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 107830181 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 107830181 # number of overall hits
-system.cpu.icache.overall_hits::total 107830181 # number of overall hits
+system.cpu.icache.ReadReq_hits::cpu.inst 107830172 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 107830172 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 107830172 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 107830172 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 107830172 # number of overall hits
+system.cpu.icache.overall_hits::total 107830172 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 599 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 599 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 599 # number of demand (read+write) misses
@@ -126,12 +119,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 32662000
system.cpu.icache.demand_miss_latency::total 32662000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 32662000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 32662000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 107830780 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 107830780 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 107830780 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 107830780 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 107830780 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 107830780 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst 107830771 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 107830771 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 107830771 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 107830771 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 107830771 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 107830771 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000006 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 # miss rate for demand accesses
@@ -178,26 +171,26 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910
system.cpu.icache.overall_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 942702 # number of replacements
-system.cpu.dcache.tagsinuse 3568.549501 # Cycle average of tags in use
-system.cpu.dcache.total_refs 26345365 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 3568.539568 # Cycle average of tags in use
+system.cpu.dcache.total_refs 26345364 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 27.825751 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 54479156000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 3568.549501 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.871228 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.871228 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 21649219 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 21649219 # number of ReadReq hits
+system.cpu.dcache.avg_refs 27.825750 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 54479146000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 3568.539568 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.871225 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.871225 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 21649218 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 21649218 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 26337591 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 26337591 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 26337591 # number of overall hits
-system.cpu.dcache.overall_hits::total 26337591 # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data 26337590 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 26337590 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 26337590 # number of overall hits
+system.cpu.dcache.overall_hits::total 26337590 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 900189 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 900189 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses
@@ -206,26 +199,26 @@ system.cpu.dcache.demand_misses::cpu.data 946798 # n
system.cpu.dcache.demand_misses::total 946798 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 946798 # number of overall misses
system.cpu.dcache.overall_misses::total 946798 # number of overall misses
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system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_miss_rate::total 0.039921 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses
@@ -234,14 +227,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.034701
system.cpu.dcache.demand_miss_rate::total 0.034701 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.034701 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.034701 # miss rate for overall accesses
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system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27109.399472 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 27109.399472 # average WriteReq miss latency
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-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14657.859438 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -250,8 +243,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.ReadReq_mshr_misses::total 900189 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses
@@ -260,14 +253,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 946798
system.cpu.dcache.demand_mshr_misses::total 946798 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses
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@@ -276,68 +269,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034701
system.cpu.dcache.demand_mshr_miss_rate::total 0.034701 # mshr miss rate for demand accesses
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+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 634 # number of replacements
-system.cpu.l2cache.tagsinuse 9235.307693 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1594542 # Total number of references to valid blocks.
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@@ -347,16 +340,16 @@ system.cpu.l2cache.overall_accesses::cpu.inst 599
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
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@@ -376,41 +369,39 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu.l2cache.demand_mshr_miss_latency::total 616320000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 590480000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 613600000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23120000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 593200000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 616320000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 590480000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 613600000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000313 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000955 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000238 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000879 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.312129 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015663 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.016264 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015591 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.016192 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015663 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.016264 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015591 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.016192 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
index e29268380..8e6bba913 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
@@ -158,7 +158,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
-cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
+cwd=build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing
egid=100
env=
errout=cerr
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
index 2436d9105..8432da315 100755
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 4 2012 12:01:47
-gem5 started Jun 4 2012 14:55:10
+gem5 compiled Jun 28 2012 22:06:58
+gem5 started Jun 28 2012 22:55:42
gem5 executing on zizzer
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -23,4 +23,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 362430887000 because target called exit()
+Exiting @ tick 362428997000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
index 9186661e0..75faf8d15 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
@@ -1,41 +1,34 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.362431 # Number of seconds simulated
-sim_ticks 362430887000 # Number of ticks simulated
-final_tick 362430887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.362429 # Number of seconds simulated
+sim_ticks 362428997000 # Number of ticks simulated
+final_tick 362428997000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1267775 # Simulator instruction rate (inst/s)
-host_op_rate 1267827 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1884467398 # Simulator tick rate (ticks/s)
-host_mem_usage 355400 # Number of bytes of host memory used
-host_seconds 192.33 # Real time elapsed on the host
+host_inst_rate 1801112 # Simulator instruction rate (inst/s)
+host_op_rate 1801186 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2677225778 # Simulator tick rate (ticks/s)
+host_mem_usage 354292 # Number of bytes of host memory used
+host_seconds 135.37 # Real time elapsed on the host
sim_insts 243825163 # Number of instructions simulated
sim_ops 243835278 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 945216 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1001472 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory
+system.physmem.bytes_read::total 998592 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 2560 # Number of bytes written to this memory
-system.physmem.bytes_written::total 2560 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 14769 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15648 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 40 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 40 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 155219 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2607990 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2763208 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2600057 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2755276 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 155219 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 155219 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 7063 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 7063 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 7063 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 155219 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2607990 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2770272 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2600057 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2755276 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 443 # Number of system calls
-system.cpu.numCycles 724861774 # number of cpu cycles simulated
+system.cpu.numCycles 724857994 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 243825163 # Number of instructions committed
@@ -54,16 +47,16 @@ system.cpu.num_mem_refs 105711442 # nu
system.cpu.num_load_insts 82803522 # Number of load instructions
system.cpu.num_store_insts 22907920 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 724861774 # Number of busy cycles
+system.cpu.num_busy_cycles 724857994 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 25 # number of replacements
-system.cpu.icache.tagsinuse 725.567632 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 725.567220 # Cycle average of tags in use
system.cpu.icache.total_refs 244420630 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 277120.895692 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 725.567632 # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst 725.567220 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.354281 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.354281 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 244420630 # number of ReadReq hits
@@ -136,12 +129,12 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857
system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 935475 # number of replacements
-system.cpu.dcache.tagsinuse 3563.824259 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 3563.821484 # Cycle average of tags in use
system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 134373316000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 3563.824259 # Average occupied blocks per requestor
+system.cpu.dcache.occ_blocks::cpu.data 3563.821484 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.870074 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.870074 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 81327577 # number of ReadReq hits
@@ -164,16 +157,16 @@ system.cpu.dcache.demand_misses::cpu.data 939567 # n
system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses
system.cpu.dcache.overall_misses::total 939567 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 12508482000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 12508482000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 12506592000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 12506592000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1265712000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 1265712000 # number of WriteReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::cpu.data 98000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::total 98000 # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 13774194000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 13774194000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 13774194000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 13774194000 # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 13772304000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 13772304000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 13772304000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 13772304000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 82220434 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 82220434 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses)
@@ -194,16 +187,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.008938
system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14009.502082 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14009.502082 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14007.385281 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14007.385281 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27097.238279 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 27097.238279 # average WriteReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 24500 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::total 24500 # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 14660.150899 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14660.150899 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14658.139334 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14658.139334 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14658.139334 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14658.139334 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -212,8 +205,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 935237 # number of writebacks
-system.cpu.dcache.writebacks::total 935237 # number of writebacks
+system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks
+system.cpu.dcache.writebacks::total 935266 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses
@@ -224,16 +217,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 939567
system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9829911000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 9829911000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9828021000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 9828021000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10955493000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 10955493000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10955493000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 10955493000 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10953603000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 10953603000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10953603000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 10953603000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses
@@ -244,70 +237,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938
system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.502082 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.502082 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.385281 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.385281 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11660.150899 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11660.150899 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11660.150899 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11660.150899 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 865 # number of replacements
-system.cpu.l2cache.tagsinuse 9236.752232 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1585884 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 15631 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 101.457616 # Average number of references to valid blocks.
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.tagsinuse 9744.405217 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1813121 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 15586 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 116.330104 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 8861.245791 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 244.574580 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 130.931861 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.270424 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.007464 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.003996 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.281883 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::writebacks 8861.272475 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 738.802087 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 144.330654 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.270425 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.022546 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.004405 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.297376 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 892655 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 892658 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 935237 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 935237 # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 892700 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 892703 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 935266 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 935266 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 924802 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 924805 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 924847 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 924850 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 924802 # number of overall hits
-system.cpu.l2cache.overall_hits::total 924805 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 924847 # number of overall hits
+system.cpu.l2cache.overall_hits::total 924850 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 879 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 202 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 1081 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 157 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 1036 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 14769 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 15648 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 14724 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 15603 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 14769 # number of overall misses
-system.cpu.l2cache.overall_misses::total 15648 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses
+system.cpu.l2cache.overall_misses::total 15603 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45708000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10504000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 56212000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8164000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 53872000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 757484000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 757484000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 45708000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 767988000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 813696000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 765648000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 811356000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 45708000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 767988000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 813696000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 765648000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 811356000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 882 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 892857 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 893739 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 935237 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 935237 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 935266 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 935266 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses
@@ -317,16 +310,16 @@ system.cpu.l2cache.overall_accesses::cpu.inst 882
system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000226 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.001210 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000176 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.001159 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.015719 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.016639 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.015671 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.016591 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.015719 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.016639 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
@@ -346,41 +339,39 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 40 # number of writebacks
-system.cpu.l2cache.writebacks::total 40 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 879 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 1081 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 157 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 1036 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 14769 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 15648 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 14724 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 14769 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 15648 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35160000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8080000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43240000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6280000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41440000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 582680000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 582680000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35160000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 590760000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 625920000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 588960000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 624120000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35160000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 590760000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 625920000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 588960000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 624120000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000226 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001210 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001159 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.016639 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.016639 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
index 084c1a30a..4ff330a09 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
@@ -510,7 +510,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
-cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
+cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing
egid=100
env=
errout=cerr
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
index 5c8d95ce9..ec0229a1c 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 4 2012 13:44:28
-gem5 started Jun 4 2012 15:14:48
+gem5 compiled Jun 28 2012 22:08:09
+gem5 started Jun 28 2012 23:13:04
gem5 executing on zizzer
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -24,4 +24,4 @@ flow value : 3080014995
info: Increasing stack size by one page.
checksum : 68389
optimal
-Exiting @ tick 67388458000 because target called exit()
+Exiting @ tick 66545720000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
index a6e1946c5..1baa4dbca 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
@@ -1,174 +1,174 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.067388 # Number of seconds simulated
-sim_ticks 67388458000 # Number of ticks simulated
-final_tick 67388458000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.066546 # Number of seconds simulated
+sim_ticks 66545720000 # Number of ticks simulated
+final_tick 66545720000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 84988 # Simulator instruction rate (inst/s)
-host_op_rate 149650 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 36250631 # Simulator tick rate (ticks/s)
-host_mem_usage 363056 # Number of bytes of host memory used
-host_seconds 1858.96 # Real time elapsed on the host
+host_inst_rate 128459 # Simulator instruction rate (inst/s)
+host_op_rate 226196 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 54107733 # Simulator tick rate (ticks/s)
+host_mem_usage 365700 # Number of bytes of host memory used
+host_seconds 1229.87 # Real time elapsed on the host
sim_insts 157988582 # Number of instructions simulated
sim_ops 278192519 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 69248 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 3838272 # Number of bytes read from this memory
-system.physmem.bytes_read::total 3907520 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 69248 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 69248 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 897536 # Number of bytes written to this memory
-system.physmem.bytes_written::total 897536 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 1082 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 59973 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 61055 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 14024 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 14024 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1027594 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 56957410 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 57985004 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1027594 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1027594 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 13318839 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 13318839 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 13318839 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1027594 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 56957410 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 71303843 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst 68352 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 1892992 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1961344 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 68352 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 68352 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 20032 # Number of bytes written to this memory
+system.physmem.bytes_written::total 20032 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 1068 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 29578 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 30646 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 313 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 313 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1027143 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 28446488 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 29473631 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1027143 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1027143 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 301026 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 301026 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 301026 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1027143 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 28446488 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 29774657 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 444 # Number of system calls
-system.cpu.numCycles 134776917 # number of cpu cycles simulated
+system.cpu.numCycles 133091441 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 36128556 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 36128556 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 1088012 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 25661198 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 25550813 # Number of BTB hits
+system.cpu.BPredUnit.lookups 36127369 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 36127369 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 1087558 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 25661122 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 25550646 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 27997413 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 196488492 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 36128556 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 25550813 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 59432634 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 8416233 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 39238726 # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles 27995643 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 196446977 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 36127369 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 25550646 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 59425857 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 8408654 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 38346383 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 27278821 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 142192 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 133966907 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.578141 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.358289 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles 123 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 27275955 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 142407 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 133058866 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.595223 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.362713 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 77274639 57.68% 57.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 2166516 1.62% 59.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 2997281 2.24% 61.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 4102912 3.06% 64.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 8026102 5.99% 70.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 5043006 3.76% 74.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2893464 2.16% 76.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1468336 1.10% 77.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 29994651 22.39% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 76373838 57.40% 57.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 2167538 1.63% 59.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 2997061 2.25% 61.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 4104688 3.08% 64.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 8024100 6.03% 70.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 5043618 3.79% 74.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2895035 2.18% 76.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1466845 1.10% 77.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 29986143 22.54% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 133966907 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.268062 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.457879 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 40465112 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 30125694 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 46506148 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 9571987 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 7297966 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 341297669 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 7297966 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 45865108 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 5065508 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 9277 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 50351191 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 25377857 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 337406380 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 13 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 3712 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 23187560 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 79157 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 414755881 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1009935094 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1009932394 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 2700 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 133058866 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.271448 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.476030 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 40459991 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 29238616 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 46513629 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 9555795 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 7290835 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 341218691 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 7290835 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 45832356 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 4342736 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 9009 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 50371616 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 25212314 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 337359064 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 16 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 3751 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 23039182 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 70135 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 414697998 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1009810700 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1009808348 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 2352 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 341010940 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 73744941 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 481 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 474 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 56192967 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 108162580 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 37173372 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 46311356 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 7909478 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 331723465 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2616 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 311412241 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 185399 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 53269773 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 92543278 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 2170 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 133966907 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.324546 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.724461 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 73687058 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 483 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 476 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 55957632 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 108146065 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 37162932 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 46284047 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 7887005 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 331670931 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2660 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 311367761 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 187011 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 53218475 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 92468498 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 2214 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 133058866 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.340075 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.723307 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 27936582 20.85% 20.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 17254518 12.88% 33.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 25564521 19.08% 52.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 31166509 23.26% 76.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 17676068 13.19% 89.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 9033591 6.74% 96.02% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 3761456 2.81% 98.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 1501105 1.12% 99.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 72557 0.05% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 27262165 20.49% 20.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 17087897 12.84% 33.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 25427949 19.11% 52.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 31141299 23.40% 75.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 17714013 13.31% 89.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 9070422 6.82% 95.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 3766330 2.83% 98.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1516401 1.14% 99.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 72390 0.05% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 133966907 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 133058866 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 23354 1.11% 1.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 1.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 1.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 1.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 1.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 1.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1960413 92.78% 93.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 129107 6.11% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 23137 1.10% 1.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 1959411 92.81% 93.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 128735 6.10% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 31371 0.01% 0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 177196652 56.90% 56.91% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 177167866 56.90% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 116 0.00% 56.91% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 103 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.91% # Type of FU issued
@@ -194,86 +194,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.91% # Ty
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 99714062 32.02% 88.93% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 34470040 11.07% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 99703270 32.02% 88.93% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 34465151 11.07% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 311412241 # Type of FU issued
-system.cpu.iq.rate 2.310575 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2112874 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.006785 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 759088710 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 385026224 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 308270248 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 952 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1427 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 314 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 313493303 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 441 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 52569930 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 311367761 # Type of FU issued
+system.cpu.iq.rate 2.339503 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2111283 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.006781 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 758091805 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 384922588 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 308230879 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 877 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 1235 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 288 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 313447268 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 405 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 52556752 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 17383192 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 98849 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 32443 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 5733621 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 17366677 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 97430 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 32398 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 5723181 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
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-system.cpu.iew.lsq.thread0.cacheBlocked 3845 # Number of times an access to memory failed due to the cache being blocked
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 7297966 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 891871 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 89086 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 331726081 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 45756 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 108162580 # Number of dispatched load instructions
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-system.cpu.iew.iewDispNonSpecInsts 476 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 224 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 43423 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 32443 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 615219 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 578970 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1194189 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 309448819 # Number of executed instructions
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+system.cpu.iew.iewUnblockCycles 29284 # Number of cycles IEW is unblocking
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system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
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-system.cpu.iew.wb_count 308270562 # cumulative count of insts written-back
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system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
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system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 157988582 # The number of committed instructions
system.cpu.commit.commitCommittedOps 278192519 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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-system.cpu.commit.committed_per_cycle::2 16849760 13.30% 69.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 12619079 9.96% 78.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 3360251 2.65% 81.62% # Number of insts commited each cycle
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-system.cpu.commit.committed_per_cycle::6 2707142 2.14% 86.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 1157073 0.91% 87.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 15858353 12.52% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 45423361 36.12% 36.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 24208560 19.25% 55.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 16905668 13.44% 68.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 12615481 10.03% 78.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 3337463 2.65% 81.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 3557456 2.83% 84.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 2707212 2.15% 86.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 1156864 0.92% 87.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 15855966 12.61% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 126668941 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 125768031 # Number of insts commited each cycle
system.cpu.commit.committedInsts 157988582 # Number of instructions committed
system.cpu.commit.committedOps 278192519 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -284,69 +284,69 @@ system.cpu.commit.branches 29309710 # Nu
system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
system.cpu.commit.int_insts 278186227 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 15858353 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 15855966 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 442540875 # The number of ROB reads
-system.cpu.rob.rob_writes 670767297 # The number of ROB writes
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-system.cpu.idleCycles 810010 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 441587755 # The number of ROB reads
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system.cpu.committedInsts 157988582 # Number of Instructions Simulated
system.cpu.committedOps 278192519 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 157988582 # Number of Instructions Simulated
-system.cpu.cpi 0.853080 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.853080 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.172223 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.172223 # IPC: Total IPC of All Threads
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-system.cpu.icache.avg_refs 24956.453797 # Average number of references to valid blocks.
+system.cpu.cpi 0.842412 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.842412 # CPI: Total CPI of All Threads
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+system.cpu.ipc_total 1.187068 # IPC: Total IPC of All Threads
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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+system.cpu.icache.ReadReq_avg_miss_latency::total 35452.890792 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 35452.890792 # average overall miss latency
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+system.cpu.icache.overall_avg_miss_latency::cpu.inst 35452.890792 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 35452.890792 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -355,94 +355,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
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system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.800000 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.800000 # miss rate for UpgradeReq accesses
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+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34218.803419 # average ReadReq miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::total 34093.111662 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -593,60 +593,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 14024 # number of writebacks
-system.cpu.l2cache.writebacks::total 14024 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1082 # number of ReadReq MSHR misses
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system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 4 # number of UpgradeReq MSHR misses
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system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 124000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 124000 # number of UpgradeReq MSHR miss cycles
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.800000 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.800000 # mshr miss rate for UpgradeReq accesses
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-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.028886 # mshr miss rate for overall accesses
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-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31067.467652 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31020.604170 # average ReadReq mshr miss latency
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31059.925094 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31028.205128 # average ReadReq mshr miss latency
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.574700 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31002.574700 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31067.467652 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31011.730279 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31012.718041 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31067.467652 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31011.730279 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31012.718041 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.500121 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31000.500121 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31059.925094 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31001.048076 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31003.099915 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31059.925094 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31001.048076 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31003.099915 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
index 96f41a3e2..4b59eaf01 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
@@ -179,7 +179,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
-cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
+cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing
egid=100
env=
errout=cerr
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
index d95343c19..894e40d36 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 4 2012 13:44:28
-gem5 started Jun 4 2012 15:22:27
+gem5 compiled Jun 28 2012 22:08:09
+gem5 started Jun 28 2012 23:17:22
gem5 executing on zizzer
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -23,4 +23,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 370010840000 because target called exit()
+Exiting @ tick 368062166000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
index bcdb996d9..896f57262 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
@@ -1,41 +1,41 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.370011 # Number of seconds simulated
-sim_ticks 370010840000 # Number of ticks simulated
-final_tick 370010840000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.368062 # Number of seconds simulated
+sim_ticks 368062166000 # Number of ticks simulated
+final_tick 368062166000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 564351 # Simulator instruction rate (inst/s)
-host_op_rate 993732 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1321716509 # Simulator tick rate (ticks/s)
-host_mem_usage 360832 # Number of bytes of host memory used
-host_seconds 279.95 # Real time elapsed on the host
+host_inst_rate 915530 # Simulator instruction rate (inst/s)
+host_op_rate 1612102 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2132888263 # Simulator tick rate (ticks/s)
+host_mem_usage 362628 # Number of bytes of host memory used
+host_seconds 172.57 # Real time elapsed on the host
sim_insts 157988583 # Number of instructions simulated
sim_ops 278192520 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 51712 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 4849088 # Number of bytes read from this memory
-system.physmem.bytes_read::total 4900800 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 1879680 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1931392 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 51712 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 51712 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 1885440 # Number of bytes written to this memory
-system.physmem.bytes_written::total 1885440 # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks 14528 # Number of bytes written to this memory
+system.physmem.bytes_written::total 14528 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 808 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 75767 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 76575 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 29460 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 29460 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 139758 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 13105259 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 13245017 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 139758 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 139758 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 5095634 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 5095634 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 5095634 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 139758 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 13105259 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 18340652 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::cpu.data 29370 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 30178 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 227 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 227 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 140498 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 5106963 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 5247461 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 140498 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 140498 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 39472 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 39472 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 39472 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 140498 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 5106963 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 5286933 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 444 # Number of system calls
-system.cpu.numCycles 740021680 # number of cpu cycles simulated
+system.cpu.numCycles 736124332 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 157988583 # Number of instructions committed
@@ -54,18 +54,18 @@ system.cpu.num_mem_refs 122219139 # nu
system.cpu.num_load_insts 90779388 # Number of load instructions
system.cpu.num_store_insts 31439751 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 740021680 # Number of busy cycles
+system.cpu.num_busy_cycles 736124332 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 24 # number of replacements
-system.cpu.icache.tagsinuse 666.191948 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 665.896557 # Cycle average of tags in use
system.cpu.icache.total_refs 217695401 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 269425.001238 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 666.191948 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.325289 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.325289 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst 665.896557 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.325145 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.325145 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 217695401 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 217695401 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 217695401 # number of demand (read+write) hits
@@ -136,14 +136,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2062733 # number of replacements
-system.cpu.dcache.tagsinuse 4076.661903 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4076.559519 # Cycle average of tags in use
system.cpu.dcache.total_refs 120152372 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 58.133678 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 126200130000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4076.661903 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.995279 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.995279 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data 4076.559519 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.995254 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.995254 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 88818730 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 88818730 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 31333642 # number of WriteReq hits
@@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 2066829 # n
system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses
system.cpu.dcache.overall_misses::total 2066829 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 28849058000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 28849058000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 3268793000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 3268793000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 32117851000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 32117851000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 32117851000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 32117851000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 27464486000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 27464486000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 2704691000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 2704691000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 30169177000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 30169177000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 30169177000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 30169177000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 90779450 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 90779450 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses)
@@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016911
system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14713.502183 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14713.502183 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30805.991952 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 30805.991952 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 15539.675029 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 15539.675029 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 15539.675029 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 15539.675029 # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14007.347301 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14007.347301 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25489.741681 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 25489.741681 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14596.842313 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14596.842313 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14596.842313 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14596.842313 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -200,8 +200,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 1437080 # number of writebacks
-system.cpu.dcache.writebacks::total 1437080 # number of writebacks
+system.cpu.dcache.writebacks::writebacks 2061794 # number of writebacks
+system.cpu.dcache.writebacks::total 2061794 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses
@@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2066829
system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22966898000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 22966898000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2950464500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 2950464500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25917362500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 25917362500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25917362500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 25917362500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21582326000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 21582326000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2386362500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 2386362500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23968688500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 23968688500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23968688500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 23968688500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses
@@ -226,65 +226,65 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911
system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11713.502183 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11713.502183 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27805.977815 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27805.977815 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12539.674303 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 12539.674303 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12539.674303 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 12539.674303 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.347301 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.347301 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22489.727544 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22489.727544 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11596.841587 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11596.841587 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11596.841587 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11596.841587 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 49212 # number of replacements
-system.cpu.l2cache.tagsinuse 18614.603260 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 3296079 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 77127 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 42.735735 # Average number of references to valid blocks.
+system.cpu.l2cache.replacements 1081 # number of replacements
+system.cpu.l2cache.tagsinuse 19721.209952 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 3991053 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 30157 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 132.342508 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 12062.804989 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 196.794797 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 6355.003474 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.368128 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.006006 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.193939 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.568073 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.data 1927411 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 1927411 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 1437080 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 1437080 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 63651 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 63651 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.data 1991062 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 1991062 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.data 1991062 # number of overall hits
-system.cpu.l2cache.overall_hits::total 1991062 # number of overall hits
+system.cpu.l2cache.occ_blocks::writebacks 19369.116114 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 209.759091 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 142.334747 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.591099 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.006401 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.004344 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.601844 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.data 1960377 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 1960377 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 2061794 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 2061794 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 77082 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 77082 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.data 2037459 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 2037459 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data 2037459 # number of overall hits
+system.cpu.l2cache.overall_hits::total 2037459 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 33309 # number of ReadReq misses
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@@ -323,41 +323,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
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