summaryrefslogtreecommitdiff
path: root/tests/long/se/10.mcf
diff options
context:
space:
mode:
Diffstat (limited to 'tests/long/se/10.mcf')
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini82
-rwxr-xr-xtests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr1
-rwxr-xr-xtests/long/se/10.mcf/ref/arm/linux/o3-timing/simout11
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt2516
-rw-r--r--tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini49
-rwxr-xr-xtests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr1
-rwxr-xr-xtests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout11
-rw-r--r--tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt1074
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini97
-rwxr-xr-xtests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr3
-rwxr-xr-xtests/long/se/10.mcf/ref/x86/linux/o3-timing/simout13
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt2102
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini50
-rwxr-xr-xtests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr1
-rwxr-xr-xtests/long/se/10.mcf/ref/x86/linux/simple-timing/simout11
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt1074
16 files changed, 3607 insertions, 3489 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
index afbdccd37..e061f70cd 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
@@ -65,7 +65,7 @@ SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
-cachePorts=200
+cacheStorePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
@@ -141,6 +141,7 @@ socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -176,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=6
@@ -193,6 +194,7 @@ response_latency=2
sequential_access=false
size=32768
system=system
+tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=8
write_buffers=16
@@ -205,15 +207,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
+tag_latency=2
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -316,38 +319,52 @@ pipelined=true
[system.cpu.fuPool.FUList2]
type=FUDesc
-children=opList
+children=opList0 opList1
count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1
-[system.cpu.fuPool.FUList2.opList]
+[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=2
pipelined=true
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemRead
+opLat=2
+pipelined=true
+
[system.cpu.fuPool.FUList3]
type=FUDesc
-children=opList
+children=opList0 opList1
count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1
-[system.cpu.fuPool.FUList3.opList]
+[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=2
pipelined=true
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemWrite
+opLat=2
+pipelined=true
+
[system.cpu.fuPool.FUList4]
type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
count=2
eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
+opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27
[system.cpu.fuPool.FUList4.opList00]
type=OpDesc
@@ -479,7 +496,7 @@ pipelined=true
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
-opLat=1
+opLat=5
pipelined=true
[system.cpu.fuPool.FUList4.opList19]
@@ -531,6 +548,20 @@ opClass=FloatMult
opLat=4
pipelined=true
+[system.cpu.fuPool.FUList4.opList26]
+type=OpDesc
+eventq_index=0
+opClass=FloatMultAcc
+opLat=5
+pipelined=true
+
+[system.cpu.fuPool.FUList4.opList27]
+type=OpDesc
+eventq_index=0
+opClass=FloatMisc
+opLat=3
+pipelined=true
+
[system.cpu.icache]
type=Cache
children=tags
@@ -538,10 +569,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=1
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=1
is_read_only=true
max_miss_count=0
mshrs=2
@@ -555,6 +586,7 @@ response_latency=1
sequential_access=false
size=32768
system=system
+tag_latency=1
tags=system.cpu.icache.tags
tgts_per_mshr=8
write_buffers=8
@@ -567,15 +599,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=1
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
+tag_latency=1
[system.cpu.interrupts]
type=ArmInterrupts
@@ -594,8 +627,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -606,8 +637,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -670,10 +699,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16
clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
+data_latency=12
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=12
is_read_only=false
max_miss_count=0
mshrs=16
@@ -687,6 +716,7 @@ response_latency=12
sequential_access=false
size=1048576
system=system
+tag_latency=12
tags=system.cpu.l2cache.tags
tgts_per_mshr=8
write_buffers=8
@@ -729,15 +759,16 @@ type=RandomRepl
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=12
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=12
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1048576
+tag_latency=12
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -773,7 +804,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=mcf mcf.in
cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
drivers=
@@ -782,14 +813,15 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/mcf
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100
-input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=55300000000
system=system
uid=100
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr
index 4184e8f67..5b248e07d 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr
@@ -1,4 +1,5 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
index 07887a4ce..b22552f23 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
@@ -3,13 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/sim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 20:52:57
-gem5 executing on e108600-lin, pid 17480
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/arm/linux/o3-timing
+gem5 compiled Apr 3 2017 17:55:48
+gem5 started Apr 3 2017 18:10:17
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 56685
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/10.mcf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I
by Andreas Loebel
@@ -26,4 +25,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 58675371500 because target called exit()
+Exiting @ tick 58521086000 because exiting with last active thread context
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
index 57821b2e6..7a51f9c37 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -1,1262 +1,1262 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.058521 # Number of seconds simulated
-sim_ticks 58521086000 # Number of ticks simulated
-final_tick 58521086000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 243648 # Simulator instruction rate (inst/s)
-host_op_rate 244862 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 157397000 # Simulator tick rate (ticks/s)
-host_mem_usage 492140 # Number of bytes of host memory used
-host_seconds 371.81 # Real time elapsed on the host
-sim_insts 90589799 # Number of instructions simulated
-sim_ops 91041030 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 44736 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 220224 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher 921920 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1186880 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 44736 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 44736 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4736 # Number of bytes written to this memory
-system.physmem.bytes_written::total 4736 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 699 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 3441 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher 14405 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 18545 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 74 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 74 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 764442 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3763156 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher 15753638 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 20281237 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 764442 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 764442 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 80928 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 80928 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 80928 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 764442 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3763156 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher 15753638 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 20362165 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 18546 # Number of read requests accepted
-system.physmem.writeReqs 74 # Number of write requests accepted
-system.physmem.readBursts 18546 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 74 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 1183360 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 3584 # Total number of bytes read from write queue
-system.physmem.bytesWritten 3328 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 1186944 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 4736 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 56 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 3297 # Per bank write bursts
-system.physmem.perBankRdBursts::1 920 # Per bank write bursts
-system.physmem.perBankRdBursts::2 949 # Per bank write bursts
-system.physmem.perBankRdBursts::3 1031 # Per bank write bursts
-system.physmem.perBankRdBursts::4 1067 # Per bank write bursts
-system.physmem.perBankRdBursts::5 1119 # Per bank write bursts
-system.physmem.perBankRdBursts::6 1093 # Per bank write bursts
-system.physmem.perBankRdBursts::7 1097 # Per bank write bursts
-system.physmem.perBankRdBursts::8 1024 # Per bank write bursts
-system.physmem.perBankRdBursts::9 961 # Per bank write bursts
-system.physmem.perBankRdBursts::10 934 # Per bank write bursts
-system.physmem.perBankRdBursts::11 899 # Per bank write bursts
-system.physmem.perBankRdBursts::12 902 # Per bank write bursts
-system.physmem.perBankRdBursts::13 895 # Per bank write bursts
-system.physmem.perBankRdBursts::14 1399 # Per bank write bursts
-system.physmem.perBankRdBursts::15 903 # Per bank write bursts
-system.physmem.perBankWrBursts::0 1 # Per bank write bursts
-system.physmem.perBankWrBursts::1 0 # Per bank write bursts
-system.physmem.perBankWrBursts::2 2 # Per bank write bursts
-system.physmem.perBankWrBursts::3 0 # Per bank write bursts
-system.physmem.perBankWrBursts::4 1 # Per bank write bursts
-system.physmem.perBankWrBursts::5 14 # Per bank write bursts
-system.physmem.perBankWrBursts::6 9 # Per bank write bursts
-system.physmem.perBankWrBursts::7 3 # Per bank write bursts
-system.physmem.perBankWrBursts::8 1 # Per bank write bursts
-system.physmem.perBankWrBursts::9 0 # Per bank write bursts
-system.physmem.perBankWrBursts::10 2 # Per bank write bursts
-system.physmem.perBankWrBursts::11 0 # Per bank write bursts
-system.physmem.perBankWrBursts::12 1 # Per bank write bursts
-system.physmem.perBankWrBursts::13 12 # Per bank write bursts
-system.physmem.perBankWrBursts::14 5 # Per bank write bursts
-system.physmem.perBankWrBursts::15 1 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 58521077500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 0 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 18546 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 0 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 74 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 12593 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 3390 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 500 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 409 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 319 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 301 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 297 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 299 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 279 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 103 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 4 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 3004 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 394.652463 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 214.589229 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 405.543781 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 893 29.73% 29.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 965 32.12% 61.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 89 2.96% 64.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 63 2.10% 66.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 67 2.23% 69.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 66 2.20% 71.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 53 1.76% 73.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 47 1.56% 74.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 761 25.33% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 3004 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 3 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 6161.333333 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean 2123.401593 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 8586.829993 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511 1 33.33% 33.33% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-2559 1 33.33% 66.67% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::15872-16383 1 33.33% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 3 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 3 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.333333 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.306995 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 1.154701 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 1 33.33% 33.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 2 66.67% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 3 # Writes before turning the bus around for reads
-system.physmem.totQLat 837911216 # Total ticks spent queuing
-system.physmem.totMemAccLat 1184598716 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 92450000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 45316.99 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 64066.99 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 20.22 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 0.06 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 20.28 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 0.08 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.16 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.16 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 13.38 # Average write queue length when enqueuing
-system.physmem.readRowHits 15512 # Number of row buffer hits during reads
-system.physmem.writeRowHits 18 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.89 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 25.71 # Row buffer hit rate for writes
-system.physmem.avgGap 3142915.01 # Average gap between requests
-system.physmem.pageHitRate 83.67 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 16243500 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 8614650 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 75484080 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 156600 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 1895549760.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 464945010 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 99199680 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 4173482430 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 3272736480 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 9883191315 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 19894073865 # Total energy per rank (pJ)
-system.physmem_0.averagePower 339.947098 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 57233116090 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 194944250 # Time in different power states
-system.physmem_0.memoryStateTime::REF 806364000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 39558059500 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 8522710566 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 286661660 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 9152346024 # Time in different power states
-system.physmem_1.actEnergy 5255040 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 2785530 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 56527380 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 114840 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 247699920.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 125328180 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 13397280 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 772336890 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 242624160 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 13451278005 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 14917407225 # Total energy per rank (pJ)
-system.physmem_1.averagePower 254.906533 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 58211272096 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 21634250 # Time in different power states
-system.physmem_1.memoryStateTime::REF 105218000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 55885668250 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 631842954 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 182961654 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 1693760892 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 28121660 # Number of BP lookups
-system.cpu.branchPred.condPredicted 23134709 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 844714 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 11731332 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 11630363 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 99.139322 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 80725 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 95 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 28301 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 25845 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 2456 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 243 # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks 0 # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks 0 # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 442 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 58521086000 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 117042173 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 755365 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 134380549 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 28121660 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 11736933 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 115370240 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1692793 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 848 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.IcacheWaitRetryStallCycles 1033 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 32086744 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 572 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 116973882 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.154260 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 1.318237 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 59688776 51.03% 51.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 13868271 11.86% 62.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 9100495 7.78% 70.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 34316340 29.34% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 116973882 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.240269 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.148138 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 8865418 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 65026599 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 32710680 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 9589004 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 782181 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 9831266 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 64876 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 113761457 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 2108425 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 782181 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 15316274 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 50229704 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 114341 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 35119945 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 15411437 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 110456918 # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts 1289549 # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents 11149602 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1576334 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 2138216 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 510190 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 129202611 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 481340709 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 118978784 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 633 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 21889692 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 4408 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 4400 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 21529051 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 26813393 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 5308956 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 540635 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 272789 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 109383305 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 8282 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 101253910 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 993650 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 18350557 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 40868291 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 64 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 116973882 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.865611 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 0.989909 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 55502940 47.45% 47.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 31207963 26.68% 74.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 21948493 18.76% 92.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 7109305 6.08% 98.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 1204859 1.03% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 322 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 116973882 # Number of insts issued each cycle
-system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 9836731 48.84% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 51 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMisc 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 19 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 9605308 47.69% 96.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 697155 3.46% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemRead 3 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemWrite 24 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 71822499 70.93% 70.93% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 10678 0.01% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 77 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 184 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 24343876 24.04% 94.99% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 5076562 5.01% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemRead 8 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemWrite 22 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 101253910 # Type of FU issued
-system.cpu.iq.rate 0.865106 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 20139291 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.198899 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 340613998 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 127742533 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 99568159 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 645 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 896 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 147 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 121392865 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 336 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 289487 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 4337482 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 2085 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 1323 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 564112 # Number of stores squashed
-system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 7586 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 131115 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 782181 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 8303656 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 706645 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 109404410 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 26813393 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 5308956 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 4394 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 183005 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 362995 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 1323 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 354101 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 451870 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 805971 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 100068536 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 23799476 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1185374 # Number of squashed instructions skipped in execute
-system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 12823 # number of nop insts executed
-system.cpu.iew.exec_refs 28747002 # number of memory reference insts executed
-system.cpu.iew.exec_branches 20644390 # Number of branches executed
-system.cpu.iew.exec_stores 4947526 # Number of stores executed
-system.cpu.iew.exec_rate 0.854978 # Inst execution rate
-system.cpu.iew.wb_sent 99653444 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 99568306 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 59603520 # num instructions producing a value
-system.cpu.iew.wb_consumers 95472454 # num instructions consuming a value
-system.cpu.iew.wb_rate 0.850705 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.624301 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 17204380 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 780499 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 114317449 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.796498 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.736161 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 77973404 68.21% 68.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 18552037 16.23% 84.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 7135846 6.24% 90.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 3439776 3.01% 93.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1654311 1.45% 95.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 545783 0.48% 95.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 692568 0.61% 96.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 180777 0.16% 96.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 4142947 3.62% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 114317449 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 90602408 # Number of instructions committed
-system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed
-system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27220755 # Number of memory references committed
-system.cpu.commit.loads 22475911 # Number of loads committed
-system.cpu.commit.membars 3888 # Number of memory barriers committed
-system.cpu.commit.branches 18732305 # Number of branches committed
-system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 72326352 # Number of committed integer instructions.
-system.cpu.commit.function_calls 56148 # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 63822387 70.09% 70.09% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMisc 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 22475905 24.68% 94.79% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 4744822 5.21% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemRead 6 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemWrite 22 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction
-system.cpu.commit.bw_lim_events 4142947 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 218426787 # The number of ROB reads
-system.cpu.rob.rob_writes 219173124 # The number of ROB writes
-system.cpu.timesIdled 593 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 68291 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 90589799 # Number of Instructions Simulated
-system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 1.292002 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.292002 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.773993 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.773993 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 108095256 # number of integer regfile reads
-system.cpu.int_regfile_writes 58597145 # number of integer regfile writes
-system.cpu.fp_regfile_reads 58 # number of floating regfile reads
-system.cpu.fp_regfile_writes 127 # number of floating regfile writes
-system.cpu.cc_regfile_reads 368871207 # number of cc regfile reads
-system.cpu.cc_regfile_writes 58517884 # number of cc regfile writes
-system.cpu.misc_regfile_reads 28439348 # number of misc regfile reads
-system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 5470632 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.768178 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 18243100 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 5471144 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 3.334421 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 38187500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.768178 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.999547 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.999547 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 327 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 61896540 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 61896540 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 13880582 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 13880582 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 4354214 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 4354214 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 3873 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 18234796 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 18234796 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 18235318 # number of overall hits
-system.cpu.dcache.overall_hits::total 18235318 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 9588832 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 9588832 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 380767 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 380767 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 14 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 14 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 9969599 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 9969599 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 9969606 # number of overall misses
-system.cpu.dcache.overall_misses::total 9969606 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 89393317500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 89393317500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 4103772083 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 4103772083 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 302000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 302000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 93497089583 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 93497089583 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 93497089583 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 93497089583 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 23469414 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 23469414 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total 529 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 28204395 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 28204395 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 28204924 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 28204924 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408567 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.408567 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080416 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.080416 # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.353477 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.353477 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.353470 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.353470 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9322.649255 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 9322.649255 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10777.646390 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 10777.646390 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21571.428571 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21571.428571 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 9378.219684 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 9378.219684 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 9378.213099 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 9378.213099 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 331670 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 131340 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 121646 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 12838 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.726518 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 10.230566 # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks 5470632 # number of writebacks
-system.cpu.dcache.writebacks::total 5470632 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4340269 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 4340269 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158185 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 158185 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 4498454 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 4498454 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 4498454 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 4498454 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248563 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 5248563 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222582 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 222582 # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 5471145 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 5471145 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 5471149 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 5471149 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43818706500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 43818706500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2301862483 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 2301862483 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 235500 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 235500 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46120568983 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 46120568983 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46120804483 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 46120804483 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223634 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223634 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047008 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047008 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193982 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.193982 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193979 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.193979 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8348.705446 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8348.705446 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10341.638061 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10341.638061 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 58875 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 58875 # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8429.783708 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 8429.783708 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8429.820589 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 8429.820589 # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements 449 # number of replacements
-system.cpu.icache.tags.tagsinuse 426.857560 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 32085580 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 907 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 35375.501654 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 426.857560 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.833706 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.833706 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 458 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 333 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.894531 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 64174375 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 64174375 # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst 32085580 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 32085580 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 32085580 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 32085580 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 32085580 # number of overall hits
-system.cpu.icache.overall_hits::total 32085580 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses
-system.cpu.icache.overall_misses::total 1154 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 81624480 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 81624480 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 81624480 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 81624480 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 81624480 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 81624480 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 32086734 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 32086734 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 32086734 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 32086734 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 32086734 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 32086734 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000036 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000036 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000036 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70731.785095 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 70731.785095 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 70731.785095 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 70731.785095 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 70731.785095 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 70731.785095 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 21770 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 1853 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 229 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 7 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 95.065502 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 264.714286 # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks 449 # number of writebacks
-system.cpu.icache.writebacks::total 449 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 246 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 246 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 246 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 246 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 246 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 246 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 908 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 908 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 908 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 908 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 908 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 908 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61609984 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 61609984 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61609984 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 61609984 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61609984 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 61609984 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67852.405286 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67852.405286 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67852.405286 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 67852.405286 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67852.405286 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 67852.405286 # average overall mshr miss latency
-system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.prefetcher.num_hwpf_issued 4987667 # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified 5295978 # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit 268023 # number of redundant prefetches already in prefetch queue
-system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
-system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage 14076270 # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements 99 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 11218.637670 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 5292117 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 14656 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 361.088769 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 11151.920658 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 66.717012 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.680659 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004072 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.684731 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022 67 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 14490 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4 56 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 454 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3440 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9642 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 120 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 834 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022 0.004089 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884399 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 180525307 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 180525307 # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks 5460197 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total 5460197 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks 7956 # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total 7956 # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 225753 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 225753 # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 207 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total 207 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5241769 # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total 5241769 # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 207 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 5467522 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 5467729 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 207 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 5467522 # number of overall hits
-system.cpu.l2cache.overall_hits::total 5467729 # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 499 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 499 # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 701 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total 701 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data 3123 # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total 3123 # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 701 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 3622 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 4323 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 701 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 3622 # number of overall misses
-system.cpu.l2cache.overall_misses::total 4323 # number of overall misses
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 105500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total 105500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 66196000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 66196000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 59307500 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total 59307500 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 617300000 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 617300000 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 59307500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 683496000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 742803500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 59307500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 683496000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 742803500 # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks 5460197 # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total 5460197 # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks 7956 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total 7956 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 226252 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 226252 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 908 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total 908 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244892 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total 5244892 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 908 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 5471144 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 5472052 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 908 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 5471144 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 5472052 # number of overall (read+write) accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002206 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.002206 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.772026 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.772026 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000595 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000595 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.772026 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.000662 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.000790 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.772026 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.000662 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.000790 # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21100 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21100 # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132657.314629 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132657.314629 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84604.136947 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84604.136947 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 197662.504003 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 197662.504003 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84604.136947 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 188706.791828 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 171825.931066 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84604.136947 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 188706.791828 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 171825.931066 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.unused_prefetches 1 # number of HardPF blocks evicted w/o reference
-system.cpu.l2cache.writebacks::writebacks 74 # number of writebacks
-system.cpu.l2cache.writebacks::total 74 # number of writebacks
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 158 # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total 158 # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 22 # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total 22 # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 180 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 181 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 180 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 181 # number of overall MSHR hits
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316332 # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total 316332 # number of HardPFReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 341 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 341 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 700 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 700 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 3101 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 3101 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 700 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 3442 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 4142 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 700 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 3442 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316332 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 320474 # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1095451507 # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1095451507 # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 75500 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 75500 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 46761500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 46761500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 55046500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 55046500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 590692000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 590692000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 55046500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 637453500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 692500000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 55046500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 637453500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1095451507 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 1787951507 # number of overall MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
-system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001507 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001507 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.770925 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.770925 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000591 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000591 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.770925 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000629 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.000757 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.770925 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000629 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.058566 # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3462.980372 # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3462.980372 # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15100 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15100 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 137130.498534 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 137130.498534 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 78637.857143 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 78637.857143 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 190484.359884 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 190484.359884 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 78637.857143 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185198.576409 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167189.763399 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 78637.857143 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185198.576409 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3462.980372 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 5579.084441 # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests 10943138 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471099 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2928 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 301927 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 301926 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp 5245799 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 5460271 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 10884 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 25 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq 318221 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 226252 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 226252 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 908 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244892 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2264 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412936 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 16415200 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86784 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274048 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 700360832 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 318326 # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic 5120 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 5790377 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.052651 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.223337 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 5485509 94.73% 94.73% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 304867 5.27% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 5790377 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 10942650026 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 18.7 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 9032 # Layer occupancy (ticks)
-system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1362995 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 8206721993 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 14.0 # Layer utilization (%)
-system.membus.snoop_filter.tot_requests 18651 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 3037 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp 18205 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 74 # Transaction distribution
-system.membus.trans_dist::CleanEvict 25 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 6 # Transaction distribution
-system.membus.trans_dist::ReadExReq 340 # Transaction distribution
-system.membus.trans_dist::ReadExResp 340 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 18206 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37196 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 37196 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1191616 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 1191616 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 18552 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 18552 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 18552 # Request fanout histogram
-system.membus.reqLayer0.occupancy 29380556 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer1.occupancy 97369032 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
+sim_seconds 0.058521
+sim_ticks 58521086000
+final_tick 58521086000
+sim_freq 1000000000000
+host_inst_rate 103970
+host_op_rate 104488
+host_tick_rate 67164623
+host_mem_usage 503044
+host_seconds 871.31
+sim_insts 90589799
+sim_ops 91041030
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.physmem.bytes_read::cpu.inst 44736
+system.physmem.bytes_read::cpu.data 220224
+system.physmem.bytes_read::cpu.l2cache.prefetcher 921920
+system.physmem.bytes_read::total 1186880
+system.physmem.bytes_inst_read::cpu.inst 44736
+system.physmem.bytes_inst_read::total 44736
+system.physmem.bytes_written::writebacks 4736
+system.physmem.bytes_written::total 4736
+system.physmem.num_reads::cpu.inst 699
+system.physmem.num_reads::cpu.data 3441
+system.physmem.num_reads::cpu.l2cache.prefetcher 14405
+system.physmem.num_reads::total 18545
+system.physmem.num_writes::writebacks 74
+system.physmem.num_writes::total 74
+system.physmem.bw_read::cpu.inst 764442
+system.physmem.bw_read::cpu.data 3763156
+system.physmem.bw_read::cpu.l2cache.prefetcher 15753638
+system.physmem.bw_read::total 20281237
+system.physmem.bw_inst_read::cpu.inst 764442
+system.physmem.bw_inst_read::total 764442
+system.physmem.bw_write::writebacks 80928
+system.physmem.bw_write::total 80928
+system.physmem.bw_total::writebacks 80928
+system.physmem.bw_total::cpu.inst 764442
+system.physmem.bw_total::cpu.data 3763156
+system.physmem.bw_total::cpu.l2cache.prefetcher 15753638
+system.physmem.bw_total::total 20362165
+system.physmem.readReqs 18546
+system.physmem.writeReqs 74
+system.physmem.readBursts 18546
+system.physmem.writeBursts 74
+system.physmem.bytesReadDRAM 1183360
+system.physmem.bytesReadWrQ 3584
+system.physmem.bytesWritten 3328
+system.physmem.bytesReadSys 1186944
+system.physmem.bytesWrittenSys 4736
+system.physmem.servicedByWrQ 56
+system.physmem.mergedWrBursts 4
+system.physmem.neitherReadNorWriteReqs 0
+system.physmem.perBankRdBursts::0 3297
+system.physmem.perBankRdBursts::1 920
+system.physmem.perBankRdBursts::2 949
+system.physmem.perBankRdBursts::3 1031
+system.physmem.perBankRdBursts::4 1067
+system.physmem.perBankRdBursts::5 1119
+system.physmem.perBankRdBursts::6 1093
+system.physmem.perBankRdBursts::7 1097
+system.physmem.perBankRdBursts::8 1024
+system.physmem.perBankRdBursts::9 961
+system.physmem.perBankRdBursts::10 934
+system.physmem.perBankRdBursts::11 899
+system.physmem.perBankRdBursts::12 902
+system.physmem.perBankRdBursts::13 895
+system.physmem.perBankRdBursts::14 1399
+system.physmem.perBankRdBursts::15 903
+system.physmem.perBankWrBursts::0 1
+system.physmem.perBankWrBursts::1 0
+system.physmem.perBankWrBursts::2 2
+system.physmem.perBankWrBursts::3 0
+system.physmem.perBankWrBursts::4 1
+system.physmem.perBankWrBursts::5 14
+system.physmem.perBankWrBursts::6 9
+system.physmem.perBankWrBursts::7 3
+system.physmem.perBankWrBursts::8 1
+system.physmem.perBankWrBursts::9 0
+system.physmem.perBankWrBursts::10 2
+system.physmem.perBankWrBursts::11 0
+system.physmem.perBankWrBursts::12 1
+system.physmem.perBankWrBursts::13 12
+system.physmem.perBankWrBursts::14 5
+system.physmem.perBankWrBursts::15 1
+system.physmem.numRdRetry 0
+system.physmem.numWrRetry 0
+system.physmem.totGap 58521077500
+system.physmem.readPktSize::0 0
+system.physmem.readPktSize::1 0
+system.physmem.readPktSize::2 0
+system.physmem.readPktSize::3 0
+system.physmem.readPktSize::4 0
+system.physmem.readPktSize::5 0
+system.physmem.readPktSize::6 18546
+system.physmem.writePktSize::0 0
+system.physmem.writePktSize::1 0
+system.physmem.writePktSize::2 0
+system.physmem.writePktSize::3 0
+system.physmem.writePktSize::4 0
+system.physmem.writePktSize::5 0
+system.physmem.writePktSize::6 74
+system.physmem.rdQLenPdf::0 12593
+system.physmem.rdQLenPdf::1 3390
+system.physmem.rdQLenPdf::2 500
+system.physmem.rdQLenPdf::3 409
+system.physmem.rdQLenPdf::4 319
+system.physmem.rdQLenPdf::5 301
+system.physmem.rdQLenPdf::6 297
+system.physmem.rdQLenPdf::7 299
+system.physmem.rdQLenPdf::8 279
+system.physmem.rdQLenPdf::9 103
+system.physmem.rdQLenPdf::10 0
+system.physmem.rdQLenPdf::11 0
+system.physmem.rdQLenPdf::12 0
+system.physmem.rdQLenPdf::13 0
+system.physmem.rdQLenPdf::14 0
+system.physmem.rdQLenPdf::15 0
+system.physmem.rdQLenPdf::16 0
+system.physmem.rdQLenPdf::17 0
+system.physmem.rdQLenPdf::18 0
+system.physmem.rdQLenPdf::19 0
+system.physmem.rdQLenPdf::20 0
+system.physmem.rdQLenPdf::21 0
+system.physmem.rdQLenPdf::22 0
+system.physmem.rdQLenPdf::23 0
+system.physmem.rdQLenPdf::24 0
+system.physmem.rdQLenPdf::25 0
+system.physmem.rdQLenPdf::26 0
+system.physmem.rdQLenPdf::27 0
+system.physmem.rdQLenPdf::28 0
+system.physmem.rdQLenPdf::29 0
+system.physmem.rdQLenPdf::30 0
+system.physmem.rdQLenPdf::31 0
+system.physmem.wrQLenPdf::0 1
+system.physmem.wrQLenPdf::1 1
+system.physmem.wrQLenPdf::2 1
+system.physmem.wrQLenPdf::3 1
+system.physmem.wrQLenPdf::4 1
+system.physmem.wrQLenPdf::5 1
+system.physmem.wrQLenPdf::6 1
+system.physmem.wrQLenPdf::7 1
+system.physmem.wrQLenPdf::8 1
+system.physmem.wrQLenPdf::9 1
+system.physmem.wrQLenPdf::10 1
+system.physmem.wrQLenPdf::11 1
+system.physmem.wrQLenPdf::12 1
+system.physmem.wrQLenPdf::13 1
+system.physmem.wrQLenPdf::14 1
+system.physmem.wrQLenPdf::15 3
+system.physmem.wrQLenPdf::16 3
+system.physmem.wrQLenPdf::17 4
+system.physmem.wrQLenPdf::18 3
+system.physmem.wrQLenPdf::19 3
+system.physmem.wrQLenPdf::20 3
+system.physmem.wrQLenPdf::21 3
+system.physmem.wrQLenPdf::22 3
+system.physmem.wrQLenPdf::23 3
+system.physmem.wrQLenPdf::24 3
+system.physmem.wrQLenPdf::25 3
+system.physmem.wrQLenPdf::26 3
+system.physmem.wrQLenPdf::27 3
+system.physmem.wrQLenPdf::28 3
+system.physmem.wrQLenPdf::29 3
+system.physmem.wrQLenPdf::30 3
+system.physmem.wrQLenPdf::31 3
+system.physmem.wrQLenPdf::32 3
+system.physmem.wrQLenPdf::33 0
+system.physmem.wrQLenPdf::34 0
+system.physmem.wrQLenPdf::35 0
+system.physmem.wrQLenPdf::36 0
+system.physmem.wrQLenPdf::37 0
+system.physmem.wrQLenPdf::38 0
+system.physmem.wrQLenPdf::39 0
+system.physmem.wrQLenPdf::40 0
+system.physmem.wrQLenPdf::41 0
+system.physmem.wrQLenPdf::42 0
+system.physmem.wrQLenPdf::43 0
+system.physmem.wrQLenPdf::44 0
+system.physmem.wrQLenPdf::45 0
+system.physmem.wrQLenPdf::46 0
+system.physmem.wrQLenPdf::47 0
+system.physmem.wrQLenPdf::48 0
+system.physmem.wrQLenPdf::49 0
+system.physmem.wrQLenPdf::50 0
+system.physmem.wrQLenPdf::51 0
+system.physmem.wrQLenPdf::52 0
+system.physmem.wrQLenPdf::53 0
+system.physmem.wrQLenPdf::54 0
+system.physmem.wrQLenPdf::55 0
+system.physmem.wrQLenPdf::56 0
+system.physmem.wrQLenPdf::57 0
+system.physmem.wrQLenPdf::58 0
+system.physmem.wrQLenPdf::59 0
+system.physmem.wrQLenPdf::60 0
+system.physmem.wrQLenPdf::61 0
+system.physmem.wrQLenPdf::62 0
+system.physmem.wrQLenPdf::63 0
+system.physmem.bytesPerActivate::samples 3004
+system.physmem.bytesPerActivate::mean 394.652463
+system.physmem.bytesPerActivate::gmean 214.589229
+system.physmem.bytesPerActivate::stdev 405.543781
+system.physmem.bytesPerActivate::0-127 893 29.73% 29.73%
+system.physmem.bytesPerActivate::128-255 965 32.12% 61.85%
+system.physmem.bytesPerActivate::256-383 89 2.96% 64.81%
+system.physmem.bytesPerActivate::384-511 63 2.10% 66.91%
+system.physmem.bytesPerActivate::512-639 67 2.23% 69.14%
+system.physmem.bytesPerActivate::640-767 66 2.20% 71.34%
+system.physmem.bytesPerActivate::768-895 53 1.76% 73.10%
+system.physmem.bytesPerActivate::896-1023 47 1.56% 74.67%
+system.physmem.bytesPerActivate::1024-1151 761 25.33% 100.00%
+system.physmem.bytesPerActivate::total 3004
+system.physmem.rdPerTurnAround::samples 3
+system.physmem.rdPerTurnAround::mean 6161.333333
+system.physmem.rdPerTurnAround::gmean 2123.401593
+system.physmem.rdPerTurnAround::stdev 8586.829993
+system.physmem.rdPerTurnAround::0-511 1 33.33% 33.33%
+system.physmem.rdPerTurnAround::2048-2559 1 33.33% 66.67%
+system.physmem.rdPerTurnAround::15872-16383 1 33.33% 100.00%
+system.physmem.rdPerTurnAround::total 3
+system.physmem.wrPerTurnAround::samples 3
+system.physmem.wrPerTurnAround::mean 17.333333
+system.physmem.wrPerTurnAround::gmean 17.306995
+system.physmem.wrPerTurnAround::stdev 1.154701
+system.physmem.wrPerTurnAround::16 1 33.33% 33.33%
+system.physmem.wrPerTurnAround::18 2 66.67% 100.00%
+system.physmem.wrPerTurnAround::total 3
+system.physmem.totQLat 837911216
+system.physmem.totMemAccLat 1184598716
+system.physmem.totBusLat 92450000
+system.physmem.avgQLat 45316.99
+system.physmem.avgBusLat 5000.00
+system.physmem.avgMemAccLat 64066.99
+system.physmem.avgRdBW 20.22
+system.physmem.avgWrBW 0.06
+system.physmem.avgRdBWSys 20.28
+system.physmem.avgWrBWSys 0.08
+system.physmem.peakBW 12800.00
+system.physmem.busUtil 0.16
+system.physmem.busUtilRead 0.16
+system.physmem.busUtilWrite 0.00
+system.physmem.avgRdQLen 1.04
+system.physmem.avgWrQLen 13.38
+system.physmem.readRowHits 15512
+system.physmem.writeRowHits 18
+system.physmem.readRowHitRate 83.89
+system.physmem.writeRowHitRate 25.71
+system.physmem.avgGap 3142915.01
+system.physmem.pageHitRate 83.67
+system.physmem_0.actEnergy 16243500
+system.physmem_0.preEnergy 8614650
+system.physmem_0.readEnergy 75484080
+system.physmem_0.writeEnergy 156600
+system.physmem_0.refreshEnergy 1895549760.000000
+system.physmem_0.actBackEnergy 464945010
+system.physmem_0.preBackEnergy 99199680
+system.physmem_0.actPowerDownEnergy 4173482430
+system.physmem_0.prePowerDownEnergy 3272736480
+system.physmem_0.selfRefreshEnergy 9883191315
+system.physmem_0.totalEnergy 19894073865
+system.physmem_0.averagePower 339.947098
+system.physmem_0.totalIdleTime 57233116090
+system.physmem_0.memoryStateTime::IDLE 194944250
+system.physmem_0.memoryStateTime::REF 806364000
+system.physmem_0.memoryStateTime::SREF 39558059500
+system.physmem_0.memoryStateTime::PRE_PDN 8522710566
+system.physmem_0.memoryStateTime::ACT 286661660
+system.physmem_0.memoryStateTime::ACT_PDN 9152346024
+system.physmem_1.actEnergy 5255040
+system.physmem_1.preEnergy 2785530
+system.physmem_1.readEnergy 56527380
+system.physmem_1.writeEnergy 114840
+system.physmem_1.refreshEnergy 247699920.000000
+system.physmem_1.actBackEnergy 125328180
+system.physmem_1.preBackEnergy 13397280
+system.physmem_1.actPowerDownEnergy 772336890
+system.physmem_1.prePowerDownEnergy 242624160
+system.physmem_1.selfRefreshEnergy 13451278005
+system.physmem_1.totalEnergy 14917407225
+system.physmem_1.averagePower 254.906533
+system.physmem_1.totalIdleTime 58211272096
+system.physmem_1.memoryStateTime::IDLE 21634250
+system.physmem_1.memoryStateTime::REF 105218000
+system.physmem_1.memoryStateTime::SREF 55885668250
+system.physmem_1.memoryStateTime::PRE_PDN 631842954
+system.physmem_1.memoryStateTime::ACT 182961654
+system.physmem_1.memoryStateTime::ACT_PDN 1693760892
+system.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.branchPred.lookups 28121660
+system.cpu.branchPred.condPredicted 23134709
+system.cpu.branchPred.condIncorrect 844714
+system.cpu.branchPred.BTBLookups 11731332
+system.cpu.branchPred.BTBHits 11630363
+system.cpu.branchPred.BTBCorrect 0
+system.cpu.branchPred.BTBHitPct 99.139322
+system.cpu.branchPred.usedRAS 80725
+system.cpu.branchPred.RASInCorrect 95
+system.cpu.branchPred.indirectLookups 28301
+system.cpu.branchPred.indirectHits 25845
+system.cpu.branchPred.indirectMisses 2456
+system.cpu.branchPredindirectMispredicted 243
+system.cpu_clk_domain.clock 500
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0
+system.cpu.dstage2_mmu.stage2_tlb.write_hits 0
+system.cpu.dstage2_mmu.stage2_tlb.write_misses 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
+system.cpu.dstage2_mmu.stage2_tlb.hits 0
+system.cpu.dstage2_mmu.stage2_tlb.misses 0
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.dtb.walker.walks 0
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.dtb.walker.walkRequestOrigin::total 0
+system.cpu.dtb.inst_hits 0
+system.cpu.dtb.inst_misses 0
+system.cpu.dtb.read_hits 0
+system.cpu.dtb.read_misses 0
+system.cpu.dtb.write_hits 0
+system.cpu.dtb.write_misses 0
+system.cpu.dtb.flush_tlb 0
+system.cpu.dtb.flush_tlb_mva 0
+system.cpu.dtb.flush_tlb_mva_asid 0
+system.cpu.dtb.flush_tlb_asid 0
+system.cpu.dtb.flush_entries 0
+system.cpu.dtb.align_faults 0
+system.cpu.dtb.prefetch_faults 0
+system.cpu.dtb.domain_faults 0
+system.cpu.dtb.perms_faults 0
+system.cpu.dtb.read_accesses 0
+system.cpu.dtb.write_accesses 0
+system.cpu.dtb.inst_accesses 0
+system.cpu.dtb.hits 0
+system.cpu.dtb.misses 0
+system.cpu.dtb.accesses 0
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.istage2_mmu.stage2_tlb.walker.walks 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0
+system.cpu.istage2_mmu.stage2_tlb.inst_misses 0
+system.cpu.istage2_mmu.stage2_tlb.read_hits 0
+system.cpu.istage2_mmu.stage2_tlb.read_misses 0
+system.cpu.istage2_mmu.stage2_tlb.write_hits 0
+system.cpu.istage2_mmu.stage2_tlb.write_misses 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0
+system.cpu.istage2_mmu.stage2_tlb.flush_entries 0
+system.cpu.istage2_mmu.stage2_tlb.align_faults 0
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0
+system.cpu.istage2_mmu.stage2_tlb.domain_faults 0
+system.cpu.istage2_mmu.stage2_tlb.perms_faults 0
+system.cpu.istage2_mmu.stage2_tlb.read_accesses 0
+system.cpu.istage2_mmu.stage2_tlb.write_accesses 0
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
+system.cpu.istage2_mmu.stage2_tlb.hits 0
+system.cpu.istage2_mmu.stage2_tlb.misses 0
+system.cpu.istage2_mmu.stage2_tlb.accesses 0
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.itb.walker.walks 0
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.itb.walker.walkRequestOrigin::total 0
+system.cpu.itb.inst_hits 0
+system.cpu.itb.inst_misses 0
+system.cpu.itb.read_hits 0
+system.cpu.itb.read_misses 0
+system.cpu.itb.write_hits 0
+system.cpu.itb.write_misses 0
+system.cpu.itb.flush_tlb 0
+system.cpu.itb.flush_tlb_mva 0
+system.cpu.itb.flush_tlb_mva_asid 0
+system.cpu.itb.flush_tlb_asid 0
+system.cpu.itb.flush_entries 0
+system.cpu.itb.align_faults 0
+system.cpu.itb.prefetch_faults 0
+system.cpu.itb.domain_faults 0
+system.cpu.itb.perms_faults 0
+system.cpu.itb.read_accesses 0
+system.cpu.itb.write_accesses 0
+system.cpu.itb.inst_accesses 0
+system.cpu.itb.hits 0
+system.cpu.itb.misses 0
+system.cpu.itb.accesses 0
+system.cpu.workload.numSyscalls 442
+system.cpu.pwrStateResidencyTicks::ON 58521086000
+system.cpu.numCycles 117042173
+system.cpu.numWorkItemsStarted 0
+system.cpu.numWorkItemsCompleted 0
+system.cpu.fetch.icacheStallCycles 755365
+system.cpu.fetch.Insts 134380549
+system.cpu.fetch.Branches 28121660
+system.cpu.fetch.predictedBranches 11736933
+system.cpu.fetch.Cycles 115370240
+system.cpu.fetch.SquashCycles 1692792
+system.cpu.fetch.MiscStallCycles 848
+system.cpu.fetch.IcacheWaitRetryStallCycles 1033
+system.cpu.fetch.CacheLines 32086744
+system.cpu.fetch.IcacheSquashes 572
+system.cpu.fetch.rateDist::samples 116973882
+system.cpu.fetch.rateDist::mean 1.154260
+system.cpu.fetch.rateDist::stdev 1.318237
+system.cpu.fetch.rateDist::underflows 0 0.00% 0.00%
+system.cpu.fetch.rateDist::0 59688776 51.03% 51.03%
+system.cpu.fetch.rateDist::1 13868271 11.86% 62.88%
+system.cpu.fetch.rateDist::2 9100495 7.78% 70.66%
+system.cpu.fetch.rateDist::3 34316340 29.34% 100.00%
+system.cpu.fetch.rateDist::overflows 0 0.00% 100.00%
+system.cpu.fetch.rateDist::min_value 0
+system.cpu.fetch.rateDist::max_value 3
+system.cpu.fetch.rateDist::total 116973882
+system.cpu.fetch.branchRate 0.240269
+system.cpu.fetch.rate 1.148138
+system.cpu.decode.IdleCycles 8865418
+system.cpu.decode.BlockedCycles 65026599
+system.cpu.decode.RunCycles 32710680
+system.cpu.decode.UnblockCycles 9589004
+system.cpu.decode.SquashCycles 782181
+system.cpu.decode.BranchResolved 9831266
+system.cpu.decode.BranchMispred 64876
+system.cpu.decode.DecodedInsts 113761457
+system.cpu.decode.SquashedInsts 2108425
+system.cpu.rename.SquashCycles 782181
+system.cpu.rename.IdleCycles 15316274
+system.cpu.rename.BlockCycles 50229704
+system.cpu.rename.serializeStallCycles 114341
+system.cpu.rename.RunCycles 35119945
+system.cpu.rename.UnblockCycles 15411437
+system.cpu.rename.RenamedInsts 110456918
+system.cpu.rename.SquashedInsts 1289549
+system.cpu.rename.ROBFullEvents 11149602
+system.cpu.rename.IQFullEvents 1576334
+system.cpu.rename.LQFullEvents 2138216
+system.cpu.rename.SQFullEvents 510190
+system.cpu.rename.RenamedOperands 129202611
+system.cpu.rename.RenameLookups 481340709
+system.cpu.rename.int_rename_lookups 118978784
+system.cpu.rename.fp_rename_lookups 633
+system.cpu.rename.CommittedMaps 107312919
+system.cpu.rename.UndoneMaps 21889692
+system.cpu.rename.serializingInsts 4408
+system.cpu.rename.tempSerializingInsts 4400
+system.cpu.rename.skidInsts 21529051
+system.cpu.memDep0.insertedLoads 26813393
+system.cpu.memDep0.insertedStores 5308956
+system.cpu.memDep0.conflictingLoads 540635
+system.cpu.memDep0.conflictingStores 272789
+system.cpu.iq.iqInstsAdded 109383305
+system.cpu.iq.iqNonSpecInstsAdded 8282
+system.cpu.iq.iqInstsIssued 101253910
+system.cpu.iq.iqSquashedInstsIssued 993650
+system.cpu.iq.iqSquashedInstsExamined 18350556
+system.cpu.iq.iqSquashedOperandsExamined 40868291
+system.cpu.iq.iqSquashedNonSpecRemoved 64
+system.cpu.iq.issued_per_cycle::samples 116973882
+system.cpu.iq.issued_per_cycle::mean 0.865611
+system.cpu.iq.issued_per_cycle::stdev 0.989909
+system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00%
+system.cpu.iq.issued_per_cycle::0 55502940 47.45% 47.45%
+system.cpu.iq.issued_per_cycle::1 31207963 26.68% 74.13%
+system.cpu.iq.issued_per_cycle::2 21948493 18.76% 92.89%
+system.cpu.iq.issued_per_cycle::3 7109305 6.08% 98.97%
+system.cpu.iq.issued_per_cycle::4 1204859 1.03% 100.00%
+system.cpu.iq.issued_per_cycle::5 322 0.00% 100.00%
+system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00%
+system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00%
+system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00%
+system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00%
+system.cpu.iq.issued_per_cycle::min_value 0
+system.cpu.iq.issued_per_cycle::max_value 5
+system.cpu.iq.issued_per_cycle::total 116973882
+system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00%
+system.cpu.iq.fu_full::IntAlu 9836731 48.84% 48.84%
+system.cpu.iq.fu_full::IntMult 51 0.00% 48.84%
+system.cpu.iq.fu_full::IntDiv 0 0.00% 48.84%
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.84%
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.84%
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.84%
+system.cpu.iq.fu_full::FloatMult 0 0.00% 48.84%
+system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 48.84%
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.84%
+system.cpu.iq.fu_full::FloatMisc 0 0.00% 48.84%
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdMult 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdShift 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdFloatCvt 19 0.00% 48.84%
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.84%
+system.cpu.iq.fu_full::MemRead 9605308 47.69% 96.54%
+system.cpu.iq.fu_full::MemWrite 697155 3.46% 100.00%
+system.cpu.iq.fu_full::FloatMemRead 3 0.00% 100.00%
+system.cpu.iq.fu_full::FloatMemWrite 24 0.00% 100.00%
+system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00%
+system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00%
+system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00%
+system.cpu.iq.FU_type_0::IntAlu 71822499 70.93% 70.93%
+system.cpu.iq.FU_type_0::IntMult 10678 0.01% 70.94%
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdFloatCvt 77 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdFloatMisc 184 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::MemRead 24343876 24.04% 94.99%
+system.cpu.iq.FU_type_0::MemWrite 5076562 5.01% 100.00%
+system.cpu.iq.FU_type_0::FloatMemRead 8 0.00% 100.00%
+system.cpu.iq.FU_type_0::FloatMemWrite 22 0.00% 100.00%
+system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00%
+system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00%
+system.cpu.iq.FU_type_0::total 101253910
+system.cpu.iq.rate 0.865106
+system.cpu.iq.fu_busy_cnt 20139291
+system.cpu.iq.fu_busy_rate 0.198899
+system.cpu.iq.int_inst_queue_reads 340613998
+system.cpu.iq.int_inst_queue_writes 127742532
+system.cpu.iq.int_inst_queue_wakeup_accesses 99568159
+system.cpu.iq.fp_inst_queue_reads 645
+system.cpu.iq.fp_inst_queue_writes 896
+system.cpu.iq.fp_inst_queue_wakeup_accesses 147
+system.cpu.iq.int_alu_accesses 121392865
+system.cpu.iq.fp_alu_accesses 336
+system.cpu.iew.lsq.thread0.forwLoads 289487
+system.cpu.iew.lsq.thread0.invAddrLoads 0
+system.cpu.iew.lsq.thread0.squashedLoads 4337482
+system.cpu.iew.lsq.thread0.ignoredResponses 2085
+system.cpu.iew.lsq.thread0.memOrderViolation 1323
+system.cpu.iew.lsq.thread0.squashedStores 564112
+system.cpu.iew.lsq.thread0.invAddrSwpfs 0
+system.cpu.iew.lsq.thread0.blockedLoads 0
+system.cpu.iew.lsq.thread0.rescheduledLoads 7586
+system.cpu.iew.lsq.thread0.cacheBlocked 131115
+system.cpu.iew.iewIdleCycles 0
+system.cpu.iew.iewSquashCycles 782181
+system.cpu.iew.iewBlockCycles 8303656
+system.cpu.iew.iewUnblockCycles 706645
+system.cpu.iew.iewDispatchedInsts 109404410
+system.cpu.iew.iewDispSquashedInsts 0
+system.cpu.iew.iewDispLoadInsts 26813393
+system.cpu.iew.iewDispStoreInsts 5308956
+system.cpu.iew.iewDispNonSpecInsts 4394
+system.cpu.iew.iewIQFullEvents 183005
+system.cpu.iew.iewLSQFullEvents 362995
+system.cpu.iew.memOrderViolationEvents 1323
+system.cpu.iew.predictedTakenIncorrect 354101
+system.cpu.iew.predictedNotTakenIncorrect 451870
+system.cpu.iew.branchMispredicts 805971
+system.cpu.iew.iewExecutedInsts 100068536
+system.cpu.iew.iewExecLoadInsts 23799476
+system.cpu.iew.iewExecSquashedInsts 1185374
+system.cpu.iew.exec_swp 0
+system.cpu.iew.exec_nop 12823
+system.cpu.iew.exec_refs 28747002
+system.cpu.iew.exec_branches 20644390
+system.cpu.iew.exec_stores 4947526
+system.cpu.iew.exec_rate 0.854978
+system.cpu.iew.wb_sent 99653444
+system.cpu.iew.wb_count 99568306
+system.cpu.iew.wb_producers 59603520
+system.cpu.iew.wb_consumers 95472454
+system.cpu.iew.wb_rate 0.850705
+system.cpu.iew.wb_fanout 0.624301
+system.cpu.commit.commitSquashedInsts 17204380
+system.cpu.commit.commitNonSpecStalls 8218
+system.cpu.commit.branchMispredicts 780499
+system.cpu.commit.committed_per_cycle::samples 114317449
+system.cpu.commit.committed_per_cycle::mean 0.796498
+system.cpu.commit.committed_per_cycle::stdev 1.736161
+system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00%
+system.cpu.commit.committed_per_cycle::0 77973404 68.21% 68.21%
+system.cpu.commit.committed_per_cycle::1 18552037 16.23% 84.44%
+system.cpu.commit.committed_per_cycle::2 7135846 6.24% 90.68%
+system.cpu.commit.committed_per_cycle::3 3439776 3.01% 93.69%
+system.cpu.commit.committed_per_cycle::4 1654311 1.45% 95.13%
+system.cpu.commit.committed_per_cycle::5 545783 0.48% 95.61%
+system.cpu.commit.committed_per_cycle::6 692568 0.61% 96.22%
+system.cpu.commit.committed_per_cycle::7 180777 0.16% 96.38%
+system.cpu.commit.committed_per_cycle::8 4142947 3.62% 100.00%
+system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00%
+system.cpu.commit.committed_per_cycle::min_value 0
+system.cpu.commit.committed_per_cycle::max_value 8
+system.cpu.commit.committed_per_cycle::total 114317449
+system.cpu.commit.committedInsts 90602408
+system.cpu.commit.committedOps 91053639
+system.cpu.commit.swp_count 0
+system.cpu.commit.refs 27220755
+system.cpu.commit.loads 22475911
+system.cpu.commit.membars 3888
+system.cpu.commit.branches 18732305
+system.cpu.commit.fp_insts 48
+system.cpu.commit.int_insts 72326352
+system.cpu.commit.function_calls 56148
+system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00%
+system.cpu.commit.op_class_0::IntAlu 63822387 70.09% 70.09%
+system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.10%
+system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.10%
+system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10%
+system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10%
+system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10%
+system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10%
+system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 70.10%
+system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10%
+system.cpu.commit.op_class_0::FloatMisc 0 0.00% 70.10%
+system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10%
+system.cpu.commit.op_class_0::MemRead 22475905 24.68% 94.79%
+system.cpu.commit.op_class_0::MemWrite 4744822 5.21% 100.00%
+system.cpu.commit.op_class_0::FloatMemRead 6 0.00% 100.00%
+system.cpu.commit.op_class_0::FloatMemWrite 22 0.00% 100.00%
+system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00%
+system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00%
+system.cpu.commit.op_class_0::total 91053639
+system.cpu.commit.bw_lim_events 4142947
+system.cpu.rob.rob_reads 218426787
+system.cpu.rob.rob_writes 219173123
+system.cpu.timesIdled 593
+system.cpu.idleCycles 68291
+system.cpu.committedInsts 90589799
+system.cpu.committedOps 91041030
+system.cpu.cpi 1.292002
+system.cpu.cpi_total 1.292002
+system.cpu.ipc 0.773993
+system.cpu.ipc_total 0.773993
+system.cpu.int_regfile_reads 108095256
+system.cpu.int_regfile_writes 58597145
+system.cpu.fp_regfile_reads 58
+system.cpu.fp_regfile_writes 127
+system.cpu.cc_regfile_reads 368871207
+system.cpu.cc_regfile_writes 58517884
+system.cpu.misc_regfile_reads 28439348
+system.cpu.misc_regfile_writes 7784
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.dcache.tags.replacements 5470632
+system.cpu.dcache.tags.tagsinuse 511.768178
+system.cpu.dcache.tags.total_refs 18243100
+system.cpu.dcache.tags.sampled_refs 5471144
+system.cpu.dcache.tags.avg_refs 3.334421
+system.cpu.dcache.tags.warmup_cycle 38187500
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.768178
+system.cpu.dcache.tags.occ_percent::cpu.data 0.999547
+system.cpu.dcache.tags.occ_percent::total 0.999547
+system.cpu.dcache.tags.occ_task_id_blocks::1024 512
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 327
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 185
+system.cpu.dcache.tags.occ_task_id_percent::1024 1
+system.cpu.dcache.tags.tag_accesses 61896540
+system.cpu.dcache.tags.data_accesses 61896540
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.dcache.ReadReq_hits::cpu.data 13880582
+system.cpu.dcache.ReadReq_hits::total 13880582
+system.cpu.dcache.WriteReq_hits::cpu.data 4354214
+system.cpu.dcache.WriteReq_hits::total 4354214
+system.cpu.dcache.SoftPFReq_hits::cpu.data 522
+system.cpu.dcache.SoftPFReq_hits::total 522
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873
+system.cpu.dcache.LoadLockedReq_hits::total 3873
+system.cpu.dcache.StoreCondReq_hits::cpu.data 3887
+system.cpu.dcache.StoreCondReq_hits::total 3887
+system.cpu.dcache.demand_hits::cpu.data 18234796
+system.cpu.dcache.demand_hits::total 18234796
+system.cpu.dcache.overall_hits::cpu.data 18235318
+system.cpu.dcache.overall_hits::total 18235318
+system.cpu.dcache.ReadReq_misses::cpu.data 9588832
+system.cpu.dcache.ReadReq_misses::total 9588832
+system.cpu.dcache.WriteReq_misses::cpu.data 380767
+system.cpu.dcache.WriteReq_misses::total 380767
+system.cpu.dcache.SoftPFReq_misses::cpu.data 7
+system.cpu.dcache.SoftPFReq_misses::total 7
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 14
+system.cpu.dcache.LoadLockedReq_misses::total 14
+system.cpu.dcache.demand_misses::cpu.data 9969599
+system.cpu.dcache.demand_misses::total 9969599
+system.cpu.dcache.overall_misses::cpu.data 9969606
+system.cpu.dcache.overall_misses::total 9969606
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 89393317500
+system.cpu.dcache.ReadReq_miss_latency::total 89393317500
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 4103772083
+system.cpu.dcache.WriteReq_miss_latency::total 4103772083
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 302000
+system.cpu.dcache.LoadLockedReq_miss_latency::total 302000
+system.cpu.dcache.demand_miss_latency::cpu.data 93497089583
+system.cpu.dcache.demand_miss_latency::total 93497089583
+system.cpu.dcache.overall_miss_latency::cpu.data 93497089583
+system.cpu.dcache.overall_miss_latency::total 93497089583
+system.cpu.dcache.ReadReq_accesses::cpu.data 23469414
+system.cpu.dcache.ReadReq_accesses::total 23469414
+system.cpu.dcache.WriteReq_accesses::cpu.data 4734981
+system.cpu.dcache.WriteReq_accesses::total 4734981
+system.cpu.dcache.SoftPFReq_accesses::cpu.data 529
+system.cpu.dcache.SoftPFReq_accesses::total 529
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887
+system.cpu.dcache.LoadLockedReq_accesses::total 3887
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887
+system.cpu.dcache.StoreCondReq_accesses::total 3887
+system.cpu.dcache.demand_accesses::cpu.data 28204395
+system.cpu.dcache.demand_accesses::total 28204395
+system.cpu.dcache.overall_accesses::cpu.data 28204924
+system.cpu.dcache.overall_accesses::total 28204924
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408567
+system.cpu.dcache.ReadReq_miss_rate::total 0.408567
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080416
+system.cpu.dcache.WriteReq_miss_rate::total 0.080416
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233
+system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602
+system.cpu.dcache.demand_miss_rate::cpu.data 0.353477
+system.cpu.dcache.demand_miss_rate::total 0.353477
+system.cpu.dcache.overall_miss_rate::cpu.data 0.353470
+system.cpu.dcache.overall_miss_rate::total 0.353470
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9322.649255
+system.cpu.dcache.ReadReq_avg_miss_latency::total 9322.649255
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10777.646390
+system.cpu.dcache.WriteReq_avg_miss_latency::total 10777.646390
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21571.428571
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21571.428571
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 9378.219684
+system.cpu.dcache.demand_avg_miss_latency::total 9378.219684
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 9378.213099
+system.cpu.dcache.overall_avg_miss_latency::total 9378.213099
+system.cpu.dcache.blocked_cycles::no_mshrs 331670
+system.cpu.dcache.blocked_cycles::no_targets 131340
+system.cpu.dcache.blocked::no_mshrs 121646
+system.cpu.dcache.blocked::no_targets 12838
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.726518
+system.cpu.dcache.avg_blocked_cycles::no_targets 10.230566
+system.cpu.dcache.writebacks::writebacks 5470632
+system.cpu.dcache.writebacks::total 5470632
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4340269
+system.cpu.dcache.ReadReq_mshr_hits::total 4340269
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158185
+system.cpu.dcache.WriteReq_mshr_hits::total 158185
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 14
+system.cpu.dcache.demand_mshr_hits::cpu.data 4498454
+system.cpu.dcache.demand_mshr_hits::total 4498454
+system.cpu.dcache.overall_mshr_hits::cpu.data 4498454
+system.cpu.dcache.overall_mshr_hits::total 4498454
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248563
+system.cpu.dcache.ReadReq_mshr_misses::total 5248563
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222582
+system.cpu.dcache.WriteReq_mshr_misses::total 222582
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4
+system.cpu.dcache.SoftPFReq_mshr_misses::total 4
+system.cpu.dcache.demand_mshr_misses::cpu.data 5471145
+system.cpu.dcache.demand_mshr_misses::total 5471145
+system.cpu.dcache.overall_mshr_misses::cpu.data 5471149
+system.cpu.dcache.overall_mshr_misses::total 5471149
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43818706500
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 43818706500
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2301862483
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 2301862483
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 235500
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 235500
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46120568983
+system.cpu.dcache.demand_mshr_miss_latency::total 46120568983
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46120804483
+system.cpu.dcache.overall_mshr_miss_latency::total 46120804483
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223634
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223634
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047008
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047008
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193982
+system.cpu.dcache.demand_mshr_miss_rate::total 0.193982
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193979
+system.cpu.dcache.overall_mshr_miss_rate::total 0.193979
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8348.705446
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8348.705446
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10341.638061
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10341.638061
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 58875
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 58875
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8429.783708
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 8429.783708
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8429.820589
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 8429.820589
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.icache.tags.replacements 449
+system.cpu.icache.tags.tagsinuse 426.857560
+system.cpu.icache.tags.total_refs 32085580
+system.cpu.icache.tags.sampled_refs 907
+system.cpu.icache.tags.avg_refs 35375.501654
+system.cpu.icache.tags.warmup_cycle 0
+system.cpu.icache.tags.occ_blocks::cpu.inst 426.857560
+system.cpu.icache.tags.occ_percent::cpu.inst 0.833706
+system.cpu.icache.tags.occ_percent::total 0.833706
+system.cpu.icache.tags.occ_task_id_blocks::1024 458
+system.cpu.icache.tags.age_task_id_blocks_1024::0 53
+system.cpu.icache.tags.age_task_id_blocks_1024::2 50
+system.cpu.icache.tags.age_task_id_blocks_1024::3 22
+system.cpu.icache.tags.age_task_id_blocks_1024::4 333
+system.cpu.icache.tags.occ_task_id_percent::1024 0.894531
+system.cpu.icache.tags.tag_accesses 64174375
+system.cpu.icache.tags.data_accesses 64174375
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.icache.ReadReq_hits::cpu.inst 32085580
+system.cpu.icache.ReadReq_hits::total 32085580
+system.cpu.icache.demand_hits::cpu.inst 32085580
+system.cpu.icache.demand_hits::total 32085580
+system.cpu.icache.overall_hits::cpu.inst 32085580
+system.cpu.icache.overall_hits::total 32085580
+system.cpu.icache.ReadReq_misses::cpu.inst 1154
+system.cpu.icache.ReadReq_misses::total 1154
+system.cpu.icache.demand_misses::cpu.inst 1154
+system.cpu.icache.demand_misses::total 1154
+system.cpu.icache.overall_misses::cpu.inst 1154
+system.cpu.icache.overall_misses::total 1154
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 81624480
+system.cpu.icache.ReadReq_miss_latency::total 81624480
+system.cpu.icache.demand_miss_latency::cpu.inst 81624480
+system.cpu.icache.demand_miss_latency::total 81624480
+system.cpu.icache.overall_miss_latency::cpu.inst 81624480
+system.cpu.icache.overall_miss_latency::total 81624480
+system.cpu.icache.ReadReq_accesses::cpu.inst 32086734
+system.cpu.icache.ReadReq_accesses::total 32086734
+system.cpu.icache.demand_accesses::cpu.inst 32086734
+system.cpu.icache.demand_accesses::total 32086734
+system.cpu.icache.overall_accesses::cpu.inst 32086734
+system.cpu.icache.overall_accesses::total 32086734
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036
+system.cpu.icache.ReadReq_miss_rate::total 0.000036
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000036
+system.cpu.icache.demand_miss_rate::total 0.000036
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000036
+system.cpu.icache.overall_miss_rate::total 0.000036
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70731.785095
+system.cpu.icache.ReadReq_avg_miss_latency::total 70731.785095
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 70731.785095
+system.cpu.icache.demand_avg_miss_latency::total 70731.785095
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 70731.785095
+system.cpu.icache.overall_avg_miss_latency::total 70731.785095
+system.cpu.icache.blocked_cycles::no_mshrs 21770
+system.cpu.icache.blocked_cycles::no_targets 1853
+system.cpu.icache.blocked::no_mshrs 229
+system.cpu.icache.blocked::no_targets 7
+system.cpu.icache.avg_blocked_cycles::no_mshrs 95.065502
+system.cpu.icache.avg_blocked_cycles::no_targets 264.714286
+system.cpu.icache.writebacks::writebacks 449
+system.cpu.icache.writebacks::total 449
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 246
+system.cpu.icache.ReadReq_mshr_hits::total 246
+system.cpu.icache.demand_mshr_hits::cpu.inst 246
+system.cpu.icache.demand_mshr_hits::total 246
+system.cpu.icache.overall_mshr_hits::cpu.inst 246
+system.cpu.icache.overall_mshr_hits::total 246
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 908
+system.cpu.icache.ReadReq_mshr_misses::total 908
+system.cpu.icache.demand_mshr_misses::cpu.inst 908
+system.cpu.icache.demand_mshr_misses::total 908
+system.cpu.icache.overall_mshr_misses::cpu.inst 908
+system.cpu.icache.overall_mshr_misses::total 908
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61609984
+system.cpu.icache.ReadReq_mshr_miss_latency::total 61609984
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61609984
+system.cpu.icache.demand_mshr_miss_latency::total 61609984
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61609984
+system.cpu.icache.overall_mshr_miss_latency::total 61609984
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028
+system.cpu.icache.demand_mshr_miss_rate::total 0.000028
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028
+system.cpu.icache.overall_mshr_miss_rate::total 0.000028
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67852.405286
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67852.405286
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67852.405286
+system.cpu.icache.demand_avg_mshr_miss_latency::total 67852.405286
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67852.405286
+system.cpu.icache.overall_avg_mshr_miss_latency::total 67852.405286
+system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.l2cache.prefetcher.num_hwpf_issued 4987667
+system.cpu.l2cache.prefetcher.pfIdentified 5295978
+system.cpu.l2cache.prefetcher.pfBufferHit 268023
+system.cpu.l2cache.prefetcher.pfInCache 0
+system.cpu.l2cache.prefetcher.pfRemovedFull 0
+system.cpu.l2cache.prefetcher.pfSpanPage 14076270
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.l2cache.tags.replacements 99
+system.cpu.l2cache.tags.tagsinuse 11218.637670
+system.cpu.l2cache.tags.total_refs 5292117
+system.cpu.l2cache.tags.sampled_refs 14656
+system.cpu.l2cache.tags.avg_refs 361.088769
+system.cpu.l2cache.tags.warmup_cycle 0
+system.cpu.l2cache.tags.occ_blocks::writebacks 11151.920658
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 66.717012
+system.cpu.l2cache.tags.occ_percent::writebacks 0.680659
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004072
+system.cpu.l2cache.tags.occ_percent::total 0.684731
+system.cpu.l2cache.tags.occ_task_id_blocks::1022 67
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 14490
+system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2
+system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4 56
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 454
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3440
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9642
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 120
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 834
+system.cpu.l2cache.tags.occ_task_id_percent::1022 0.004089
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884399
+system.cpu.l2cache.tags.tag_accesses 180525307
+system.cpu.l2cache.tags.data_accesses 180525307
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.l2cache.WritebackDirty_hits::writebacks 5460197
+system.cpu.l2cache.WritebackDirty_hits::total 5460197
+system.cpu.l2cache.WritebackClean_hits::writebacks 7956
+system.cpu.l2cache.WritebackClean_hits::total 7956
+system.cpu.l2cache.ReadExReq_hits::cpu.data 225753
+system.cpu.l2cache.ReadExReq_hits::total 225753
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 207
+system.cpu.l2cache.ReadCleanReq_hits::total 207
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5241769
+system.cpu.l2cache.ReadSharedReq_hits::total 5241769
+system.cpu.l2cache.demand_hits::cpu.inst 207
+system.cpu.l2cache.demand_hits::cpu.data 5467522
+system.cpu.l2cache.demand_hits::total 5467729
+system.cpu.l2cache.overall_hits::cpu.inst 207
+system.cpu.l2cache.overall_hits::cpu.data 5467522
+system.cpu.l2cache.overall_hits::total 5467729
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 5
+system.cpu.l2cache.UpgradeReq_misses::total 5
+system.cpu.l2cache.ReadExReq_misses::cpu.data 499
+system.cpu.l2cache.ReadExReq_misses::total 499
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 701
+system.cpu.l2cache.ReadCleanReq_misses::total 701
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data 3123
+system.cpu.l2cache.ReadSharedReq_misses::total 3123
+system.cpu.l2cache.demand_misses::cpu.inst 701
+system.cpu.l2cache.demand_misses::cpu.data 3622
+system.cpu.l2cache.demand_misses::total 4323
+system.cpu.l2cache.overall_misses::cpu.inst 701
+system.cpu.l2cache.overall_misses::cpu.data 3622
+system.cpu.l2cache.overall_misses::total 4323
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 105500
+system.cpu.l2cache.UpgradeReq_miss_latency::total 105500
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 66196000
+system.cpu.l2cache.ReadExReq_miss_latency::total 66196000
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 59307500
+system.cpu.l2cache.ReadCleanReq_miss_latency::total 59307500
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 617300000
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 617300000
+system.cpu.l2cache.demand_miss_latency::cpu.inst 59307500
+system.cpu.l2cache.demand_miss_latency::cpu.data 683496000
+system.cpu.l2cache.demand_miss_latency::total 742803500
+system.cpu.l2cache.overall_miss_latency::cpu.inst 59307500
+system.cpu.l2cache.overall_miss_latency::cpu.data 683496000
+system.cpu.l2cache.overall_miss_latency::total 742803500
+system.cpu.l2cache.WritebackDirty_accesses::writebacks 5460197
+system.cpu.l2cache.WritebackDirty_accesses::total 5460197
+system.cpu.l2cache.WritebackClean_accesses::writebacks 7956
+system.cpu.l2cache.WritebackClean_accesses::total 7956
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5
+system.cpu.l2cache.UpgradeReq_accesses::total 5
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 226252
+system.cpu.l2cache.ReadExReq_accesses::total 226252
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 908
+system.cpu.l2cache.ReadCleanReq_accesses::total 908
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244892
+system.cpu.l2cache.ReadSharedReq_accesses::total 5244892
+system.cpu.l2cache.demand_accesses::cpu.inst 908
+system.cpu.l2cache.demand_accesses::cpu.data 5471144
+system.cpu.l2cache.demand_accesses::total 5472052
+system.cpu.l2cache.overall_accesses::cpu.inst 908
+system.cpu.l2cache.overall_accesses::cpu.data 5471144
+system.cpu.l2cache.overall_accesses::total 5472052
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1
+system.cpu.l2cache.UpgradeReq_miss_rate::total 1
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002206
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.002206
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.772026
+system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.772026
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000595
+system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000595
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.772026
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.000662
+system.cpu.l2cache.demand_miss_rate::total 0.000790
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.772026
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.000662
+system.cpu.l2cache.overall_miss_rate::total 0.000790
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21100
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21100
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132657.314629
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132657.314629
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84604.136947
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84604.136947
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 197662.504003
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 197662.504003
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84604.136947
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 188706.791828
+system.cpu.l2cache.demand_avg_miss_latency::total 171825.931066
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84604.136947
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 188706.791828
+system.cpu.l2cache.overall_avg_miss_latency::total 171825.931066
+system.cpu.l2cache.blocked_cycles::no_mshrs 0
+system.cpu.l2cache.blocked_cycles::no_targets 0
+system.cpu.l2cache.blocked::no_mshrs 0
+system.cpu.l2cache.blocked::no_targets 0
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan
+system.cpu.l2cache.unused_prefetches 1
+system.cpu.l2cache.writebacks::writebacks 74
+system.cpu.l2cache.writebacks::total 74
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 158
+system.cpu.l2cache.ReadExReq_mshr_hits::total 158
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 22
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total 22
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 1
+system.cpu.l2cache.demand_mshr_hits::cpu.data 180
+system.cpu.l2cache.demand_mshr_hits::total 181
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 1
+system.cpu.l2cache.overall_mshr_hits::cpu.data 180
+system.cpu.l2cache.overall_mshr_hits::total 181
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316332
+system.cpu.l2cache.HardPFReq_mshr_misses::total 316332
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 5
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 341
+system.cpu.l2cache.ReadExReq_mshr_misses::total 341
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 700
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 700
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 3101
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 3101
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 700
+system.cpu.l2cache.demand_mshr_misses::cpu.data 3442
+system.cpu.l2cache.demand_mshr_misses::total 4142
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 700
+system.cpu.l2cache.overall_mshr_misses::cpu.data 3442
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316332
+system.cpu.l2cache.overall_mshr_misses::total 320474
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1095451507
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1095451507
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 75500
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 75500
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 46761500
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 46761500
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 55046500
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 55046500
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 590692000
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 590692000
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 55046500
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 637453500
+system.cpu.l2cache.demand_mshr_miss_latency::total 692500000
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 55046500
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 637453500
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1095451507
+system.cpu.l2cache.overall_mshr_miss_latency::total 1787951507
+system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf
+system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001507
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001507
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.770925
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.770925
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000591
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000591
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.770925
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000629
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.000757
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.770925
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000629
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.058566
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3462.980372
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3462.980372
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15100
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15100
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 137130.498534
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 137130.498534
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 78637.857143
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 78637.857143
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 190484.359884
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 190484.359884
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 78637.857143
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185198.576409
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167189.763399
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 78637.857143
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185198.576409
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3462.980372
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 5579.084441
+system.cpu.toL2Bus.snoop_filter.tot_requests 10943138
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471099
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2928
+system.cpu.toL2Bus.snoop_filter.tot_snoops 301927
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 301926
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.toL2Bus.trans_dist::ReadResp 5245799
+system.cpu.toL2Bus.trans_dist::WritebackDirty 5460271
+system.cpu.toL2Bus.trans_dist::WritebackClean 10884
+system.cpu.toL2Bus.trans_dist::CleanEvict 25
+system.cpu.toL2Bus.trans_dist::HardPFReq 318221
+system.cpu.toL2Bus.trans_dist::HardPFResp 6
+system.cpu.toL2Bus.trans_dist::UpgradeReq 5
+system.cpu.toL2Bus.trans_dist::UpgradeResp 5
+system.cpu.toL2Bus.trans_dist::ReadExReq 226252
+system.cpu.toL2Bus.trans_dist::ReadExResp 226252
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 908
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244892
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2264
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412936
+system.cpu.toL2Bus.pkt_count::total 16415200
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86784
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274048
+system.cpu.toL2Bus.pkt_size::total 700360832
+system.cpu.toL2Bus.snoops 318326
+system.cpu.toL2Bus.snoopTraffic 5120
+system.cpu.toL2Bus.snoop_fanout::samples 5790377
+system.cpu.toL2Bus.snoop_fanout::mean 0.052651
+system.cpu.toL2Bus.snoop_fanout::stdev 0.223337
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu.toL2Bus.snoop_fanout::0 5485509 94.73% 94.73%
+system.cpu.toL2Bus.snoop_fanout::1 304867 5.27% 100.00%
+system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::min_value 0
+system.cpu.toL2Bus.snoop_fanout::max_value 2
+system.cpu.toL2Bus.snoop_fanout::total 5790377
+system.cpu.toL2Bus.reqLayer0.occupancy 10942650026
+system.cpu.toL2Bus.reqLayer0.utilization 18.7
+system.cpu.toL2Bus.snoopLayer0.occupancy 9032
+system.cpu.toL2Bus.snoopLayer0.utilization 0.0
+system.cpu.toL2Bus.respLayer0.occupancy 1362995
+system.cpu.toL2Bus.respLayer0.utilization 0.0
+system.cpu.toL2Bus.respLayer1.occupancy 8206721993
+system.cpu.toL2Bus.respLayer1.utilization 14.0
+system.membus.snoop_filter.tot_requests 18651
+system.membus.snoop_filter.hit_single_requests 3037
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.membus.trans_dist::ReadResp 18205
+system.membus.trans_dist::WritebackDirty 74
+system.membus.trans_dist::CleanEvict 25
+system.membus.trans_dist::UpgradeReq 6
+system.membus.trans_dist::ReadExReq 340
+system.membus.trans_dist::ReadExResp 340
+system.membus.trans_dist::ReadSharedReq 18206
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37196
+system.membus.pkt_count::total 37196
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1191616
+system.membus.pkt_size::total 1191616
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 18552
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 18552 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 18552
+system.membus.reqLayer0.occupancy 29380556
+system.membus.reqLayer0.utilization 0.1
+system.membus.respLayer1.occupancy 97369032
+system.membus.respLayer1.utilization 0.2
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
index c6db85421..d6f970870 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
@@ -85,6 +85,7 @@ progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -94,14 +95,14 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@@ -115,6 +116,7 @@ response_latency=2
sequential_access=false
size=262144
system=system
+tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@@ -127,15 +129,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
+tag_latency=2
[system.cpu.dtb]
type=SparcTLB
@@ -145,14 +148,14 @@ size=64
[system.cpu.icache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@@ -166,6 +169,7 @@ response_latency=2
sequential_access=false
size=131072
system=system
+tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@@ -178,15 +182,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
+tag_latency=2
[system.cpu.interrupts]
type=SparcInterrupts
@@ -204,14 +209,14 @@ size=64
[system.cpu.l2cache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@@ -225,6 +230,7 @@ response_latency=20
sequential_access=false
size=2097152
system=system
+tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@@ -237,15 +243,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=20
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
+tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -281,7 +288,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=mcf mcf.in
cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
drivers=
@@ -290,14 +297,15 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/sparc/linux/mcf
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/sparc/linux/mcf
gid=100
-input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=55300000000
system=system
uid=100
@@ -321,6 +329,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -332,7 +341,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -340,6 +349,13 @@ width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -348,6 +364,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
+kvm_map=true
latency=30000
latency_var=0
null=false
@@ -355,7 +372,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
-range=0:268435455
+range=0:268435455:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr
index aadc3d011..c0b55d123 100755
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr
@@ -1,2 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
index 8bd59a796..1f1ba7a8d 100755
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
@@ -3,13 +3,12 @@ Redirecting stderr to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-ti
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 21 2016 14:30:06
-gem5 started Jul 21 2016 14:30:36
-gem5 executing on e108600-lin, pid 38669
-command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/sparc/linux/simple-timing
+gem5 compiled Apr 3 2017 18:41:19
+gem5 started Apr 3 2017 18:43:33
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 66471
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/10.mcf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I
by Andreas Loebel
@@ -26,4 +25,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 361597758500 because target called exit()
+Exiting @ tick 361613361500 because exiting with last active thread context
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
index 33d560709..7f71ad751 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
@@ -1,541 +1,541 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.361613 # Number of seconds simulated
-sim_ticks 361613361500 # Number of ticks simulated
-final_tick 361613361500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1844871 # Simulator instruction rate (inst/s)
-host_op_rate 1844948 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2736100211 # Simulator tick rate (ticks/s)
-host_mem_usage 385448 # Number of bytes of host memory used
-host_seconds 132.16 # Real time elapsed on the host
-sim_insts 243825150 # Number of instructions simulated
-sim_ops 243835265 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory
-system.physmem.bytes_read::total 998592 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 155569 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2605921 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2761491 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 155569 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 155569 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 155569 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2605921 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2761491 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.workload.numSyscalls 443 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 361613361500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 723226723 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 243825150 # Number of instructions committed
-system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses
-system.cpu.num_func_calls 4252956 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls
-system.cpu.num_int_insts 194726494 # number of integer instructions
-system.cpu.num_fp_insts 11630 # number of float instructions
-system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read
-system.cpu.num_int_register_writes 215451553 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 90 # number of times the floating registers were written
-system.cpu.num_mem_refs 105711441 # number of memory refs
-system.cpu.num_load_insts 82803521 # Number of load instructions
-system.cpu.num_store_insts 22907920 # Number of store instructions
-system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 723226722.998000 # Number of busy cycles
-system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 29302884 # Number of branches fetched
-system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction
-system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction
-system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::MemRead 82803516 33.88% 90.63% # Class of executed instruction
-system.cpu.op_class::MemWrite 22896343 9.37% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 11 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 11577 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 244431613 # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 935475 # number of replacements
-system.cpu.dcache.tags.tagsinuse 3562.404243 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 134415942500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 3562.404243 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.869728 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.869728 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 1416 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 2526 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits
-system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits
-system.cpu.dcache.overall_hits::total 104182817 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses
-system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses
-system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses
-system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses
-system.cpu.dcache.overall_misses::total 939567 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 11614992000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 11614992000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 1335530000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 1335530000 # number of WriteReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::cpu.data 102000 # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::total 102000 # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 12950522000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 12950522000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 12950522000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 12950522000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.793121 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.793121 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28591.950332 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 28591.950332 # average WriteReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25500 # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::total 25500 # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 13783.500272 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 13783.500272 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 13783.500272 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 13783.500272 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks
-system.cpu.dcache.writebacks::total 935266 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses
-system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses
-system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10722135000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 10722135000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1288820000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 1288820000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 98000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::total 98000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12010955000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 12010955000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12010955000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 12010955000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.793121 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.793121 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27591.950332 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27591.950332 # average WriteReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24500 # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24500 # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12783.500272 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 12783.500272 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12783.500272 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 12783.500272 # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements 25 # number of replacements
-system.cpu.icache.tags.tagsinuse 725.403723 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 725.403723 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.354201 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.354201 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 781 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 488843880 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 488843880 # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 244420617 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 244420617 # number of overall hits
-system.cpu.icache.overall_hits::total 244420617 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses
-system.cpu.icache.overall_misses::total 882 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 55422500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 55422500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 55422500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 55422500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 55422500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 55422500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 244421499 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 244421499 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 244421499 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62837.301587 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 62837.301587 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 62837.301587 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 62837.301587 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 62837.301587 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 62837.301587 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks 25 # number of writebacks
-system.cpu.icache.writebacks::total 25 # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54540500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 54540500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54540500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 54540500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54540500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 54540500 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61837.301587 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61837.301587 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61837.301587 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 61837.301587 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61837.301587 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 61837.301587 # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 10855.563013 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 1860349 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 15603 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 119.230212 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.626846 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 10116.936167 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.308744 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.331285 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 15603 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15465 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.476166 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 15023219 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 15023219 # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks 935266 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total 935266 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks 25 # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total 25 # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data 892700 # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total 892700 # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 924847 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 924850 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 924847 # number of overall hits
-system.cpu.l2cache.overall_hits::total 924850 # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 879 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total 879 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data 157 # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total 157 # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 14724 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 15603 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses
-system.cpu.l2cache.overall_misses::total 15603 # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 881303500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 881303500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 53183000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total 53183000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9498500 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 9498500 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 53183000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 890802000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 943985000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 53183000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 890802000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 943985000 # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks 935266 # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total 935266 # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks 25 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total 25 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 882 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total 882 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 892857 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total 892857 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996599 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000176 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000176 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.015671 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.016591 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60503.981797 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60503.981797 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60503.981797 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 60500.224316 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60503.981797 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 60500.224316 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 879 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 879 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 157 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 157 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 14724 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 735633500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 735633500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 44393000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 44393000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7928500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7928500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44393000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 743562000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 787955000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44393000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 743562000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 787955000 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996599 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000176 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50503.981797 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50503.981797 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50503.981797 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.224316 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50503.981797 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.224316 # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 935266 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 25 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 209 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 882 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 892857 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1789 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814617 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 2816406 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58048 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 120047616 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 940453 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.000001 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.001031 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 940452 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 1 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 940453 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 1873267500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
-system.membus.snoop_filter.tot_requests 15603 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp 1036 # Transaction distribution
-system.membus.trans_dist::ReadExReq 14567 # Transaction distribution
-system.membus.trans_dist::ReadExResp 14567 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 1036 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 15603 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 15603 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 15603 # Request fanout histogram
-system.membus.reqLayer0.occupancy 15606500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 78015000 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
+sim_seconds 0.361613
+sim_ticks 361613361500
+final_tick 361613361500
+sim_freq 1000000000000
+host_inst_rate 812212
+host_op_rate 812245
+host_tick_rate 1204578633
+host_mem_usage 395932
+host_seconds 300.20
+sim_insts 243825150
+sim_ops 243835265
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 361613361500
+system.physmem.bytes_read::cpu.inst 56256
+system.physmem.bytes_read::cpu.data 942336
+system.physmem.bytes_read::total 998592
+system.physmem.bytes_inst_read::cpu.inst 56256
+system.physmem.bytes_inst_read::total 56256
+system.physmem.num_reads::cpu.inst 879
+system.physmem.num_reads::cpu.data 14724
+system.physmem.num_reads::total 15603
+system.physmem.bw_read::cpu.inst 155569
+system.physmem.bw_read::cpu.data 2605921
+system.physmem.bw_read::total 2761491
+system.physmem.bw_inst_read::cpu.inst 155569
+system.physmem.bw_inst_read::total 155569
+system.physmem.bw_total::cpu.inst 155569
+system.physmem.bw_total::cpu.data 2605921
+system.physmem.bw_total::total 2761491
+system.pwrStateResidencyTicks::UNDEFINED 361613361500
+system.cpu_clk_domain.clock 500
+system.cpu.workload.numSyscalls 443
+system.cpu.pwrStateResidencyTicks::ON 361613361500
+system.cpu.numCycles 723226723
+system.cpu.numWorkItemsStarted 0
+system.cpu.numWorkItemsCompleted 0
+system.cpu.committedInsts 243825150
+system.cpu.committedOps 243835265
+system.cpu.num_int_alu_accesses 194726494
+system.cpu.num_fp_alu_accesses 11630
+system.cpu.num_func_calls 4252956
+system.cpu.num_conditional_control_insts 18619959
+system.cpu.num_int_insts 194726494
+system.cpu.num_fp_insts 11630
+system.cpu.num_int_register_reads 456818988
+system.cpu.num_int_register_writes 215451553
+system.cpu.num_fp_register_reads 23256
+system.cpu.num_fp_register_writes 90
+system.cpu.num_mem_refs 105711441
+system.cpu.num_load_insts 82803521
+system.cpu.num_store_insts 22907920
+system.cpu.num_idle_cycles 0
+system.cpu.num_busy_cycles 723226723
+system.cpu.not_idle_fraction 1
+system.cpu.idle_fraction 0
+system.cpu.Branches 29302884
+system.cpu.op_class::No_OpClass 28877736 11.81% 11.81%
+system.cpu.op_class::IntAlu 109842388 44.94% 56.75%
+system.cpu.op_class::IntMult 0 0.00% 56.75%
+system.cpu.op_class::IntDiv 0 0.00% 56.75%
+system.cpu.op_class::FloatAdd 42 0.00% 56.75%
+system.cpu.op_class::FloatCmp 0 0.00% 56.75%
+system.cpu.op_class::FloatCvt 0 0.00% 56.75%
+system.cpu.op_class::FloatMult 0 0.00% 56.75%
+system.cpu.op_class::FloatMultAcc 0 0.00% 56.75%
+system.cpu.op_class::FloatDiv 0 0.00% 56.75%
+system.cpu.op_class::FloatMisc 0 0.00% 56.75%
+system.cpu.op_class::FloatSqrt 0 0.00% 56.75%
+system.cpu.op_class::SimdAdd 0 0.00% 56.75%
+system.cpu.op_class::SimdAddAcc 0 0.00% 56.75%
+system.cpu.op_class::SimdAlu 0 0.00% 56.75%
+system.cpu.op_class::SimdCmp 0 0.00% 56.75%
+system.cpu.op_class::SimdCvt 0 0.00% 56.75%
+system.cpu.op_class::SimdMisc 0 0.00% 56.75%
+system.cpu.op_class::SimdMult 0 0.00% 56.75%
+system.cpu.op_class::SimdMultAcc 0 0.00% 56.75%
+system.cpu.op_class::SimdShift 0 0.00% 56.75%
+system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75%
+system.cpu.op_class::SimdSqrt 0 0.00% 56.75%
+system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75%
+system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75%
+system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75%
+system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75%
+system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75%
+system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75%
+system.cpu.op_class::SimdFloatMult 0 0.00% 56.75%
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75%
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75%
+system.cpu.op_class::MemRead 82803516 33.88% 90.63%
+system.cpu.op_class::MemWrite 22896343 9.37% 100.00%
+system.cpu.op_class::FloatMemRead 11 0.00% 100.00%
+system.cpu.op_class::FloatMemWrite 11577 0.00% 100.00%
+system.cpu.op_class::IprAccess 0 0.00% 100.00%
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
+system.cpu.op_class::total 244431613
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500
+system.cpu.dcache.tags.replacements 935475
+system.cpu.dcache.tags.tagsinuse 3562.404243
+system.cpu.dcache.tags.total_refs 104186699
+system.cpu.dcache.tags.sampled_refs 939571
+system.cpu.dcache.tags.avg_refs 110.887521
+system.cpu.dcache.tags.warmup_cycle 134415942500
+system.cpu.dcache.tags.occ_blocks::cpu.data 3562.404243
+system.cpu.dcache.tags.occ_percent::cpu.data 0.869728
+system.cpu.dcache.tags.occ_percent::total 0.869728
+system.cpu.dcache.tags.occ_task_id_blocks::1024 4096
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 107
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 1416
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 2526
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 47
+system.cpu.dcache.tags.occ_task_id_percent::1024 1
+system.cpu.dcache.tags.tag_accesses 211192111
+system.cpu.dcache.tags.data_accesses 211192111
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 361613361500
+system.cpu.dcache.ReadReq_hits::cpu.data 81327576
+system.cpu.dcache.ReadReq_hits::total 81327576
+system.cpu.dcache.WriteReq_hits::cpu.data 22855241
+system.cpu.dcache.WriteReq_hits::total 22855241
+system.cpu.dcache.SwapReq_hits::cpu.data 3882
+system.cpu.dcache.SwapReq_hits::total 3882
+system.cpu.dcache.demand_hits::cpu.data 104182817
+system.cpu.dcache.demand_hits::total 104182817
+system.cpu.dcache.overall_hits::cpu.data 104182817
+system.cpu.dcache.overall_hits::total 104182817
+system.cpu.dcache.ReadReq_misses::cpu.data 892857
+system.cpu.dcache.ReadReq_misses::total 892857
+system.cpu.dcache.WriteReq_misses::cpu.data 46710
+system.cpu.dcache.WriteReq_misses::total 46710
+system.cpu.dcache.SwapReq_misses::cpu.data 4
+system.cpu.dcache.SwapReq_misses::total 4
+system.cpu.dcache.demand_misses::cpu.data 939567
+system.cpu.dcache.demand_misses::total 939567
+system.cpu.dcache.overall_misses::cpu.data 939567
+system.cpu.dcache.overall_misses::total 939567
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 11614992000
+system.cpu.dcache.ReadReq_miss_latency::total 11614992000
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 1335530000
+system.cpu.dcache.WriteReq_miss_latency::total 1335530000
+system.cpu.dcache.SwapReq_miss_latency::cpu.data 102000
+system.cpu.dcache.SwapReq_miss_latency::total 102000
+system.cpu.dcache.demand_miss_latency::cpu.data 12950522000
+system.cpu.dcache.demand_miss_latency::total 12950522000
+system.cpu.dcache.overall_miss_latency::cpu.data 12950522000
+system.cpu.dcache.overall_miss_latency::total 12950522000
+system.cpu.dcache.ReadReq_accesses::cpu.data 82220433
+system.cpu.dcache.ReadReq_accesses::total 82220433
+system.cpu.dcache.WriteReq_accesses::cpu.data 22901951
+system.cpu.dcache.WriteReq_accesses::total 22901951
+system.cpu.dcache.SwapReq_accesses::cpu.data 3886
+system.cpu.dcache.SwapReq_accesses::total 3886
+system.cpu.dcache.demand_accesses::cpu.data 105122384
+system.cpu.dcache.demand_accesses::total 105122384
+system.cpu.dcache.overall_accesses::cpu.data 105122384
+system.cpu.dcache.overall_accesses::total 105122384
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859
+system.cpu.dcache.ReadReq_miss_rate::total 0.010859
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040
+system.cpu.dcache.WriteReq_miss_rate::total 0.002040
+system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029
+system.cpu.dcache.SwapReq_miss_rate::total 0.001029
+system.cpu.dcache.demand_miss_rate::cpu.data 0.008938
+system.cpu.dcache.demand_miss_rate::total 0.008938
+system.cpu.dcache.overall_miss_rate::cpu.data 0.008938
+system.cpu.dcache.overall_miss_rate::total 0.008938
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.793121
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.793121
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28591.950332
+system.cpu.dcache.WriteReq_avg_miss_latency::total 28591.950332
+system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25500
+system.cpu.dcache.SwapReq_avg_miss_latency::total 25500
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 13783.500272
+system.cpu.dcache.demand_avg_miss_latency::total 13783.500272
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 13783.500272
+system.cpu.dcache.overall_avg_miss_latency::total 13783.500272
+system.cpu.dcache.blocked_cycles::no_mshrs 0
+system.cpu.dcache.blocked_cycles::no_targets 0
+system.cpu.dcache.blocked::no_mshrs 0
+system.cpu.dcache.blocked::no_targets 0
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
+system.cpu.dcache.avg_blocked_cycles::no_targets nan
+system.cpu.dcache.writebacks::writebacks 935266
+system.cpu.dcache.writebacks::total 935266
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857
+system.cpu.dcache.ReadReq_mshr_misses::total 892857
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710
+system.cpu.dcache.WriteReq_mshr_misses::total 46710
+system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4
+system.cpu.dcache.SwapReq_mshr_misses::total 4
+system.cpu.dcache.demand_mshr_misses::cpu.data 939567
+system.cpu.dcache.demand_mshr_misses::total 939567
+system.cpu.dcache.overall_mshr_misses::cpu.data 939567
+system.cpu.dcache.overall_mshr_misses::total 939567
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10722135000
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 10722135000
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1288820000
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 1288820000
+system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 98000
+system.cpu.dcache.SwapReq_mshr_miss_latency::total 98000
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12010955000
+system.cpu.dcache.demand_mshr_miss_latency::total 12010955000
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12010955000
+system.cpu.dcache.overall_mshr_miss_latency::total 12010955000
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040
+system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029
+system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938
+system.cpu.dcache.demand_mshr_miss_rate::total 0.008938
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938
+system.cpu.dcache.overall_mshr_miss_rate::total 0.008938
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.793121
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.793121
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27591.950332
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27591.950332
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24500
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24500
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12783.500272
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 12783.500272
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12783.500272
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 12783.500272
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500
+system.cpu.icache.tags.replacements 25
+system.cpu.icache.tags.tagsinuse 725.403723
+system.cpu.icache.tags.total_refs 244420617
+system.cpu.icache.tags.sampled_refs 882
+system.cpu.icache.tags.avg_refs 277120.880952
+system.cpu.icache.tags.warmup_cycle 0
+system.cpu.icache.tags.occ_blocks::cpu.inst 725.403723
+system.cpu.icache.tags.occ_percent::cpu.inst 0.354201
+system.cpu.icache.tags.occ_percent::total 0.354201
+system.cpu.icache.tags.occ_task_id_blocks::1024 857
+system.cpu.icache.tags.age_task_id_blocks_1024::0 53
+system.cpu.icache.tags.age_task_id_blocks_1024::2 12
+system.cpu.icache.tags.age_task_id_blocks_1024::3 11
+system.cpu.icache.tags.age_task_id_blocks_1024::4 781
+system.cpu.icache.tags.occ_task_id_percent::1024 0.418457
+system.cpu.icache.tags.tag_accesses 488843880
+system.cpu.icache.tags.data_accesses 488843880
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 361613361500
+system.cpu.icache.ReadReq_hits::cpu.inst 244420617
+system.cpu.icache.ReadReq_hits::total 244420617
+system.cpu.icache.demand_hits::cpu.inst 244420617
+system.cpu.icache.demand_hits::total 244420617
+system.cpu.icache.overall_hits::cpu.inst 244420617
+system.cpu.icache.overall_hits::total 244420617
+system.cpu.icache.ReadReq_misses::cpu.inst 882
+system.cpu.icache.ReadReq_misses::total 882
+system.cpu.icache.demand_misses::cpu.inst 882
+system.cpu.icache.demand_misses::total 882
+system.cpu.icache.overall_misses::cpu.inst 882
+system.cpu.icache.overall_misses::total 882
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 55422500
+system.cpu.icache.ReadReq_miss_latency::total 55422500
+system.cpu.icache.demand_miss_latency::cpu.inst 55422500
+system.cpu.icache.demand_miss_latency::total 55422500
+system.cpu.icache.overall_miss_latency::cpu.inst 55422500
+system.cpu.icache.overall_miss_latency::total 55422500
+system.cpu.icache.ReadReq_accesses::cpu.inst 244421499
+system.cpu.icache.ReadReq_accesses::total 244421499
+system.cpu.icache.demand_accesses::cpu.inst 244421499
+system.cpu.icache.demand_accesses::total 244421499
+system.cpu.icache.overall_accesses::cpu.inst 244421499
+system.cpu.icache.overall_accesses::total 244421499
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004
+system.cpu.icache.ReadReq_miss_rate::total 0.000004
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000004
+system.cpu.icache.demand_miss_rate::total 0.000004
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000004
+system.cpu.icache.overall_miss_rate::total 0.000004
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62837.301587
+system.cpu.icache.ReadReq_avg_miss_latency::total 62837.301587
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 62837.301587
+system.cpu.icache.demand_avg_miss_latency::total 62837.301587
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 62837.301587
+system.cpu.icache.overall_avg_miss_latency::total 62837.301587
+system.cpu.icache.blocked_cycles::no_mshrs 0
+system.cpu.icache.blocked_cycles::no_targets 0
+system.cpu.icache.blocked::no_mshrs 0
+system.cpu.icache.blocked::no_targets 0
+system.cpu.icache.avg_blocked_cycles::no_mshrs nan
+system.cpu.icache.avg_blocked_cycles::no_targets nan
+system.cpu.icache.writebacks::writebacks 25
+system.cpu.icache.writebacks::total 25
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882
+system.cpu.icache.ReadReq_mshr_misses::total 882
+system.cpu.icache.demand_mshr_misses::cpu.inst 882
+system.cpu.icache.demand_mshr_misses::total 882
+system.cpu.icache.overall_mshr_misses::cpu.inst 882
+system.cpu.icache.overall_mshr_misses::total 882
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54540500
+system.cpu.icache.ReadReq_mshr_miss_latency::total 54540500
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54540500
+system.cpu.icache.demand_mshr_miss_latency::total 54540500
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54540500
+system.cpu.icache.overall_mshr_miss_latency::total 54540500
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004
+system.cpu.icache.demand_mshr_miss_rate::total 0.000004
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004
+system.cpu.icache.overall_mshr_miss_rate::total 0.000004
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61837.301587
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61837.301587
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61837.301587
+system.cpu.icache.demand_avg_mshr_miss_latency::total 61837.301587
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61837.301587
+system.cpu.icache.overall_avg_mshr_miss_latency::total 61837.301587
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500
+system.cpu.l2cache.tags.replacements 0
+system.cpu.l2cache.tags.tagsinuse 10855.563013
+system.cpu.l2cache.tags.total_refs 1860349
+system.cpu.l2cache.tags.sampled_refs 15603
+system.cpu.l2cache.tags.avg_refs 119.230212
+system.cpu.l2cache.tags.warmup_cycle 0
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.626846
+system.cpu.l2cache.tags.occ_blocks::cpu.data 10116.936167
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.308744
+system.cpu.l2cache.tags.occ_percent::total 0.331285
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 15603
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 64
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15465
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.476166
+system.cpu.l2cache.tags.tag_accesses 15023219
+system.cpu.l2cache.tags.data_accesses 15023219
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 361613361500
+system.cpu.l2cache.WritebackDirty_hits::writebacks 935266
+system.cpu.l2cache.WritebackDirty_hits::total 935266
+system.cpu.l2cache.WritebackClean_hits::writebacks 25
+system.cpu.l2cache.WritebackClean_hits::total 25
+system.cpu.l2cache.ReadExReq_hits::cpu.data 32147
+system.cpu.l2cache.ReadExReq_hits::total 32147
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3
+system.cpu.l2cache.ReadCleanReq_hits::total 3
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data 892700
+system.cpu.l2cache.ReadSharedReq_hits::total 892700
+system.cpu.l2cache.demand_hits::cpu.inst 3
+system.cpu.l2cache.demand_hits::cpu.data 924847
+system.cpu.l2cache.demand_hits::total 924850
+system.cpu.l2cache.overall_hits::cpu.inst 3
+system.cpu.l2cache.overall_hits::cpu.data 924847
+system.cpu.l2cache.overall_hits::total 924850
+system.cpu.l2cache.ReadExReq_misses::cpu.data 14567
+system.cpu.l2cache.ReadExReq_misses::total 14567
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 879
+system.cpu.l2cache.ReadCleanReq_misses::total 879
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data 157
+system.cpu.l2cache.ReadSharedReq_misses::total 157
+system.cpu.l2cache.demand_misses::cpu.inst 879
+system.cpu.l2cache.demand_misses::cpu.data 14724
+system.cpu.l2cache.demand_misses::total 15603
+system.cpu.l2cache.overall_misses::cpu.inst 879
+system.cpu.l2cache.overall_misses::cpu.data 14724
+system.cpu.l2cache.overall_misses::total 15603
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 881303500
+system.cpu.l2cache.ReadExReq_miss_latency::total 881303500
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 53183000
+system.cpu.l2cache.ReadCleanReq_miss_latency::total 53183000
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9498500
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 9498500
+system.cpu.l2cache.demand_miss_latency::cpu.inst 53183000
+system.cpu.l2cache.demand_miss_latency::cpu.data 890802000
+system.cpu.l2cache.demand_miss_latency::total 943985000
+system.cpu.l2cache.overall_miss_latency::cpu.inst 53183000
+system.cpu.l2cache.overall_miss_latency::cpu.data 890802000
+system.cpu.l2cache.overall_miss_latency::total 943985000
+system.cpu.l2cache.WritebackDirty_accesses::writebacks 935266
+system.cpu.l2cache.WritebackDirty_accesses::total 935266
+system.cpu.l2cache.WritebackClean_accesses::writebacks 25
+system.cpu.l2cache.WritebackClean_accesses::total 25
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714
+system.cpu.l2cache.ReadExReq_accesses::total 46714
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 882
+system.cpu.l2cache.ReadCleanReq_accesses::total 882
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 892857
+system.cpu.l2cache.ReadSharedReq_accesses::total 892857
+system.cpu.l2cache.demand_accesses::cpu.inst 882
+system.cpu.l2cache.demand_accesses::cpu.data 939571
+system.cpu.l2cache.demand_accesses::total 940453
+system.cpu.l2cache.overall_accesses::cpu.inst 882
+system.cpu.l2cache.overall_accesses::cpu.data 939571
+system.cpu.l2cache.overall_accesses::total 940453
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996599
+system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996599
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000176
+system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000176
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.015671
+system.cpu.l2cache.demand_miss_rate::total 0.016591
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671
+system.cpu.l2cache.overall_miss_rate::total 0.016591
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60503.981797
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60503.981797
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60503.981797
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500
+system.cpu.l2cache.demand_avg_miss_latency::total 60500.224316
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60503.981797
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500
+system.cpu.l2cache.overall_avg_miss_latency::total 60500.224316
+system.cpu.l2cache.blocked_cycles::no_mshrs 0
+system.cpu.l2cache.blocked_cycles::no_targets 0
+system.cpu.l2cache.blocked::no_mshrs 0
+system.cpu.l2cache.blocked::no_targets 0
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567
+system.cpu.l2cache.ReadExReq_mshr_misses::total 14567
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 879
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 879
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 157
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 157
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 879
+system.cpu.l2cache.demand_mshr_misses::cpu.data 14724
+system.cpu.l2cache.demand_mshr_misses::total 15603
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 879
+system.cpu.l2cache.overall_mshr_misses::cpu.data 14724
+system.cpu.l2cache.overall_mshr_misses::total 15603
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 735633500
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 735633500
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 44393000
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 44393000
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7928500
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7928500
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44393000
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 743562000
+system.cpu.l2cache.demand_mshr_miss_latency::total 787955000
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44393000
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 743562000
+system.cpu.l2cache.overall_mshr_miss_latency::total 787955000
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996599
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996599
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000176
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000176
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015671
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50503.981797
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50503.981797
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50503.981797
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.224316
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50503.981797
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.224316
+system.cpu.toL2Bus.snoop_filter.tot_requests 1875953
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1
+system.cpu.toL2Bus.snoop_filter.tot_snoops 0
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 361613361500
+system.cpu.toL2Bus.trans_dist::ReadResp 893739
+system.cpu.toL2Bus.trans_dist::WritebackDirty 935266
+system.cpu.toL2Bus.trans_dist::WritebackClean 25
+system.cpu.toL2Bus.trans_dist::CleanEvict 209
+system.cpu.toL2Bus.trans_dist::ReadExReq 46714
+system.cpu.toL2Bus.trans_dist::ReadExResp 46714
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 882
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 892857
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1789
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814617
+system.cpu.toL2Bus.pkt_count::total 2816406
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58048
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568
+system.cpu.toL2Bus.pkt_size::total 120047616
+system.cpu.toL2Bus.snoops 0
+system.cpu.toL2Bus.snoopTraffic 0
+system.cpu.toL2Bus.snoop_fanout::samples 940453
+system.cpu.toL2Bus.snoop_fanout::mean 0.000001
+system.cpu.toL2Bus.snoop_fanout::stdev 0.001031
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu.toL2Bus.snoop_fanout::0 940452 100.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::1 1 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::min_value 0
+system.cpu.toL2Bus.snoop_fanout::max_value 1
+system.cpu.toL2Bus.snoop_fanout::total 940453
+system.cpu.toL2Bus.reqLayer0.occupancy 1873267500
+system.cpu.toL2Bus.reqLayer0.utilization 0.5
+system.cpu.toL2Bus.respLayer0.occupancy 1323000
+system.cpu.toL2Bus.respLayer0.utilization 0.0
+system.cpu.toL2Bus.respLayer1.occupancy 1409356500
+system.cpu.toL2Bus.respLayer1.utilization 0.4
+system.membus.snoop_filter.tot_requests 15603
+system.membus.snoop_filter.hit_single_requests 0
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 361613361500
+system.membus.trans_dist::ReadResp 1036
+system.membus.trans_dist::ReadExReq 14567
+system.membus.trans_dist::ReadExResp 14567
+system.membus.trans_dist::ReadSharedReq 1036
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206
+system.membus.pkt_count::total 31206
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592
+system.membus.pkt_size::total 998592
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 15603
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 15603 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 15603
+system.membus.reqLayer0.occupancy 15606500
+system.membus.reqLayer0.utilization 0.0
+system.membus.respLayer1.occupancy 78015000
+system.membus.respLayer1.utilization 0.0
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
index e54b7db9f..ebb274721 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
@@ -20,6 +20,7 @@ exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
+kvm_vm=Null
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
@@ -65,7 +66,7 @@ SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
-cachePorts=200
+cacheStorePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
@@ -139,6 +140,7 @@ socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -183,10 +185,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@@ -200,6 +202,7 @@ response_latency=2
sequential_access=false
size=262144
system=system
+tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@@ -212,15 +215,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
+tag_latency=2
[system.cpu.dtb]
type=X86TLB
@@ -313,10 +317,10 @@ pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
-children=opList0 opList1 opList2
+children=opList0 opList1 opList2 opList3 opList4
count=2
eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
@@ -328,11 +332,25 @@ pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
+opClass=FloatMultAcc
+opLat=5
+pipelined=true
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+eventq_index=0
+opClass=FloatMisc
+opLat=3
+pipelined=true
+
+[system.cpu.fuPool.FUList3.opList3]
+type=OpDesc
+eventq_index=0
opClass=FloatDiv
opLat=12
pipelined=false
-[system.cpu.fuPool.FUList3.opList2]
+[system.cpu.fuPool.FUList3.opList4]
type=OpDesc
eventq_index=0
opClass=FloatSqrt
@@ -341,18 +359,25 @@ pipelined=false
[system.cpu.fuPool.FUList4]
type=FUDesc
-children=opList
+children=opList0 opList1
count=0
eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList
+opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1
-[system.cpu.fuPool.FUList4.opList]
+[system.cpu.fuPool.FUList4.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
+[system.cpu.fuPool.FUList4.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemRead
+opLat=1
+pipelined=true
+
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
@@ -502,24 +527,31 @@ pipelined=true
[system.cpu.fuPool.FUList6]
type=FUDesc
-children=opList
+children=opList0 opList1
count=0
eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-[system.cpu.fuPool.FUList6.opList]
+[system.cpu.fuPool.FUList6.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemWrite
+opLat=1
+pipelined=true
+
[system.cpu.fuPool.FUList7]
type=FUDesc
-children=opList0 opList1
+children=opList0 opList1 opList2 opList3
count=4
eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
@@ -535,6 +567,20 @@ opClass=MemWrite
opLat=1
pipelined=true
+[system.cpu.fuPool.FUList7.opList2]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemRead
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList7.opList3]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemWrite
+opLat=1
+pipelined=true
+
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
@@ -556,10 +602,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@@ -573,6 +619,7 @@ response_latency=2
sequential_access=false
size=131072
system=system
+tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@@ -585,15 +632,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
+tag_latency=2
[system.cpu.interrupts]
type=X86LocalApic
@@ -643,10 +691,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@@ -660,6 +708,7 @@ response_latency=20
sequential_access=false
size=2097152
system=system
+tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@@ -672,15 +721,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=20
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
+tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -716,7 +766,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=mcf mcf.in
cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
drivers=
@@ -725,14 +775,15 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/mcf
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/mcf
gid=100
-input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=55300000000
system=system
uid=100
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr
index 36f24465c..5d01a7eba 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr
@@ -1,3 +1,6 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
index 9e929c5a5..fa6158a9b 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
@@ -3,13 +3,12 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/sim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 21:08:11
-gem5 executing on e108600-lin, pid 17630
-command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/x86/linux/o3-timing
+gem5 compiled Apr 3 2017 19:05:53
+gem5 started Apr 3 2017 19:06:21
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87177
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/10.mcf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I
by Andreas Loebel
@@ -19,13 +18,11 @@ All Rights Reserved.
nodes : 500
active arcs : 1905
simplex iterations : 1502
-info: Increasing stack size by one page.
flow value : 4990014995
-info: Increasing stack size by one page.
new implicit arcs : 23867
active arcs : 25772
simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 66079350000 because target called exit()
+Exiting @ tick 65721494500 because exiting with last active thread context
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
index 492625dc5..b9b8eb4c6 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
@@ -1,1055 +1,1055 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.065721 # Number of seconds simulated
-sim_ticks 65721494500 # Number of ticks simulated
-final_tick 65721494500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 191999 # Simulator instruction rate (inst/s)
-host_op_rate 338080 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 79869594 # Simulator tick rate (ticks/s)
-host_mem_usage 415448 # Number of bytes of host memory used
-host_seconds 822.86 # Real time elapsed on the host
-sim_insts 157988547 # Number of instructions simulated
-sim_ops 278192464 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 68800 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1892544 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1961344 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 68800 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 68800 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 19136 # Number of bytes written to this memory
-system.physmem.bytes_written::total 19136 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 1075 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 29571 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 30646 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 299 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 299 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1046842 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 28796424 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 29843265 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1046842 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1046842 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 291168 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 291168 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 291168 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1046842 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 28796424 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 30134433 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 30646 # Number of read requests accepted
-system.physmem.writeReqs 299 # Number of write requests accepted
-system.physmem.readBursts 30646 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 299 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 1952832 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 8512 # Total number of bytes read from write queue
-system.physmem.bytesWritten 17216 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 1961344 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 19136 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 133 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 1937 # Per bank write bursts
-system.physmem.perBankRdBursts::1 2081 # Per bank write bursts
-system.physmem.perBankRdBursts::2 2039 # Per bank write bursts
-system.physmem.perBankRdBursts::3 1941 # Per bank write bursts
-system.physmem.perBankRdBursts::4 2068 # Per bank write bursts
-system.physmem.perBankRdBursts::5 1911 # Per bank write bursts
-system.physmem.perBankRdBursts::6 1977 # Per bank write bursts
-system.physmem.perBankRdBursts::7 1878 # Per bank write bursts
-system.physmem.perBankRdBursts::8 1945 # Per bank write bursts
-system.physmem.perBankRdBursts::9 1939 # Per bank write bursts
-system.physmem.perBankRdBursts::10 1805 # Per bank write bursts
-system.physmem.perBankRdBursts::11 1794 # Per bank write bursts
-system.physmem.perBankRdBursts::12 1792 # Per bank write bursts
-system.physmem.perBankRdBursts::13 1800 # Per bank write bursts
-system.physmem.perBankRdBursts::14 1827 # Per bank write bursts
-system.physmem.perBankRdBursts::15 1779 # Per bank write bursts
-system.physmem.perBankWrBursts::0 8 # Per bank write bursts
-system.physmem.perBankWrBursts::1 125 # Per bank write bursts
-system.physmem.perBankWrBursts::2 25 # Per bank write bursts
-system.physmem.perBankWrBursts::3 26 # Per bank write bursts
-system.physmem.perBankWrBursts::4 54 # Per bank write bursts
-system.physmem.perBankWrBursts::5 8 # Per bank write bursts
-system.physmem.perBankWrBursts::6 14 # Per bank write bursts
-system.physmem.perBankWrBursts::7 0 # Per bank write bursts
-system.physmem.perBankWrBursts::8 0 # Per bank write bursts
-system.physmem.perBankWrBursts::9 6 # Per bank write bursts
-system.physmem.perBankWrBursts::10 3 # Per bank write bursts
-system.physmem.perBankWrBursts::11 0 # Per bank write bursts
-system.physmem.perBankWrBursts::12 0 # Per bank write bursts
-system.physmem.perBankWrBursts::13 0 # Per bank write bursts
-system.physmem.perBankWrBursts::14 0 # Per bank write bursts
-system.physmem.perBankWrBursts::15 0 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 65721290500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 0 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 30646 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 0 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 299 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 29942 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 423 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 106 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 15 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 15 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 15 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 2852 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 690.064516 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 482.522488 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 397.377699 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 418 14.66% 14.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 289 10.13% 24.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 128 4.49% 29.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 119 4.17% 33.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 133 4.66% 38.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 123 4.31% 42.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 83 2.91% 45.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 90 3.16% 48.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 1469 51.51% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 2852 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 15 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 2030.466667 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean 23.801531 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 7801.447410 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 14 93.33% 93.33% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::29696-30719 1 6.67% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 15 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 15 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.933333 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.931540 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 0.258199 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 1 6.67% 6.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 14 93.33% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 15 # Writes before turning the bus around for reads
-system.physmem.totQLat 402617750 # Total ticks spent queuing
-system.physmem.totMemAccLat 974736500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 152565000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 13194.96 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 31944.96 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 29.71 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 0.26 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 29.84 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 0.29 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.23 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 12.51 # Average write queue length when enqueuing
-system.physmem.readRowHits 27734 # Number of row buffer hits during reads
-system.physmem.writeRowHits 187 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 90.89 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 62.54 # Row buffer hit rate for writes
-system.physmem.avgGap 2123809.68 # Average gap between requests
-system.physmem.pageHitRate 90.62 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 11052720 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 5855685 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 113040480 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 1357200 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 309163920.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 263324610 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 16569120 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 979073610 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 268447200 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 14975920920 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 16943805465 # Total energy per rank (pJ)
-system.physmem_0.averagePower 257.812234 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 65100637750 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 22061500 # Time in different power states
-system.physmem_0.memoryStateTime::REF 131194000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 62254705500 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 699065250 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 467433500 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 2147034750 # Time in different power states
-system.physmem_1.actEnergy 9374820 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 4967655 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 104822340 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 46980 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 372471840.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 249536310 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 19488480 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 1119740490 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 403290240 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 14835337125 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 17119488570 # Total energy per rank (pJ)
-system.physmem_1.averagePower 260.485370 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 65120969250 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 28589000 # Time in different power states
-system.physmem_1.memoryStateTime::REF 158136000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 61616793750 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 1050209250 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 412212500 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 2455554000 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 40406290 # Number of BP lookups
-system.cpu.branchPred.condPredicted 40406290 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1431845 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 26031629 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 0 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 6025963 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 91921 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 26031629 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 20992529 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 5039100 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 530263 # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states
-system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states
-system.cpu.workload.numSyscalls 444 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 65721494500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 131442990 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 30464048 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 219898668 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 40406290 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 27018492 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 99269738 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 2979935 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 465 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 7592 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 128961 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 50 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 174 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 29660171 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 359072 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 17 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 131360995 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.946103 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.409063 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 65827184 50.11% 50.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 4032527 3.07% 53.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 3600376 2.74% 55.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 6081929 4.63% 60.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 7728911 5.88% 66.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 5535416 4.21% 70.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 3331669 2.54% 73.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 2842658 2.16% 75.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 32380325 24.65% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 131360995 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.307405 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.672959 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 15255907 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 64520496 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 40208811 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 9885814 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1489967 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 362265652 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 1489967 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 20796133 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 11129664 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 23832 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 44255424 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 53665975 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 352608748 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 23342 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 777450 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 46732943 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 5205031 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 354925639 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 934456502 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 575559102 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 21159 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 75712892 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 482 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 483 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 64647332 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 112313472 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 38475522 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 51426374 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 8868395 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 343765046 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 3883 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 317634440 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 163759 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 65576465 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 101836454 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 3438 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 131360995 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.418027 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.167913 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 35651981 27.14% 27.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 20061286 15.27% 42.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 17078933 13.00% 55.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 17586289 13.39% 68.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 15273572 11.63% 80.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 12870930 9.80% 90.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 6718617 5.11% 95.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 4059315 3.09% 98.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 2060072 1.57% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 131360995 # Number of insts issued each cycle
-system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 367555 8.92% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMisc 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 3559749 86.40% 95.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 191317 4.64% 99.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemRead 13 0.00% 99.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemWrite 1395 0.03% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 33339 0.01% 0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 181647745 57.19% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 11501 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 497 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 296 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 101245285 31.87% 89.08% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 34690277 10.92% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemRead 508 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemWrite 4992 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 317634440 # Type of FU issued
-system.cpu.iq.rate 2.416519 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 4120029 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.012971 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 770896978 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 409373525 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 313389776 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 16685 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 31480 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 3775 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 321713926 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 7204 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 57497351 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 21534087 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 66072 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 62227 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 7035770 # Number of stores squashed
-system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 4204 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 141777 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1489967 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 8057522 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 2987683 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 343768929 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 139556 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 112313472 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 38475522 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1604 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 2862 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 2991864 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 62227 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 520614 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 1090823 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1611437 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 315197484 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 100490397 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2436956 # Number of squashed instructions skipped in execute
-system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 134782236 # number of memory reference insts executed
-system.cpu.iew.exec_branches 32089039 # Number of branches executed
-system.cpu.iew.exec_stores 34291839 # Number of stores executed
-system.cpu.iew.exec_rate 2.397979 # Inst execution rate
-system.cpu.iew.wb_sent 314036708 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 313393551 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 237399400 # num instructions producing a value
-system.cpu.iew.wb_consumers 342887037 # num instructions consuming a value
-system.cpu.iew.wb_rate 2.384255 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.692355 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 65692241 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1439325 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 121896437 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.282203 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 3.051706 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 56939574 46.71% 46.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 16454719 13.50% 60.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 11025665 9.05% 69.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 8756483 7.18% 76.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 2109912 1.73% 78.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1768746 1.45% 79.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 935268 0.77% 80.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 726580 0.60% 80.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 23179490 19.02% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 121896437 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 157988547 # Number of instructions committed
-system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed
-system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 122219137 # Number of memory references committed
-system.cpu.commit.loads 90779385 # Number of loads committed
-system.cpu.commit.membars 0 # Number of memory barriers committed
-system.cpu.commit.branches 29309705 # Number of branches committed
-system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 278169481 # Number of committed integer instructions.
-system.cpu.commit.function_calls 4237596 # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass 16695 0.01% 0.01% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 155945353 56.06% 56.06% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 10938 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 329 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd 12 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMisc 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 90779371 32.63% 88.70% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 31439738 11.30% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemRead 14 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemWrite 14 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction
-system.cpu.commit.bw_lim_events 23179490 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 442601652 # The number of ROB reads
-system.cpu.rob.rob_writes 697313320 # The number of ROB writes
-system.cpu.timesIdled 909 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 81995 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 157988547 # Number of Instructions Simulated
-system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.831978 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.831978 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.201955 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.201955 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 502529726 # number of integer regfile reads
-system.cpu.int_regfile_writes 247564665 # number of integer regfile writes
-system.cpu.fp_regfile_reads 3566 # number of floating regfile reads
-system.cpu.fp_regfile_writes 731 # number of floating regfile writes
-system.cpu.cc_regfile_reads 108994485 # number of cc regfile reads
-system.cpu.cc_regfile_writes 65428204 # number of cc regfile writes
-system.cpu.misc_regfile_reads 201784346 # number of misc regfile reads
-system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 2073509 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4067.268199 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 71482624 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 2077605 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 34.406263 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 21075173500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4067.268199 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.992985 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.992985 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 504 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 3445 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 147 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 150633517 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 150633517 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 40136683 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 40136683 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 31345941 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 31345941 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 71482624 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 71482624 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 71482624 # number of overall hits
-system.cpu.dcache.overall_hits::total 71482624 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 2701521 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 2701521 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 93811 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 93811 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 2795332 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2795332 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2795332 # number of overall misses
-system.cpu.dcache.overall_misses::total 2795332 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 32454671000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 32454671000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 3177582491 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 3177582491 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 35632253491 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 35632253491 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 35632253491 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 35632253491 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 42838204 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 42838204 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 74277956 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 74277956 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 74277956 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 74277956 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.063063 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.063063 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002984 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.002984 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12013.480924 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 12013.480924 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33872.173743 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 33872.173743 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 12747.055982 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 12747.055982 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 12747.055982 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 12747.055982 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 219709 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 682 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 43158 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 6 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.090806 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 113.666667 # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks 2066902 # number of writebacks
-system.cpu.dcache.writebacks::total 2066902 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 705827 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 705827 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11900 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 11900 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 717727 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 717727 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 717727 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 717727 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995694 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1995694 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81911 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 81911 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2077605 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2077605 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2077605 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2077605 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24272933500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 24272933500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3020316491 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3020316491 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27293249991 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 27293249991 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27293249991 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 27293249991 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046587 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046587 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002605 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002605 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027971 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.027971 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027971 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.027971 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12162.652942 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12162.652942 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36873.148796 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36873.148796 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13136.881164 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 13136.881164 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13136.881164 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 13136.881164 # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements 86 # number of replacements
-system.cpu.icache.tags.tagsinuse 865.699388 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 29658716 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 1101 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 26937.980018 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 865.699388 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.422705 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.422705 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 1015 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 900 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.495605 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 59321439 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 59321439 # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst 29658716 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 29658716 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 29658716 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 29658716 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 29658716 # number of overall hits
-system.cpu.icache.overall_hits::total 29658716 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1453 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1453 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1453 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1453 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1453 # number of overall misses
-system.cpu.icache.overall_misses::total 1453 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 154504998 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 154504998 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 154504998 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 154504998 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 154504998 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 154504998 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 29660169 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 29660169 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 29660169 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 29660169 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 29660169 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 29660169 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000049 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000049 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000049 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000049 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000049 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000049 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 106335.167240 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 106335.167240 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 106335.167240 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 106335.167240 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 106335.167240 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 106335.167240 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 4008 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 235.764706 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks 86 # number of writebacks
-system.cpu.icache.writebacks::total 86 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 352 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 352 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 352 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 352 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 352 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 352 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1101 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 1101 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 1101 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 1101 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 1101 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 1101 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 113239998 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 113239998 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 113239998 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 113239998 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 113239998 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 113239998 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 102851.950954 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 102851.950954 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 102851.950954 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 102851.950954 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 102851.950954 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 102851.950954 # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements 680 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 21650.115816 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 4121613 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 30665 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 134.407729 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 3.138386 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 704.921194 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 20942.056236 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.000096 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.021512 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.639101 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.660709 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 29985 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 172 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 54 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29640 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.915070 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 33248889 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 33248889 # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks 2066902 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total 2066902 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks 86 # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total 86 # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 52946 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 52946 # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 26 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total 26 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1995088 # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total 1995088 # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 2048034 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2048060 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 2048034 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2048060 # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data 28996 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 28996 # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1075 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total 1075 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data 575 # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total 575 # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 1075 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 29571 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 30646 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 1075 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 29571 # number of overall misses
-system.cpu.l2cache.overall_misses::total 30646 # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2341147500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 2341147500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 111300000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total 111300000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 88414500 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 88414500 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 111300000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 2429562000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 2540862000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 111300000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 2429562000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 2540862000 # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks 2066902 # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total 2066902 # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks 86 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total 86 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 81942 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 81942 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1101 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total 1101 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1995663 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total 1995663 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 1101 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 2077605 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 2078706 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 1101 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 2077605 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 2078706 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353860 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.353860 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.976385 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.976385 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000288 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000288 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.976385 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.014233 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.014743 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.976385 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.014233 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.014743 # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80740.360739 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80740.360739 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 103534.883721 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 103534.883721 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 153764.347826 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 153764.347826 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 103534.883721 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82160.292178 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 82910.069830 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 103534.883721 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82160.292178 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 82910.069830 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks 299 # number of writebacks
-system.cpu.l2cache.writebacks::total 299 # number of writebacks
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28996 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 28996 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1075 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1075 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 575 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 575 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 1075 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 29571 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 30646 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 1075 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 29571 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 30646 # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2051187500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2051187500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 100550000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 100550000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 82664500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 82664500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 100550000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2133852000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 2234402000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 100550000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2133852000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 2234402000 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353860 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353860 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.976385 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.976385 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000288 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000288 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.976385 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014233 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.014743 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.976385 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014233 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.014743 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70740.360739 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70740.360739 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93534.883721 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93534.883721 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 143764.347826 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 143764.347826 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93534.883721 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72160.292178 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72910.069830 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93534.883721 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72160.292178 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72910.069830 # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests 4152301 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073596 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 330 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 330 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp 1996764 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 2067201 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 86 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 6988 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 81942 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 81942 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 1101 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995663 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2288 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228719 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 6231007 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 75968 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265248448 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 265324416 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 680 # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic 19136 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 2079386 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.000170 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.013047 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 2079032 99.98% 99.98% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 354 0.02% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 2079386 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 4143138500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1652498 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3116407500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 4.7 # Layer utilization (%)
-system.membus.snoop_filter.tot_requests 30996 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 350 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp 1650 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 299 # Transaction distribution
-system.membus.trans_dist::CleanEvict 51 # Transaction distribution
-system.membus.trans_dist::ReadExReq 28996 # Transaction distribution
-system.membus.trans_dist::ReadExResp 28996 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 1650 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61642 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61642 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 61642 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1980480 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1980480 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 1980480 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 30646 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 30646 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 30646 # Request fanout histogram
-system.membus.reqLayer0.occupancy 43591500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer1.occupancy 161486250 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
+sim_seconds 0.065721
+sim_ticks 65721494500
+final_tick 65721494500
+sim_freq 1000000000000
+host_inst_rate 83517
+host_op_rate 147060
+host_tick_rate 34742064
+host_mem_usage 427260
+host_seconds 1891.70
+sim_insts 157988547
+sim_ops 278192464
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 65721494500
+system.physmem.bytes_read::cpu.inst 68800
+system.physmem.bytes_read::cpu.data 1892544
+system.physmem.bytes_read::total 1961344
+system.physmem.bytes_inst_read::cpu.inst 68800
+system.physmem.bytes_inst_read::total 68800
+system.physmem.bytes_written::writebacks 19136
+system.physmem.bytes_written::total 19136
+system.physmem.num_reads::cpu.inst 1075
+system.physmem.num_reads::cpu.data 29571
+system.physmem.num_reads::total 30646
+system.physmem.num_writes::writebacks 299
+system.physmem.num_writes::total 299
+system.physmem.bw_read::cpu.inst 1046842
+system.physmem.bw_read::cpu.data 28796424
+system.physmem.bw_read::total 29843265
+system.physmem.bw_inst_read::cpu.inst 1046842
+system.physmem.bw_inst_read::total 1046842
+system.physmem.bw_write::writebacks 291168
+system.physmem.bw_write::total 291168
+system.physmem.bw_total::writebacks 291168
+system.physmem.bw_total::cpu.inst 1046842
+system.physmem.bw_total::cpu.data 28796424
+system.physmem.bw_total::total 30134433
+system.physmem.readReqs 30646
+system.physmem.writeReqs 299
+system.physmem.readBursts 30646
+system.physmem.writeBursts 299
+system.physmem.bytesReadDRAM 1952832
+system.physmem.bytesReadWrQ 8512
+system.physmem.bytesWritten 17216
+system.physmem.bytesReadSys 1961344
+system.physmem.bytesWrittenSys 19136
+system.physmem.servicedByWrQ 133
+system.physmem.mergedWrBursts 0
+system.physmem.neitherReadNorWriteReqs 0
+system.physmem.perBankRdBursts::0 1937
+system.physmem.perBankRdBursts::1 2081
+system.physmem.perBankRdBursts::2 2039
+system.physmem.perBankRdBursts::3 1941
+system.physmem.perBankRdBursts::4 2068
+system.physmem.perBankRdBursts::5 1911
+system.physmem.perBankRdBursts::6 1977
+system.physmem.perBankRdBursts::7 1878
+system.physmem.perBankRdBursts::8 1945
+system.physmem.perBankRdBursts::9 1939
+system.physmem.perBankRdBursts::10 1805
+system.physmem.perBankRdBursts::11 1794
+system.physmem.perBankRdBursts::12 1792
+system.physmem.perBankRdBursts::13 1800
+system.physmem.perBankRdBursts::14 1827
+system.physmem.perBankRdBursts::15 1779
+system.physmem.perBankWrBursts::0 8
+system.physmem.perBankWrBursts::1 125
+system.physmem.perBankWrBursts::2 25
+system.physmem.perBankWrBursts::3 26
+system.physmem.perBankWrBursts::4 54
+system.physmem.perBankWrBursts::5 8
+system.physmem.perBankWrBursts::6 14
+system.physmem.perBankWrBursts::7 0
+system.physmem.perBankWrBursts::8 0
+system.physmem.perBankWrBursts::9 6
+system.physmem.perBankWrBursts::10 3
+system.physmem.perBankWrBursts::11 0
+system.physmem.perBankWrBursts::12 0
+system.physmem.perBankWrBursts::13 0
+system.physmem.perBankWrBursts::14 0
+system.physmem.perBankWrBursts::15 0
+system.physmem.numRdRetry 0
+system.physmem.numWrRetry 0
+system.physmem.totGap 65721290500
+system.physmem.readPktSize::0 0
+system.physmem.readPktSize::1 0
+system.physmem.readPktSize::2 0
+system.physmem.readPktSize::3 0
+system.physmem.readPktSize::4 0
+system.physmem.readPktSize::5 0
+system.physmem.readPktSize::6 30646
+system.physmem.writePktSize::0 0
+system.physmem.writePktSize::1 0
+system.physmem.writePktSize::2 0
+system.physmem.writePktSize::3 0
+system.physmem.writePktSize::4 0
+system.physmem.writePktSize::5 0
+system.physmem.writePktSize::6 299
+system.physmem.rdQLenPdf::0 29942
+system.physmem.rdQLenPdf::1 423
+system.physmem.rdQLenPdf::2 106
+system.physmem.rdQLenPdf::3 36
+system.physmem.rdQLenPdf::4 5
+system.physmem.rdQLenPdf::5 1
+system.physmem.rdQLenPdf::6 0
+system.physmem.rdQLenPdf::7 0
+system.physmem.rdQLenPdf::8 0
+system.physmem.rdQLenPdf::9 0
+system.physmem.rdQLenPdf::10 0
+system.physmem.rdQLenPdf::11 0
+system.physmem.rdQLenPdf::12 0
+system.physmem.rdQLenPdf::13 0
+system.physmem.rdQLenPdf::14 0
+system.physmem.rdQLenPdf::15 0
+system.physmem.rdQLenPdf::16 0
+system.physmem.rdQLenPdf::17 0
+system.physmem.rdQLenPdf::18 0
+system.physmem.rdQLenPdf::19 0
+system.physmem.rdQLenPdf::20 0
+system.physmem.rdQLenPdf::21 0
+system.physmem.rdQLenPdf::22 0
+system.physmem.rdQLenPdf::23 0
+system.physmem.rdQLenPdf::24 0
+system.physmem.rdQLenPdf::25 0
+system.physmem.rdQLenPdf::26 0
+system.physmem.rdQLenPdf::27 0
+system.physmem.rdQLenPdf::28 0
+system.physmem.rdQLenPdf::29 0
+system.physmem.rdQLenPdf::30 0
+system.physmem.rdQLenPdf::31 0
+system.physmem.wrQLenPdf::0 1
+system.physmem.wrQLenPdf::1 1
+system.physmem.wrQLenPdf::2 1
+system.physmem.wrQLenPdf::3 1
+system.physmem.wrQLenPdf::4 1
+system.physmem.wrQLenPdf::5 1
+system.physmem.wrQLenPdf::6 1
+system.physmem.wrQLenPdf::7 1
+system.physmem.wrQLenPdf::8 1
+system.physmem.wrQLenPdf::9 1
+system.physmem.wrQLenPdf::10 1
+system.physmem.wrQLenPdf::11 1
+system.physmem.wrQLenPdf::12 1
+system.physmem.wrQLenPdf::13 1
+system.physmem.wrQLenPdf::14 1
+system.physmem.wrQLenPdf::15 15
+system.physmem.wrQLenPdf::16 16
+system.physmem.wrQLenPdf::17 16
+system.physmem.wrQLenPdf::18 16
+system.physmem.wrQLenPdf::19 16
+system.physmem.wrQLenPdf::20 16
+system.physmem.wrQLenPdf::21 16
+system.physmem.wrQLenPdf::22 16
+system.physmem.wrQLenPdf::23 16
+system.physmem.wrQLenPdf::24 16
+system.physmem.wrQLenPdf::25 16
+system.physmem.wrQLenPdf::26 16
+system.physmem.wrQLenPdf::27 16
+system.physmem.wrQLenPdf::28 16
+system.physmem.wrQLenPdf::29 16
+system.physmem.wrQLenPdf::30 15
+system.physmem.wrQLenPdf::31 15
+system.physmem.wrQLenPdf::32 15
+system.physmem.wrQLenPdf::33 0
+system.physmem.wrQLenPdf::34 0
+system.physmem.wrQLenPdf::35 0
+system.physmem.wrQLenPdf::36 0
+system.physmem.wrQLenPdf::37 0
+system.physmem.wrQLenPdf::38 0
+system.physmem.wrQLenPdf::39 0
+system.physmem.wrQLenPdf::40 0
+system.physmem.wrQLenPdf::41 0
+system.physmem.wrQLenPdf::42 0
+system.physmem.wrQLenPdf::43 0
+system.physmem.wrQLenPdf::44 0
+system.physmem.wrQLenPdf::45 0
+system.physmem.wrQLenPdf::46 0
+system.physmem.wrQLenPdf::47 0
+system.physmem.wrQLenPdf::48 0
+system.physmem.wrQLenPdf::49 0
+system.physmem.wrQLenPdf::50 0
+system.physmem.wrQLenPdf::51 0
+system.physmem.wrQLenPdf::52 0
+system.physmem.wrQLenPdf::53 0
+system.physmem.wrQLenPdf::54 0
+system.physmem.wrQLenPdf::55 0
+system.physmem.wrQLenPdf::56 0
+system.physmem.wrQLenPdf::57 0
+system.physmem.wrQLenPdf::58 0
+system.physmem.wrQLenPdf::59 0
+system.physmem.wrQLenPdf::60 0
+system.physmem.wrQLenPdf::61 0
+system.physmem.wrQLenPdf::62 0
+system.physmem.wrQLenPdf::63 0
+system.physmem.bytesPerActivate::samples 2852
+system.physmem.bytesPerActivate::mean 690.064516
+system.physmem.bytesPerActivate::gmean 482.522488
+system.physmem.bytesPerActivate::stdev 397.377699
+system.physmem.bytesPerActivate::0-127 418 14.66% 14.66%
+system.physmem.bytesPerActivate::128-255 289 10.13% 24.79%
+system.physmem.bytesPerActivate::256-383 128 4.49% 29.28%
+system.physmem.bytesPerActivate::384-511 119 4.17% 33.45%
+system.physmem.bytesPerActivate::512-639 133 4.66% 38.11%
+system.physmem.bytesPerActivate::640-767 123 4.31% 42.43%
+system.physmem.bytesPerActivate::768-895 83 2.91% 45.34%
+system.physmem.bytesPerActivate::896-1023 90 3.16% 48.49%
+system.physmem.bytesPerActivate::1024-1151 1469 51.51% 100.00%
+system.physmem.bytesPerActivate::total 2852
+system.physmem.rdPerTurnAround::samples 15
+system.physmem.rdPerTurnAround::mean 2030.466667
+system.physmem.rdPerTurnAround::gmean 23.801531
+system.physmem.rdPerTurnAround::stdev 7801.447410
+system.physmem.rdPerTurnAround::0-1023 14 93.33% 93.33%
+system.physmem.rdPerTurnAround::29696-30719 1 6.67% 100.00%
+system.physmem.rdPerTurnAround::total 15
+system.physmem.wrPerTurnAround::samples 15
+system.physmem.wrPerTurnAround::mean 17.933333
+system.physmem.wrPerTurnAround::gmean 17.931540
+system.physmem.wrPerTurnAround::stdev 0.258199
+system.physmem.wrPerTurnAround::17 1 6.67% 6.67%
+system.physmem.wrPerTurnAround::18 14 93.33% 100.00%
+system.physmem.wrPerTurnAround::total 15
+system.physmem.totQLat 402617750
+system.physmem.totMemAccLat 974736500
+system.physmem.totBusLat 152565000
+system.physmem.avgQLat 13194.96
+system.physmem.avgBusLat 5000.00
+system.physmem.avgMemAccLat 31944.96
+system.physmem.avgRdBW 29.71
+system.physmem.avgWrBW 0.26
+system.physmem.avgRdBWSys 29.84
+system.physmem.avgWrBWSys 0.29
+system.physmem.peakBW 12800.00
+system.physmem.busUtil 0.23
+system.physmem.busUtilRead 0.23
+system.physmem.busUtilWrite 0.00
+system.physmem.avgRdQLen 1.00
+system.physmem.avgWrQLen 12.51
+system.physmem.readRowHits 27734
+system.physmem.writeRowHits 187
+system.physmem.readRowHitRate 90.89
+system.physmem.writeRowHitRate 62.54
+system.physmem.avgGap 2123809.68
+system.physmem.pageHitRate 90.62
+system.physmem_0.actEnergy 11052720
+system.physmem_0.preEnergy 5855685
+system.physmem_0.readEnergy 113040480
+system.physmem_0.writeEnergy 1357200
+system.physmem_0.refreshEnergy 309163920.000000
+system.physmem_0.actBackEnergy 263324610
+system.physmem_0.preBackEnergy 16569120
+system.physmem_0.actPowerDownEnergy 979073610
+system.physmem_0.prePowerDownEnergy 268447200
+system.physmem_0.selfRefreshEnergy 14975920920
+system.physmem_0.totalEnergy 16943805465
+system.physmem_0.averagePower 257.812234
+system.physmem_0.totalIdleTime 65100637750
+system.physmem_0.memoryStateTime::IDLE 22061500
+system.physmem_0.memoryStateTime::REF 131194000
+system.physmem_0.memoryStateTime::SREF 62254705500
+system.physmem_0.memoryStateTime::PRE_PDN 699065250
+system.physmem_0.memoryStateTime::ACT 467433500
+system.physmem_0.memoryStateTime::ACT_PDN 2147034750
+system.physmem_1.actEnergy 9374820
+system.physmem_1.preEnergy 4967655
+system.physmem_1.readEnergy 104822340
+system.physmem_1.writeEnergy 46980
+system.physmem_1.refreshEnergy 372471840.000000
+system.physmem_1.actBackEnergy 249536310
+system.physmem_1.preBackEnergy 19488480
+system.physmem_1.actPowerDownEnergy 1119740490
+system.physmem_1.prePowerDownEnergy 403290240
+system.physmem_1.selfRefreshEnergy 14835337125
+system.physmem_1.totalEnergy 17119488570
+system.physmem_1.averagePower 260.485370
+system.physmem_1.totalIdleTime 65120969250
+system.physmem_1.memoryStateTime::IDLE 28589000
+system.physmem_1.memoryStateTime::REF 158136000
+system.physmem_1.memoryStateTime::SREF 61616793750
+system.physmem_1.memoryStateTime::PRE_PDN 1050209250
+system.physmem_1.memoryStateTime::ACT 412212500
+system.physmem_1.memoryStateTime::ACT_PDN 2455554000
+system.pwrStateResidencyTicks::UNDEFINED 65721494500
+system.cpu.branchPred.lookups 40406290
+system.cpu.branchPred.condPredicted 40406290
+system.cpu.branchPred.condIncorrect 1431845
+system.cpu.branchPred.BTBLookups 26031629
+system.cpu.branchPred.BTBHits 0
+system.cpu.branchPred.BTBCorrect 0
+system.cpu.branchPred.BTBHitPct 0.000000
+system.cpu.branchPred.usedRAS 6025963
+system.cpu.branchPred.RASInCorrect 91921
+system.cpu.branchPred.indirectLookups 26031629
+system.cpu.branchPred.indirectHits 20992529
+system.cpu.branchPred.indirectMisses 5039100
+system.cpu.branchPredindirectMispredicted 530263
+system.cpu_clk_domain.clock 500
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 65721494500
+system.cpu.apic_clk_domain.clock 8000
+system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 65721494500
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 65721494500
+system.cpu.workload.numSyscalls 444
+system.cpu.pwrStateResidencyTicks::ON 65721494500
+system.cpu.numCycles 131442990
+system.cpu.numWorkItemsStarted 0
+system.cpu.numWorkItemsCompleted 0
+system.cpu.fetch.icacheStallCycles 30464048
+system.cpu.fetch.Insts 219898668
+system.cpu.fetch.Branches 40406290
+system.cpu.fetch.predictedBranches 27018492
+system.cpu.fetch.Cycles 99269738
+system.cpu.fetch.SquashCycles 2979934
+system.cpu.fetch.TlbCycles 465
+system.cpu.fetch.MiscStallCycles 7592
+system.cpu.fetch.PendingTrapStallCycles 128961
+system.cpu.fetch.PendingQuiesceStallCycles 50
+system.cpu.fetch.IcacheWaitRetryStallCycles 174
+system.cpu.fetch.CacheLines 29660171
+system.cpu.fetch.IcacheSquashes 359072
+system.cpu.fetch.ItlbSquashes 17
+system.cpu.fetch.rateDist::samples 131360995
+system.cpu.fetch.rateDist::mean 2.946103
+system.cpu.fetch.rateDist::stdev 3.409063
+system.cpu.fetch.rateDist::underflows 0 0.00% 0.00%
+system.cpu.fetch.rateDist::0 65827184 50.11% 50.11%
+system.cpu.fetch.rateDist::1 4032527 3.07% 53.18%
+system.cpu.fetch.rateDist::2 3600376 2.74% 55.92%
+system.cpu.fetch.rateDist::3 6081929 4.63% 60.55%
+system.cpu.fetch.rateDist::4 7728911 5.88% 66.44%
+system.cpu.fetch.rateDist::5 5535416 4.21% 70.65%
+system.cpu.fetch.rateDist::6 3331669 2.54% 73.19%
+system.cpu.fetch.rateDist::7 2842658 2.16% 75.35%
+system.cpu.fetch.rateDist::8 32380325 24.65% 100.00%
+system.cpu.fetch.rateDist::overflows 0 0.00% 100.00%
+system.cpu.fetch.rateDist::min_value 0
+system.cpu.fetch.rateDist::max_value 8
+system.cpu.fetch.rateDist::total 131360995
+system.cpu.fetch.branchRate 0.307405
+system.cpu.fetch.rate 1.672959
+system.cpu.decode.IdleCycles 15255907
+system.cpu.decode.BlockedCycles 64520496
+system.cpu.decode.RunCycles 40208811
+system.cpu.decode.UnblockCycles 9885814
+system.cpu.decode.SquashCycles 1489967
+system.cpu.decode.DecodedInsts 362265652
+system.cpu.rename.SquashCycles 1489967
+system.cpu.rename.IdleCycles 20796133
+system.cpu.rename.BlockCycles 11129664
+system.cpu.rename.serializeStallCycles 23832
+system.cpu.rename.RunCycles 44255424
+system.cpu.rename.UnblockCycles 53665975
+system.cpu.rename.RenamedInsts 352608748
+system.cpu.rename.ROBFullEvents 23342
+system.cpu.rename.IQFullEvents 777450
+system.cpu.rename.LQFullEvents 46732943
+system.cpu.rename.SQFullEvents 5205031
+system.cpu.rename.RenamedOperands 354925639
+system.cpu.rename.RenameLookups 934456502
+system.cpu.rename.int_rename_lookups 575559102
+system.cpu.rename.fp_rename_lookups 21159
+system.cpu.rename.CommittedMaps 279212747
+system.cpu.rename.UndoneMaps 75712892
+system.cpu.rename.serializingInsts 482
+system.cpu.rename.tempSerializingInsts 483
+system.cpu.rename.skidInsts 64647332
+system.cpu.memDep0.insertedLoads 112313472
+system.cpu.memDep0.insertedStores 38475522
+system.cpu.memDep0.conflictingLoads 51426374
+system.cpu.memDep0.conflictingStores 8868395
+system.cpu.iq.iqInstsAdded 343765046
+system.cpu.iq.iqNonSpecInstsAdded 3883
+system.cpu.iq.iqInstsIssued 317634440
+system.cpu.iq.iqSquashedInstsIssued 163759
+system.cpu.iq.iqSquashedInstsExamined 65576464
+system.cpu.iq.iqSquashedOperandsExamined 101836454
+system.cpu.iq.iqSquashedNonSpecRemoved 3438
+system.cpu.iq.issued_per_cycle::samples 131360995
+system.cpu.iq.issued_per_cycle::mean 2.418027
+system.cpu.iq.issued_per_cycle::stdev 2.167913
+system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00%
+system.cpu.iq.issued_per_cycle::0 35651981 27.14% 27.14%
+system.cpu.iq.issued_per_cycle::1 20061286 15.27% 42.41%
+system.cpu.iq.issued_per_cycle::2 17078933 13.00% 55.41%
+system.cpu.iq.issued_per_cycle::3 17586289 13.39% 68.80%
+system.cpu.iq.issued_per_cycle::4 15273572 11.63% 80.43%
+system.cpu.iq.issued_per_cycle::5 12870930 9.80% 90.23%
+system.cpu.iq.issued_per_cycle::6 6718617 5.11% 95.34%
+system.cpu.iq.issued_per_cycle::7 4059315 3.09% 98.43%
+system.cpu.iq.issued_per_cycle::8 2060072 1.57% 100.00%
+system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00%
+system.cpu.iq.issued_per_cycle::min_value 0
+system.cpu.iq.issued_per_cycle::max_value 8
+system.cpu.iq.issued_per_cycle::total 131360995
+system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00%
+system.cpu.iq.fu_full::IntAlu 367555 8.92% 8.92%
+system.cpu.iq.fu_full::IntMult 0 0.00% 8.92%
+system.cpu.iq.fu_full::IntDiv 0 0.00% 8.92%
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.92%
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.92%
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.92%
+system.cpu.iq.fu_full::FloatMult 0 0.00% 8.92%
+system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 8.92%
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.92%
+system.cpu.iq.fu_full::FloatMisc 0 0.00% 8.92%
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.92%
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.92%
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.92%
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.92%
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.92%
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.92%
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.92%
+system.cpu.iq.fu_full::SimdMult 0 0.00% 8.92%
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.92%
+system.cpu.iq.fu_full::SimdShift 0 0.00% 8.92%
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.92%
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.92%
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.92%
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.92%
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.92%
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.92%
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.92%
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.92%
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.92%
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.92%
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.92%
+system.cpu.iq.fu_full::MemRead 3559749 86.40% 95.32%
+system.cpu.iq.fu_full::MemWrite 191317 4.64% 99.97%
+system.cpu.iq.fu_full::FloatMemRead 13 0.00% 99.97%
+system.cpu.iq.fu_full::FloatMemWrite 1395 0.03% 100.00%
+system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00%
+system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00%
+system.cpu.iq.FU_type_0::No_OpClass 33339 0.01% 0.01%
+system.cpu.iq.FU_type_0::IntAlu 181647745 57.19% 57.20%
+system.cpu.iq.FU_type_0::IntMult 11501 0.00% 57.20%
+system.cpu.iq.FU_type_0::IntDiv 497 0.00% 57.20%
+system.cpu.iq.FU_type_0::FloatAdd 296 0.00% 57.20%
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.20%
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.20%
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.20%
+system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 57.20%
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.20%
+system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 57.20%
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.20%
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.20%
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.20%
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.20%
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.20%
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.20%
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.20%
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.20%
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.20%
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.20%
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.20%
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.20%
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.20%
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.20%
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.20%
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.20%
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.20%
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.20%
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.20%
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.20%
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.20%
+system.cpu.iq.FU_type_0::MemRead 101245285 31.87% 89.08%
+system.cpu.iq.FU_type_0::MemWrite 34690277 10.92% 100.00%
+system.cpu.iq.FU_type_0::FloatMemRead 508 0.00% 100.00%
+system.cpu.iq.FU_type_0::FloatMemWrite 4992 0.00% 100.00%
+system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00%
+system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00%
+system.cpu.iq.FU_type_0::total 317634440
+system.cpu.iq.rate 2.416519
+system.cpu.iq.fu_busy_cnt 4120029
+system.cpu.iq.fu_busy_rate 0.012971
+system.cpu.iq.int_inst_queue_reads 770896978
+system.cpu.iq.int_inst_queue_writes 409373524
+system.cpu.iq.int_inst_queue_wakeup_accesses 313389776
+system.cpu.iq.fp_inst_queue_reads 16685
+system.cpu.iq.fp_inst_queue_writes 31480
+system.cpu.iq.fp_inst_queue_wakeup_accesses 3775
+system.cpu.iq.int_alu_accesses 321713926
+system.cpu.iq.fp_alu_accesses 7204
+system.cpu.iew.lsq.thread0.forwLoads 57497351
+system.cpu.iew.lsq.thread0.invAddrLoads 0
+system.cpu.iew.lsq.thread0.squashedLoads 21534087
+system.cpu.iew.lsq.thread0.ignoredResponses 66072
+system.cpu.iew.lsq.thread0.memOrderViolation 62227
+system.cpu.iew.lsq.thread0.squashedStores 7035770
+system.cpu.iew.lsq.thread0.invAddrSwpfs 0
+system.cpu.iew.lsq.thread0.blockedLoads 0
+system.cpu.iew.lsq.thread0.rescheduledLoads 4204
+system.cpu.iew.lsq.thread0.cacheBlocked 141777
+system.cpu.iew.iewIdleCycles 0
+system.cpu.iew.iewSquashCycles 1489967
+system.cpu.iew.iewBlockCycles 8057522
+system.cpu.iew.iewUnblockCycles 2987683
+system.cpu.iew.iewDispatchedInsts 343768929
+system.cpu.iew.iewDispSquashedInsts 139556
+system.cpu.iew.iewDispLoadInsts 112313472
+system.cpu.iew.iewDispStoreInsts 38475522
+system.cpu.iew.iewDispNonSpecInsts 1604
+system.cpu.iew.iewIQFullEvents 2862
+system.cpu.iew.iewLSQFullEvents 2991864
+system.cpu.iew.memOrderViolationEvents 62227
+system.cpu.iew.predictedTakenIncorrect 520614
+system.cpu.iew.predictedNotTakenIncorrect 1090823
+system.cpu.iew.branchMispredicts 1611437
+system.cpu.iew.iewExecutedInsts 315197484
+system.cpu.iew.iewExecLoadInsts 100490397
+system.cpu.iew.iewExecSquashedInsts 2436956
+system.cpu.iew.exec_swp 0
+system.cpu.iew.exec_nop 0
+system.cpu.iew.exec_refs 134782236
+system.cpu.iew.exec_branches 32089039
+system.cpu.iew.exec_stores 34291839
+system.cpu.iew.exec_rate 2.397979
+system.cpu.iew.wb_sent 314036708
+system.cpu.iew.wb_count 313393551
+system.cpu.iew.wb_producers 237399400
+system.cpu.iew.wb_consumers 342887037
+system.cpu.iew.wb_rate 2.384255
+system.cpu.iew.wb_fanout 0.692355
+system.cpu.commit.commitSquashedInsts 65692241
+system.cpu.commit.commitNonSpecStalls 445
+system.cpu.commit.branchMispredicts 1439325
+system.cpu.commit.committed_per_cycle::samples 121896438
+system.cpu.commit.committed_per_cycle::mean 2.282203
+system.cpu.commit.committed_per_cycle::stdev 3.051706
+system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00%
+system.cpu.commit.committed_per_cycle::0 56939575 46.71% 46.71%
+system.cpu.commit.committed_per_cycle::1 16454719 13.50% 60.21%
+system.cpu.commit.committed_per_cycle::2 11025665 9.05% 69.26%
+system.cpu.commit.committed_per_cycle::3 8756483 7.18% 76.44%
+system.cpu.commit.committed_per_cycle::4 2109912 1.73% 78.17%
+system.cpu.commit.committed_per_cycle::5 1768746 1.45% 79.62%
+system.cpu.commit.committed_per_cycle::6 935268 0.77% 80.39%
+system.cpu.commit.committed_per_cycle::7 726580 0.60% 80.98%
+system.cpu.commit.committed_per_cycle::8 23179490 19.02% 100.00%
+system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00%
+system.cpu.commit.committed_per_cycle::min_value 0
+system.cpu.commit.committed_per_cycle::max_value 8
+system.cpu.commit.committed_per_cycle::total 121896438
+system.cpu.commit.committedInsts 157988547
+system.cpu.commit.committedOps 278192464
+system.cpu.commit.swp_count 0
+system.cpu.commit.refs 122219137
+system.cpu.commit.loads 90779385
+system.cpu.commit.membars 0
+system.cpu.commit.branches 29309705
+system.cpu.commit.fp_insts 40
+system.cpu.commit.int_insts 278169481
+system.cpu.commit.function_calls 4237596
+system.cpu.commit.op_class_0::No_OpClass 16695 0.01% 0.01%
+system.cpu.commit.op_class_0::IntAlu 155945353 56.06% 56.06%
+system.cpu.commit.op_class_0::IntMult 10938 0.00% 56.07%
+system.cpu.commit.op_class_0::IntDiv 329 0.00% 56.07%
+system.cpu.commit.op_class_0::FloatAdd 12 0.00% 56.07%
+system.cpu.commit.op_class_0::FloatCmp 0 0.00% 56.07%
+system.cpu.commit.op_class_0::FloatCvt 0 0.00% 56.07%
+system.cpu.commit.op_class_0::FloatMult 0 0.00% 56.07%
+system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 56.07%
+system.cpu.commit.op_class_0::FloatDiv 0 0.00% 56.07%
+system.cpu.commit.op_class_0::FloatMisc 0 0.00% 56.07%
+system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 56.07%
+system.cpu.commit.op_class_0::SimdAdd 0 0.00% 56.07%
+system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 56.07%
+system.cpu.commit.op_class_0::SimdAlu 0 0.00% 56.07%
+system.cpu.commit.op_class_0::SimdCmp 0 0.00% 56.07%
+system.cpu.commit.op_class_0::SimdCvt 0 0.00% 56.07%
+system.cpu.commit.op_class_0::SimdMisc 0 0.00% 56.07%
+system.cpu.commit.op_class_0::SimdMult 0 0.00% 56.07%
+system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 56.07%
+system.cpu.commit.op_class_0::SimdShift 0 0.00% 56.07%
+system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 56.07%
+system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 56.07%
+system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 56.07%
+system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 56.07%
+system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 56.07%
+system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 56.07%
+system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 56.07%
+system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 56.07%
+system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 56.07%
+system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.07%
+system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.07%
+system.cpu.commit.op_class_0::MemRead 90779371 32.63% 88.70%
+system.cpu.commit.op_class_0::MemWrite 31439738 11.30% 100.00%
+system.cpu.commit.op_class_0::FloatMemRead 14 0.00% 100.00%
+system.cpu.commit.op_class_0::FloatMemWrite 14 0.00% 100.00%
+system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00%
+system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00%
+system.cpu.commit.op_class_0::total 278192464
+system.cpu.commit.bw_lim_events 23179490
+system.cpu.rob.rob_reads 442601653
+system.cpu.rob.rob_writes 697313319
+system.cpu.timesIdled 909
+system.cpu.idleCycles 81995
+system.cpu.committedInsts 157988547
+system.cpu.committedOps 278192464
+system.cpu.cpi 0.831978
+system.cpu.cpi_total 0.831978
+system.cpu.ipc 1.201955
+system.cpu.ipc_total 1.201955
+system.cpu.int_regfile_reads 502529726
+system.cpu.int_regfile_writes 247564665
+system.cpu.fp_regfile_reads 3566
+system.cpu.fp_regfile_writes 731
+system.cpu.cc_regfile_reads 108994485
+system.cpu.cc_regfile_writes 65428204
+system.cpu.misc_regfile_reads 201784346
+system.cpu.misc_regfile_writes 1
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 65721494500
+system.cpu.dcache.tags.replacements 2073509
+system.cpu.dcache.tags.tagsinuse 4067.268199
+system.cpu.dcache.tags.total_refs 71482624
+system.cpu.dcache.tags.sampled_refs 2077605
+system.cpu.dcache.tags.avg_refs 34.406263
+system.cpu.dcache.tags.warmup_cycle 21075173500
+system.cpu.dcache.tags.occ_blocks::cpu.data 4067.268199
+system.cpu.dcache.tags.occ_percent::cpu.data 0.992985
+system.cpu.dcache.tags.occ_percent::total 0.992985
+system.cpu.dcache.tags.occ_task_id_blocks::1024 4096
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 504
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 3445
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 147
+system.cpu.dcache.tags.occ_task_id_percent::1024 1
+system.cpu.dcache.tags.tag_accesses 150633517
+system.cpu.dcache.tags.data_accesses 150633517
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 65721494500
+system.cpu.dcache.ReadReq_hits::cpu.data 40136683
+system.cpu.dcache.ReadReq_hits::total 40136683
+system.cpu.dcache.WriteReq_hits::cpu.data 31345941
+system.cpu.dcache.WriteReq_hits::total 31345941
+system.cpu.dcache.demand_hits::cpu.data 71482624
+system.cpu.dcache.demand_hits::total 71482624
+system.cpu.dcache.overall_hits::cpu.data 71482624
+system.cpu.dcache.overall_hits::total 71482624
+system.cpu.dcache.ReadReq_misses::cpu.data 2701521
+system.cpu.dcache.ReadReq_misses::total 2701521
+system.cpu.dcache.WriteReq_misses::cpu.data 93811
+system.cpu.dcache.WriteReq_misses::total 93811
+system.cpu.dcache.demand_misses::cpu.data 2795332
+system.cpu.dcache.demand_misses::total 2795332
+system.cpu.dcache.overall_misses::cpu.data 2795332
+system.cpu.dcache.overall_misses::total 2795332
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 32454671000
+system.cpu.dcache.ReadReq_miss_latency::total 32454671000
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 3177582491
+system.cpu.dcache.WriteReq_miss_latency::total 3177582491
+system.cpu.dcache.demand_miss_latency::cpu.data 35632253491
+system.cpu.dcache.demand_miss_latency::total 35632253491
+system.cpu.dcache.overall_miss_latency::cpu.data 35632253491
+system.cpu.dcache.overall_miss_latency::total 35632253491
+system.cpu.dcache.ReadReq_accesses::cpu.data 42838204
+system.cpu.dcache.ReadReq_accesses::total 42838204
+system.cpu.dcache.WriteReq_accesses::cpu.data 31439752
+system.cpu.dcache.WriteReq_accesses::total 31439752
+system.cpu.dcache.demand_accesses::cpu.data 74277956
+system.cpu.dcache.demand_accesses::total 74277956
+system.cpu.dcache.overall_accesses::cpu.data 74277956
+system.cpu.dcache.overall_accesses::total 74277956
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.063063
+system.cpu.dcache.ReadReq_miss_rate::total 0.063063
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002984
+system.cpu.dcache.WriteReq_miss_rate::total 0.002984
+system.cpu.dcache.demand_miss_rate::cpu.data 0.037633
+system.cpu.dcache.demand_miss_rate::total 0.037633
+system.cpu.dcache.overall_miss_rate::cpu.data 0.037633
+system.cpu.dcache.overall_miss_rate::total 0.037633
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12013.480924
+system.cpu.dcache.ReadReq_avg_miss_latency::total 12013.480924
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33872.173743
+system.cpu.dcache.WriteReq_avg_miss_latency::total 33872.173743
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 12747.055982
+system.cpu.dcache.demand_avg_miss_latency::total 12747.055982
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 12747.055982
+system.cpu.dcache.overall_avg_miss_latency::total 12747.055982
+system.cpu.dcache.blocked_cycles::no_mshrs 219709
+system.cpu.dcache.blocked_cycles::no_targets 682
+system.cpu.dcache.blocked::no_mshrs 43158
+system.cpu.dcache.blocked::no_targets 6
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.090806
+system.cpu.dcache.avg_blocked_cycles::no_targets 113.666667
+system.cpu.dcache.writebacks::writebacks 2066902
+system.cpu.dcache.writebacks::total 2066902
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 705827
+system.cpu.dcache.ReadReq_mshr_hits::total 705827
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11900
+system.cpu.dcache.WriteReq_mshr_hits::total 11900
+system.cpu.dcache.demand_mshr_hits::cpu.data 717727
+system.cpu.dcache.demand_mshr_hits::total 717727
+system.cpu.dcache.overall_mshr_hits::cpu.data 717727
+system.cpu.dcache.overall_mshr_hits::total 717727
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995694
+system.cpu.dcache.ReadReq_mshr_misses::total 1995694
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81911
+system.cpu.dcache.WriteReq_mshr_misses::total 81911
+system.cpu.dcache.demand_mshr_misses::cpu.data 2077605
+system.cpu.dcache.demand_mshr_misses::total 2077605
+system.cpu.dcache.overall_mshr_misses::cpu.data 2077605
+system.cpu.dcache.overall_mshr_misses::total 2077605
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24272933500
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 24272933500
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3020316491
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3020316491
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27293249991
+system.cpu.dcache.demand_mshr_miss_latency::total 27293249991
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27293249991
+system.cpu.dcache.overall_mshr_miss_latency::total 27293249991
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046587
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046587
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002605
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002605
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027971
+system.cpu.dcache.demand_mshr_miss_rate::total 0.027971
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027971
+system.cpu.dcache.overall_mshr_miss_rate::total 0.027971
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12162.652942
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12162.652942
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36873.148796
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36873.148796
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13136.881164
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 13136.881164
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13136.881164
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 13136.881164
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 65721494500
+system.cpu.icache.tags.replacements 86
+system.cpu.icache.tags.tagsinuse 865.699388
+system.cpu.icache.tags.total_refs 29658716
+system.cpu.icache.tags.sampled_refs 1101
+system.cpu.icache.tags.avg_refs 26937.980018
+system.cpu.icache.tags.warmup_cycle 0
+system.cpu.icache.tags.occ_blocks::cpu.inst 865.699388
+system.cpu.icache.tags.occ_percent::cpu.inst 0.422705
+system.cpu.icache.tags.occ_percent::total 0.422705
+system.cpu.icache.tags.occ_task_id_blocks::1024 1015
+system.cpu.icache.tags.age_task_id_blocks_1024::0 53
+system.cpu.icache.tags.age_task_id_blocks_1024::2 27
+system.cpu.icache.tags.age_task_id_blocks_1024::3 35
+system.cpu.icache.tags.age_task_id_blocks_1024::4 900
+system.cpu.icache.tags.occ_task_id_percent::1024 0.495605
+system.cpu.icache.tags.tag_accesses 59321439
+system.cpu.icache.tags.data_accesses 59321439
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 65721494500
+system.cpu.icache.ReadReq_hits::cpu.inst 29658716
+system.cpu.icache.ReadReq_hits::total 29658716
+system.cpu.icache.demand_hits::cpu.inst 29658716
+system.cpu.icache.demand_hits::total 29658716
+system.cpu.icache.overall_hits::cpu.inst 29658716
+system.cpu.icache.overall_hits::total 29658716
+system.cpu.icache.ReadReq_misses::cpu.inst 1453
+system.cpu.icache.ReadReq_misses::total 1453
+system.cpu.icache.demand_misses::cpu.inst 1453
+system.cpu.icache.demand_misses::total 1453
+system.cpu.icache.overall_misses::cpu.inst 1453
+system.cpu.icache.overall_misses::total 1453
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 154504998
+system.cpu.icache.ReadReq_miss_latency::total 154504998
+system.cpu.icache.demand_miss_latency::cpu.inst 154504998
+system.cpu.icache.demand_miss_latency::total 154504998
+system.cpu.icache.overall_miss_latency::cpu.inst 154504998
+system.cpu.icache.overall_miss_latency::total 154504998
+system.cpu.icache.ReadReq_accesses::cpu.inst 29660169
+system.cpu.icache.ReadReq_accesses::total 29660169
+system.cpu.icache.demand_accesses::cpu.inst 29660169
+system.cpu.icache.demand_accesses::total 29660169
+system.cpu.icache.overall_accesses::cpu.inst 29660169
+system.cpu.icache.overall_accesses::total 29660169
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000049
+system.cpu.icache.ReadReq_miss_rate::total 0.000049
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000049
+system.cpu.icache.demand_miss_rate::total 0.000049
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000049
+system.cpu.icache.overall_miss_rate::total 0.000049
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 106335.167240
+system.cpu.icache.ReadReq_avg_miss_latency::total 106335.167240
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 106335.167240
+system.cpu.icache.demand_avg_miss_latency::total 106335.167240
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 106335.167240
+system.cpu.icache.overall_avg_miss_latency::total 106335.167240
+system.cpu.icache.blocked_cycles::no_mshrs 4008
+system.cpu.icache.blocked_cycles::no_targets 0
+system.cpu.icache.blocked::no_mshrs 17
+system.cpu.icache.blocked::no_targets 0
+system.cpu.icache.avg_blocked_cycles::no_mshrs 235.764706
+system.cpu.icache.avg_blocked_cycles::no_targets nan
+system.cpu.icache.writebacks::writebacks 86
+system.cpu.icache.writebacks::total 86
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 352
+system.cpu.icache.ReadReq_mshr_hits::total 352
+system.cpu.icache.demand_mshr_hits::cpu.inst 352
+system.cpu.icache.demand_mshr_hits::total 352
+system.cpu.icache.overall_mshr_hits::cpu.inst 352
+system.cpu.icache.overall_mshr_hits::total 352
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1101
+system.cpu.icache.ReadReq_mshr_misses::total 1101
+system.cpu.icache.demand_mshr_misses::cpu.inst 1101
+system.cpu.icache.demand_mshr_misses::total 1101
+system.cpu.icache.overall_mshr_misses::cpu.inst 1101
+system.cpu.icache.overall_mshr_misses::total 1101
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 113239998
+system.cpu.icache.ReadReq_mshr_miss_latency::total 113239998
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 113239998
+system.cpu.icache.demand_mshr_miss_latency::total 113239998
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 113239998
+system.cpu.icache.overall_mshr_miss_latency::total 113239998
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037
+system.cpu.icache.demand_mshr_miss_rate::total 0.000037
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037
+system.cpu.icache.overall_mshr_miss_rate::total 0.000037
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 102851.950954
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 102851.950954
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 102851.950954
+system.cpu.icache.demand_avg_mshr_miss_latency::total 102851.950954
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 102851.950954
+system.cpu.icache.overall_avg_mshr_miss_latency::total 102851.950954
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 65721494500
+system.cpu.l2cache.tags.replacements 680
+system.cpu.l2cache.tags.tagsinuse 21650.115816
+system.cpu.l2cache.tags.total_refs 4121613
+system.cpu.l2cache.tags.sampled_refs 30665
+system.cpu.l2cache.tags.avg_refs 134.407729
+system.cpu.l2cache.tags.warmup_cycle 0
+system.cpu.l2cache.tags.occ_blocks::writebacks 3.138386
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 704.921194
+system.cpu.l2cache.tags.occ_blocks::cpu.data 20942.056236
+system.cpu.l2cache.tags.occ_percent::writebacks 0.000096
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.021512
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.639101
+system.cpu.l2cache.tags.occ_percent::total 0.660709
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 29985
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 62
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 57
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 172
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 54
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29640
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.915070
+system.cpu.l2cache.tags.tag_accesses 33248889
+system.cpu.l2cache.tags.data_accesses 33248889
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 65721494500
+system.cpu.l2cache.WritebackDirty_hits::writebacks 2066902
+system.cpu.l2cache.WritebackDirty_hits::total 2066902
+system.cpu.l2cache.WritebackClean_hits::writebacks 86
+system.cpu.l2cache.WritebackClean_hits::total 86
+system.cpu.l2cache.ReadExReq_hits::cpu.data 52946
+system.cpu.l2cache.ReadExReq_hits::total 52946
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 26
+system.cpu.l2cache.ReadCleanReq_hits::total 26
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1995088
+system.cpu.l2cache.ReadSharedReq_hits::total 1995088
+system.cpu.l2cache.demand_hits::cpu.inst 26
+system.cpu.l2cache.demand_hits::cpu.data 2048034
+system.cpu.l2cache.demand_hits::total 2048060
+system.cpu.l2cache.overall_hits::cpu.inst 26
+system.cpu.l2cache.overall_hits::cpu.data 2048034
+system.cpu.l2cache.overall_hits::total 2048060
+system.cpu.l2cache.ReadExReq_misses::cpu.data 28996
+system.cpu.l2cache.ReadExReq_misses::total 28996
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1075
+system.cpu.l2cache.ReadCleanReq_misses::total 1075
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data 575
+system.cpu.l2cache.ReadSharedReq_misses::total 575
+system.cpu.l2cache.demand_misses::cpu.inst 1075
+system.cpu.l2cache.demand_misses::cpu.data 29571
+system.cpu.l2cache.demand_misses::total 30646
+system.cpu.l2cache.overall_misses::cpu.inst 1075
+system.cpu.l2cache.overall_misses::cpu.data 29571
+system.cpu.l2cache.overall_misses::total 30646
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2341147500
+system.cpu.l2cache.ReadExReq_miss_latency::total 2341147500
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 111300000
+system.cpu.l2cache.ReadCleanReq_miss_latency::total 111300000
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 88414500
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 88414500
+system.cpu.l2cache.demand_miss_latency::cpu.inst 111300000
+system.cpu.l2cache.demand_miss_latency::cpu.data 2429562000
+system.cpu.l2cache.demand_miss_latency::total 2540862000
+system.cpu.l2cache.overall_miss_latency::cpu.inst 111300000
+system.cpu.l2cache.overall_miss_latency::cpu.data 2429562000
+system.cpu.l2cache.overall_miss_latency::total 2540862000
+system.cpu.l2cache.WritebackDirty_accesses::writebacks 2066902
+system.cpu.l2cache.WritebackDirty_accesses::total 2066902
+system.cpu.l2cache.WritebackClean_accesses::writebacks 86
+system.cpu.l2cache.WritebackClean_accesses::total 86
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 81942
+system.cpu.l2cache.ReadExReq_accesses::total 81942
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1101
+system.cpu.l2cache.ReadCleanReq_accesses::total 1101
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1995663
+system.cpu.l2cache.ReadSharedReq_accesses::total 1995663
+system.cpu.l2cache.demand_accesses::cpu.inst 1101
+system.cpu.l2cache.demand_accesses::cpu.data 2077605
+system.cpu.l2cache.demand_accesses::total 2078706
+system.cpu.l2cache.overall_accesses::cpu.inst 1101
+system.cpu.l2cache.overall_accesses::cpu.data 2077605
+system.cpu.l2cache.overall_accesses::total 2078706
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353860
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.353860
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.976385
+system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.976385
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000288
+system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000288
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.976385
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.014233
+system.cpu.l2cache.demand_miss_rate::total 0.014743
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.976385
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.014233
+system.cpu.l2cache.overall_miss_rate::total 0.014743
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80740.360739
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80740.360739
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 103534.883721
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 103534.883721
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 153764.347826
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 153764.347826
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 103534.883721
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82160.292178
+system.cpu.l2cache.demand_avg_miss_latency::total 82910.069830
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 103534.883721
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82160.292178
+system.cpu.l2cache.overall_avg_miss_latency::total 82910.069830
+system.cpu.l2cache.blocked_cycles::no_mshrs 0
+system.cpu.l2cache.blocked_cycles::no_targets 0
+system.cpu.l2cache.blocked::no_mshrs 0
+system.cpu.l2cache.blocked::no_targets 0
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan
+system.cpu.l2cache.writebacks::writebacks 299
+system.cpu.l2cache.writebacks::total 299
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28996
+system.cpu.l2cache.ReadExReq_mshr_misses::total 28996
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1075
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1075
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 575
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 575
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 1075
+system.cpu.l2cache.demand_mshr_misses::cpu.data 29571
+system.cpu.l2cache.demand_mshr_misses::total 30646
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 1075
+system.cpu.l2cache.overall_mshr_misses::cpu.data 29571
+system.cpu.l2cache.overall_mshr_misses::total 30646
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2051187500
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2051187500
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 100550000
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 100550000
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 82664500
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 82664500
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 100550000
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2133852000
+system.cpu.l2cache.demand_mshr_miss_latency::total 2234402000
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 100550000
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2133852000
+system.cpu.l2cache.overall_mshr_miss_latency::total 2234402000
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353860
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353860
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.976385
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.976385
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000288
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000288
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.976385
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014233
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.014743
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.976385
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014233
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.014743
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70740.360739
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70740.360739
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93534.883721
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93534.883721
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 143764.347826
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 143764.347826
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93534.883721
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72160.292178
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72910.069830
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93534.883721
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72160.292178
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72910.069830
+system.cpu.toL2Bus.snoop_filter.tot_requests 4152301
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073596
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23
+system.cpu.toL2Bus.snoop_filter.tot_snoops 330
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 330
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 65721494500
+system.cpu.toL2Bus.trans_dist::ReadResp 1996764
+system.cpu.toL2Bus.trans_dist::WritebackDirty 2067201
+system.cpu.toL2Bus.trans_dist::WritebackClean 86
+system.cpu.toL2Bus.trans_dist::CleanEvict 6988
+system.cpu.toL2Bus.trans_dist::ReadExReq 81942
+system.cpu.toL2Bus.trans_dist::ReadExResp 81942
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 1101
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995663
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2288
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228719
+system.cpu.toL2Bus.pkt_count::total 6231007
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 75968
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265248448
+system.cpu.toL2Bus.pkt_size::total 265324416
+system.cpu.toL2Bus.snoops 680
+system.cpu.toL2Bus.snoopTraffic 19136
+system.cpu.toL2Bus.snoop_fanout::samples 2079386
+system.cpu.toL2Bus.snoop_fanout::mean 0.000170
+system.cpu.toL2Bus.snoop_fanout::stdev 0.013047
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu.toL2Bus.snoop_fanout::0 2079032 99.98% 99.98%
+system.cpu.toL2Bus.snoop_fanout::1 354 0.02% 100.00%
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::min_value 0
+system.cpu.toL2Bus.snoop_fanout::max_value 1
+system.cpu.toL2Bus.snoop_fanout::total 2079386
+system.cpu.toL2Bus.reqLayer0.occupancy 4143138500
+system.cpu.toL2Bus.reqLayer0.utilization 6.3
+system.cpu.toL2Bus.respLayer0.occupancy 1652498
+system.cpu.toL2Bus.respLayer0.utilization 0.0
+system.cpu.toL2Bus.respLayer1.occupancy 3116407500
+system.cpu.toL2Bus.respLayer1.utilization 4.7
+system.membus.snoop_filter.tot_requests 30996
+system.membus.snoop_filter.hit_single_requests 350
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 65721494500
+system.membus.trans_dist::ReadResp 1650
+system.membus.trans_dist::WritebackDirty 299
+system.membus.trans_dist::CleanEvict 51
+system.membus.trans_dist::ReadExReq 28996
+system.membus.trans_dist::ReadExResp 28996
+system.membus.trans_dist::ReadSharedReq 1650
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61642
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61642
+system.membus.pkt_count::total 61642
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1980480
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1980480
+system.membus.pkt_size::total 1980480
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 30646
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 30646 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 30646
+system.membus.reqLayer0.occupancy 43591500
+system.membus.reqLayer0.utilization 0.1
+system.membus.respLayer1.occupancy 161486250
+system.membus.respLayer1.utilization 0.2
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
index 420cd8ed8..03e352749 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
@@ -20,6 +20,7 @@ exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
+kvm_vm=Null
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
@@ -85,6 +86,7 @@ progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -100,14 +102,14 @@ eventq_index=0
[system.cpu.dcache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@@ -121,6 +123,7 @@ response_latency=2
sequential_access=false
size=262144
system=system
+tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@@ -133,15 +136,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
+tag_latency=2
[system.cpu.dtb]
type=X86TLB
@@ -166,14 +170,14 @@ port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@@ -187,6 +191,7 @@ response_latency=2
sequential_access=false
size=131072
system=system
+tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@@ -199,15 +204,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
+tag_latency=2
[system.cpu.interrupts]
type=X86LocalApic
@@ -253,14 +259,14 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@@ -274,6 +280,7 @@ response_latency=20
sequential_access=false
size=2097152
system=system
+tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@@ -286,15 +293,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=20
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
+tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -330,7 +338,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=mcf mcf.in
cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
drivers=
@@ -339,14 +347,15 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/mcf
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/mcf
gid=100
-input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=55300000000
system=system
uid=100
@@ -370,6 +379,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -381,7 +391,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -389,6 +399,13 @@ width=16
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -397,6 +414,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
+kvm_map=true
latency=30000
latency_var=0
null=false
@@ -404,7 +422,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
-range=0:268435455
+range=0:268435455:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
index aadc3d011..c0b55d123 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
@@ -1,2 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
index 657298ab6..712b4d61b 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
@@ -3,13 +3,12 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 21 2016 14:35:23
-gem5 started Jul 21 2016 14:36:18
-gem5 executing on e108600-lin, pid 18549
-command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/x86/linux/simple-timing
+gem5 compiled Apr 3 2017 19:05:53
+gem5 started Apr 3 2017 19:08:56
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 90898
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/10.mcf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I
by Andreas Loebel
@@ -26,4 +25,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 366199170500 because target called exit()
+Exiting @ tick 366229314500 because exiting with last active thread context
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
index 957a0aa1f..275d179a2 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
@@ -1,541 +1,541 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.366229 # Number of seconds simulated
-sim_ticks 366229314500 # Number of ticks simulated
-final_tick 366229314500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1002365 # Simulator instruction rate (inst/s)
-host_op_rate 1765004 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2323557450 # Simulator tick rate (ticks/s)
-host_mem_usage 412036 # Number of bytes of host memory used
-host_seconds 157.62 # Real time elapsed on the host
-sim_insts 157988548 # Number of instructions simulated
-sim_ops 278192465 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1871552 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1922944 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 51392 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 6656 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6656 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 803 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 29243 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 30046 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 104 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 104 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 140327 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 5110328 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 5250656 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 140327 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 140327 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 18174 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 18174 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 18174 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 140327 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 5110328 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 5268830 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states
-system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states
-system.cpu.workload.numSyscalls 444 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 366229314500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 732458629 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 157988548 # Number of instructions committed
-system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
-system.cpu.num_func_calls 8475189 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls
-system.cpu.num_int_insts 278169482 # number of integer instructions
-system.cpu.num_fp_insts 40 # number of float instructions
-system.cpu.num_int_register_reads 635379407 # number of times the integer registers were read
-system.cpu.num_int_register_writes 217447860 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written
-system.cpu.num_mem_refs 122219137 # number of memory refs
-system.cpu.num_load_insts 90779385 # Number of load instructions
-system.cpu.num_store_insts 31439752 # Number of store instructions
-system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 732458628.998000 # Number of busy cycles
-system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 29309705 # Number of branches fetched
-system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction
-system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction
-system.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::MemRead 90779371 32.63% 88.70% # Class of executed instruction
-system.cpu.op_class::MemWrite 31439738 11.30% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 14 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 14 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 278192465 # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 2062733 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4076.272883 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 126128435500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4076.272883 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.995184 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.995184 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 1776 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 2198 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 120152370 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 120152370 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 120152370 # number of overall hits
-system.cpu.dcache.overall_hits::total 120152370 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses
-system.cpu.dcache.overall_misses::total 2066829 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 25500310500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 25500310500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 2830649000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 2830649000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 28330959500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 28330959500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 28330959500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 28330959500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 122219199 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 122219199 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 122219199 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 122219199 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13005.584938 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13005.584938 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26676.804041 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 26676.804041 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 13707.452092 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 13707.452092 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 13707.452092 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 13707.452092 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks 2062482 # number of writebacks
-system.cpu.dcache.writebacks::total 2062482 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23539590500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 23539590500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2724540000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 2724540000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26264130500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 26264130500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26264130500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 26264130500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12005.584938 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12005.584938 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25676.804041 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25676.804041 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12707.452092 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 12707.452092 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12707.452092 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 12707.452092 # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements 24 # number of replacements
-system.cpu.icache.tags.tagsinuse 665.626582 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 269424.945545 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 665.626582 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.325013 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.325013 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 715 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.382812 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 435393136 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 435393136 # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst 217695356 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 217695356 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 217695356 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 217695356 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 217695356 # number of overall hits
-system.cpu.icache.overall_hits::total 217695356 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses
-system.cpu.icache.overall_misses::total 808 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 50660000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 50660000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 50660000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 50660000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 50660000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 50660000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 217696164 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 217696164 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 217696164 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 217696164 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 217696164 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 217696164 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62698.019802 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 62698.019802 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 62698.019802 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 62698.019802 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 62698.019802 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 62698.019802 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks 24 # number of writebacks
-system.cpu.icache.writebacks::total 24 # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49852000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 49852000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49852000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 49852000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49852000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 49852000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61698.019802 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61698.019802 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61698.019802 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 61698.019802 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61698.019802 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 61698.019802 # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements 315 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 21080.806353 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 4100347 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 30047 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 136.464439 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 0.624695 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 556.051540 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 20524.130118 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.000019 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.016969 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.626347 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.643335 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 29732 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 45 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29568 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.907349 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 33073199 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 33073199 # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks 2062482 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total 2062482 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks 24 # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total 24 # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 77085 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 77085 # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total 5 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1960501 # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total 1960501 # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 2037586 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2037591 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 2037586 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2037591 # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data 29024 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 29024 # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 803 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total 803 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data 219 # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total 219 # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 803 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 29243 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 30046 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 803 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 29243 # number of overall misses
-system.cpu.l2cache.overall_misses::total 30046 # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1755983000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 1755983000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 48585000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total 48585000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13249500 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 13249500 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 48585000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 1769232500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 1817817500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 48585000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 1769232500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 1817817500 # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks 2062482 # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total 2062482 # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks 24 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total 24 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 808 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total 808 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1960720 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total 1960720 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 2066829 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 2067637 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 808 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273530 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.273530 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993812 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993812 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000112 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000112 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993812 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.014149 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.014532 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.014149 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.014532 # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60501.068082 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60501.068082 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60504.358655 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60504.358655 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60504.358655 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.060083 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 60501.148239 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60504.358655 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.060083 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 60501.148239 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks 104 # number of writebacks
-system.cpu.l2cache.writebacks::total 104 # number of writebacks
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 29024 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 803 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 803 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 219 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 219 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 29243 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 30046 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 29243 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 30046 # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1465743000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1465743000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 40555000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 40555000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11059500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11059500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40555000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1476802500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 1517357500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40555000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1476802500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 1517357500 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993812 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000112 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014149 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.014532 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014149 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.014532 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50501.068082 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50501.068082 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50504.358655 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50504.358655 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50504.358655 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.060083 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.148239 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50504.358655 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.060083 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.148239 # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests 4130394 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 2062757 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 197 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 197 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 2062586 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 24 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 462 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 808 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 1960720 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196391 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 6198031 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53248 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264275904 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 264329152 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 315 # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic 6656 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 2067952 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.000095 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.009760 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 2067755 99.99% 99.99% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 197 0.01% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 2067952 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 4127703000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
-system.membus.snoop_filter.tot_requests 30164 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 118 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp 1022 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 104 # Transaction distribution
-system.membus.trans_dist::CleanEvict 14 # Transaction distribution
-system.membus.trans_dist::ReadExReq 29024 # Transaction distribution
-system.membus.trans_dist::ReadExResp 29024 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 1022 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60210 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60210 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 60210 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929600 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929600 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 1929600 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 30046 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 30046 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 30046 # Request fanout histogram
-system.membus.reqLayer0.occupancy 30614500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 150230000 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
+sim_seconds 0.366229
+sim_ticks 366229314500
+final_tick 366229314500
+sim_freq 1000000000000
+host_inst_rate 440271
+host_op_rate 775247
+host_tick_rate 1020581695
+host_mem_usage 422392
+host_seconds 358.84
+sim_insts 157988548
+sim_ops 278192465
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 366229314500
+system.physmem.bytes_read::cpu.inst 51392
+system.physmem.bytes_read::cpu.data 1871552
+system.physmem.bytes_read::total 1922944
+system.physmem.bytes_inst_read::cpu.inst 51392
+system.physmem.bytes_inst_read::total 51392
+system.physmem.bytes_written::writebacks 6656
+system.physmem.bytes_written::total 6656
+system.physmem.num_reads::cpu.inst 803
+system.physmem.num_reads::cpu.data 29243
+system.physmem.num_reads::total 30046
+system.physmem.num_writes::writebacks 104
+system.physmem.num_writes::total 104
+system.physmem.bw_read::cpu.inst 140327
+system.physmem.bw_read::cpu.data 5110328
+system.physmem.bw_read::total 5250656
+system.physmem.bw_inst_read::cpu.inst 140327
+system.physmem.bw_inst_read::total 140327
+system.physmem.bw_write::writebacks 18174
+system.physmem.bw_write::total 18174
+system.physmem.bw_total::writebacks 18174
+system.physmem.bw_total::cpu.inst 140327
+system.physmem.bw_total::cpu.data 5110328
+system.physmem.bw_total::total 5268830
+system.pwrStateResidencyTicks::UNDEFINED 366229314500
+system.cpu_clk_domain.clock 500
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366229314500
+system.cpu.apic_clk_domain.clock 8000
+system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 366229314500
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366229314500
+system.cpu.workload.numSyscalls 444
+system.cpu.pwrStateResidencyTicks::ON 366229314500
+system.cpu.numCycles 732458629
+system.cpu.numWorkItemsStarted 0
+system.cpu.numWorkItemsCompleted 0
+system.cpu.committedInsts 157988548
+system.cpu.committedOps 278192465
+system.cpu.num_int_alu_accesses 278169482
+system.cpu.num_fp_alu_accesses 40
+system.cpu.num_func_calls 8475189
+system.cpu.num_conditional_control_insts 18628007
+system.cpu.num_int_insts 278169482
+system.cpu.num_fp_insts 40
+system.cpu.num_int_register_reads 635379407
+system.cpu.num_int_register_writes 217447860
+system.cpu.num_fp_register_reads 40
+system.cpu.num_fp_register_writes 26
+system.cpu.num_cc_register_reads 104140596
+system.cpu.num_cc_register_writes 61764861
+system.cpu.num_mem_refs 122219137
+system.cpu.num_load_insts 90779385
+system.cpu.num_store_insts 31439752
+system.cpu.num_idle_cycles 0
+system.cpu.num_busy_cycles 732458629
+system.cpu.not_idle_fraction 1
+system.cpu.idle_fraction 0
+system.cpu.Branches 29309705
+system.cpu.op_class::No_OpClass 16695 0.01% 0.01%
+system.cpu.op_class::IntAlu 155945354 56.06% 56.06%
+system.cpu.op_class::IntMult 10938 0.00% 56.07%
+system.cpu.op_class::IntDiv 329 0.00% 56.07%
+system.cpu.op_class::FloatAdd 12 0.00% 56.07%
+system.cpu.op_class::FloatCmp 0 0.00% 56.07%
+system.cpu.op_class::FloatCvt 0 0.00% 56.07%
+system.cpu.op_class::FloatMult 0 0.00% 56.07%
+system.cpu.op_class::FloatMultAcc 0 0.00% 56.07%
+system.cpu.op_class::FloatDiv 0 0.00% 56.07%
+system.cpu.op_class::FloatMisc 0 0.00% 56.07%
+system.cpu.op_class::FloatSqrt 0 0.00% 56.07%
+system.cpu.op_class::SimdAdd 0 0.00% 56.07%
+system.cpu.op_class::SimdAddAcc 0 0.00% 56.07%
+system.cpu.op_class::SimdAlu 0 0.00% 56.07%
+system.cpu.op_class::SimdCmp 0 0.00% 56.07%
+system.cpu.op_class::SimdCvt 0 0.00% 56.07%
+system.cpu.op_class::SimdMisc 0 0.00% 56.07%
+system.cpu.op_class::SimdMult 0 0.00% 56.07%
+system.cpu.op_class::SimdMultAcc 0 0.00% 56.07%
+system.cpu.op_class::SimdShift 0 0.00% 56.07%
+system.cpu.op_class::SimdShiftAcc 0 0.00% 56.07%
+system.cpu.op_class::SimdSqrt 0 0.00% 56.07%
+system.cpu.op_class::SimdFloatAdd 0 0.00% 56.07%
+system.cpu.op_class::SimdFloatAlu 0 0.00% 56.07%
+system.cpu.op_class::SimdFloatCmp 0 0.00% 56.07%
+system.cpu.op_class::SimdFloatCvt 0 0.00% 56.07%
+system.cpu.op_class::SimdFloatDiv 0 0.00% 56.07%
+system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07%
+system.cpu.op_class::SimdFloatMult 0 0.00% 56.07%
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07%
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07%
+system.cpu.op_class::MemRead 90779371 32.63% 88.70%
+system.cpu.op_class::MemWrite 31439738 11.30% 100.00%
+system.cpu.op_class::FloatMemRead 14 0.00% 100.00%
+system.cpu.op_class::FloatMemWrite 14 0.00% 100.00%
+system.cpu.op_class::IprAccess 0 0.00% 100.00%
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
+system.cpu.op_class::total 278192465
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366229314500
+system.cpu.dcache.tags.replacements 2062733
+system.cpu.dcache.tags.tagsinuse 4076.272883
+system.cpu.dcache.tags.total_refs 120152370
+system.cpu.dcache.tags.sampled_refs 2066829
+system.cpu.dcache.tags.avg_refs 58.133677
+system.cpu.dcache.tags.warmup_cycle 126128435500
+system.cpu.dcache.tags.occ_blocks::cpu.data 4076.272883
+system.cpu.dcache.tags.occ_percent::cpu.data 0.995184
+system.cpu.dcache.tags.occ_percent::total 0.995184
+system.cpu.dcache.tags.occ_task_id_blocks::1024 4096
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 116
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 1776
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 2198
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 6
+system.cpu.dcache.tags.occ_task_id_percent::1024 1
+system.cpu.dcache.tags.tag_accesses 246505227
+system.cpu.dcache.tags.data_accesses 246505227
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366229314500
+system.cpu.dcache.ReadReq_hits::cpu.data 88818727
+system.cpu.dcache.ReadReq_hits::total 88818727
+system.cpu.dcache.WriteReq_hits::cpu.data 31333643
+system.cpu.dcache.WriteReq_hits::total 31333643
+system.cpu.dcache.demand_hits::cpu.data 120152370
+system.cpu.dcache.demand_hits::total 120152370
+system.cpu.dcache.overall_hits::cpu.data 120152370
+system.cpu.dcache.overall_hits::total 120152370
+system.cpu.dcache.ReadReq_misses::cpu.data 1960720
+system.cpu.dcache.ReadReq_misses::total 1960720
+system.cpu.dcache.WriteReq_misses::cpu.data 106109
+system.cpu.dcache.WriteReq_misses::total 106109
+system.cpu.dcache.demand_misses::cpu.data 2066829
+system.cpu.dcache.demand_misses::total 2066829
+system.cpu.dcache.overall_misses::cpu.data 2066829
+system.cpu.dcache.overall_misses::total 2066829
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 25500310500
+system.cpu.dcache.ReadReq_miss_latency::total 25500310500
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 2830649000
+system.cpu.dcache.WriteReq_miss_latency::total 2830649000
+system.cpu.dcache.demand_miss_latency::cpu.data 28330959500
+system.cpu.dcache.demand_miss_latency::total 28330959500
+system.cpu.dcache.overall_miss_latency::cpu.data 28330959500
+system.cpu.dcache.overall_miss_latency::total 28330959500
+system.cpu.dcache.ReadReq_accesses::cpu.data 90779447
+system.cpu.dcache.ReadReq_accesses::total 90779447
+system.cpu.dcache.WriteReq_accesses::cpu.data 31439752
+system.cpu.dcache.WriteReq_accesses::total 31439752
+system.cpu.dcache.demand_accesses::cpu.data 122219199
+system.cpu.dcache.demand_accesses::total 122219199
+system.cpu.dcache.overall_accesses::cpu.data 122219199
+system.cpu.dcache.overall_accesses::total 122219199
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599
+system.cpu.dcache.ReadReq_miss_rate::total 0.021599
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375
+system.cpu.dcache.WriteReq_miss_rate::total 0.003375
+system.cpu.dcache.demand_miss_rate::cpu.data 0.016911
+system.cpu.dcache.demand_miss_rate::total 0.016911
+system.cpu.dcache.overall_miss_rate::cpu.data 0.016911
+system.cpu.dcache.overall_miss_rate::total 0.016911
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13005.584938
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13005.584938
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26676.804041
+system.cpu.dcache.WriteReq_avg_miss_latency::total 26676.804041
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 13707.452092
+system.cpu.dcache.demand_avg_miss_latency::total 13707.452092
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 13707.452092
+system.cpu.dcache.overall_avg_miss_latency::total 13707.452092
+system.cpu.dcache.blocked_cycles::no_mshrs 0
+system.cpu.dcache.blocked_cycles::no_targets 0
+system.cpu.dcache.blocked::no_mshrs 0
+system.cpu.dcache.blocked::no_targets 0
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
+system.cpu.dcache.avg_blocked_cycles::no_targets nan
+system.cpu.dcache.writebacks::writebacks 2062482
+system.cpu.dcache.writebacks::total 2062482
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720
+system.cpu.dcache.ReadReq_mshr_misses::total 1960720
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109
+system.cpu.dcache.WriteReq_mshr_misses::total 106109
+system.cpu.dcache.demand_mshr_misses::cpu.data 2066829
+system.cpu.dcache.demand_mshr_misses::total 2066829
+system.cpu.dcache.overall_mshr_misses::cpu.data 2066829
+system.cpu.dcache.overall_mshr_misses::total 2066829
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23539590500
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 23539590500
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2724540000
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 2724540000
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26264130500
+system.cpu.dcache.demand_mshr_miss_latency::total 26264130500
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26264130500
+system.cpu.dcache.overall_mshr_miss_latency::total 26264130500
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911
+system.cpu.dcache.demand_mshr_miss_rate::total 0.016911
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911
+system.cpu.dcache.overall_mshr_miss_rate::total 0.016911
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12005.584938
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12005.584938
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25676.804041
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25676.804041
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12707.452092
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 12707.452092
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12707.452092
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 12707.452092
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366229314500
+system.cpu.icache.tags.replacements 24
+system.cpu.icache.tags.tagsinuse 665.626582
+system.cpu.icache.tags.total_refs 217695357
+system.cpu.icache.tags.sampled_refs 808
+system.cpu.icache.tags.avg_refs 269424.946782
+system.cpu.icache.tags.warmup_cycle 0
+system.cpu.icache.tags.occ_blocks::cpu.inst 665.626582
+system.cpu.icache.tags.occ_percent::cpu.inst 0.325013
+system.cpu.icache.tags.occ_percent::total 0.325013
+system.cpu.icache.tags.occ_task_id_blocks::1024 784
+system.cpu.icache.tags.age_task_id_blocks_1024::0 46
+system.cpu.icache.tags.age_task_id_blocks_1024::3 23
+system.cpu.icache.tags.age_task_id_blocks_1024::4 715
+system.cpu.icache.tags.occ_task_id_percent::1024 0.382812
+system.cpu.icache.tags.tag_accesses 435393138
+system.cpu.icache.tags.data_accesses 435393138
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366229314500
+system.cpu.icache.ReadReq_hits::cpu.inst 217695357
+system.cpu.icache.ReadReq_hits::total 217695357
+system.cpu.icache.demand_hits::cpu.inst 217695357
+system.cpu.icache.demand_hits::total 217695357
+system.cpu.icache.overall_hits::cpu.inst 217695357
+system.cpu.icache.overall_hits::total 217695357
+system.cpu.icache.ReadReq_misses::cpu.inst 808
+system.cpu.icache.ReadReq_misses::total 808
+system.cpu.icache.demand_misses::cpu.inst 808
+system.cpu.icache.demand_misses::total 808
+system.cpu.icache.overall_misses::cpu.inst 808
+system.cpu.icache.overall_misses::total 808
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 50660000
+system.cpu.icache.ReadReq_miss_latency::total 50660000
+system.cpu.icache.demand_miss_latency::cpu.inst 50660000
+system.cpu.icache.demand_miss_latency::total 50660000
+system.cpu.icache.overall_miss_latency::cpu.inst 50660000
+system.cpu.icache.overall_miss_latency::total 50660000
+system.cpu.icache.ReadReq_accesses::cpu.inst 217696165
+system.cpu.icache.ReadReq_accesses::total 217696165
+system.cpu.icache.demand_accesses::cpu.inst 217696165
+system.cpu.icache.demand_accesses::total 217696165
+system.cpu.icache.overall_accesses::cpu.inst 217696165
+system.cpu.icache.overall_accesses::total 217696165
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004
+system.cpu.icache.ReadReq_miss_rate::total 0.000004
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000004
+system.cpu.icache.demand_miss_rate::total 0.000004
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000004
+system.cpu.icache.overall_miss_rate::total 0.000004
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62698.019802
+system.cpu.icache.ReadReq_avg_miss_latency::total 62698.019802
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 62698.019802
+system.cpu.icache.demand_avg_miss_latency::total 62698.019802
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 62698.019802
+system.cpu.icache.overall_avg_miss_latency::total 62698.019802
+system.cpu.icache.blocked_cycles::no_mshrs 0
+system.cpu.icache.blocked_cycles::no_targets 0
+system.cpu.icache.blocked::no_mshrs 0
+system.cpu.icache.blocked::no_targets 0
+system.cpu.icache.avg_blocked_cycles::no_mshrs nan
+system.cpu.icache.avg_blocked_cycles::no_targets nan
+system.cpu.icache.writebacks::writebacks 24
+system.cpu.icache.writebacks::total 24
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808
+system.cpu.icache.ReadReq_mshr_misses::total 808
+system.cpu.icache.demand_mshr_misses::cpu.inst 808
+system.cpu.icache.demand_mshr_misses::total 808
+system.cpu.icache.overall_mshr_misses::cpu.inst 808
+system.cpu.icache.overall_mshr_misses::total 808
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49852000
+system.cpu.icache.ReadReq_mshr_miss_latency::total 49852000
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49852000
+system.cpu.icache.demand_mshr_miss_latency::total 49852000
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49852000
+system.cpu.icache.overall_mshr_miss_latency::total 49852000
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004
+system.cpu.icache.demand_mshr_miss_rate::total 0.000004
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004
+system.cpu.icache.overall_mshr_miss_rate::total 0.000004
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61698.019802
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61698.019802
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61698.019802
+system.cpu.icache.demand_avg_mshr_miss_latency::total 61698.019802
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61698.019802
+system.cpu.icache.overall_avg_mshr_miss_latency::total 61698.019802
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366229314500
+system.cpu.l2cache.tags.replacements 315
+system.cpu.l2cache.tags.tagsinuse 21080.806353
+system.cpu.l2cache.tags.total_refs 4100347
+system.cpu.l2cache.tags.sampled_refs 30047
+system.cpu.l2cache.tags.avg_refs 136.464439
+system.cpu.l2cache.tags.warmup_cycle 0
+system.cpu.l2cache.tags.occ_blocks::writebacks 0.624695
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 556.051540
+system.cpu.l2cache.tags.occ_blocks::cpu.data 20524.130118
+system.cpu.l2cache.tags.occ_percent::writebacks 0.000019
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.016969
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.626347
+system.cpu.l2cache.tags.occ_percent::total 0.643335
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 29732
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 9
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 60
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 45
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29568
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.907349
+system.cpu.l2cache.tags.tag_accesses 33073199
+system.cpu.l2cache.tags.data_accesses 33073199
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366229314500
+system.cpu.l2cache.WritebackDirty_hits::writebacks 2062482
+system.cpu.l2cache.WritebackDirty_hits::total 2062482
+system.cpu.l2cache.WritebackClean_hits::writebacks 24
+system.cpu.l2cache.WritebackClean_hits::total 24
+system.cpu.l2cache.ReadExReq_hits::cpu.data 77085
+system.cpu.l2cache.ReadExReq_hits::total 77085
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5
+system.cpu.l2cache.ReadCleanReq_hits::total 5
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1960501
+system.cpu.l2cache.ReadSharedReq_hits::total 1960501
+system.cpu.l2cache.demand_hits::cpu.inst 5
+system.cpu.l2cache.demand_hits::cpu.data 2037586
+system.cpu.l2cache.demand_hits::total 2037591
+system.cpu.l2cache.overall_hits::cpu.inst 5
+system.cpu.l2cache.overall_hits::cpu.data 2037586
+system.cpu.l2cache.overall_hits::total 2037591
+system.cpu.l2cache.ReadExReq_misses::cpu.data 29024
+system.cpu.l2cache.ReadExReq_misses::total 29024
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 803
+system.cpu.l2cache.ReadCleanReq_misses::total 803
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data 219
+system.cpu.l2cache.ReadSharedReq_misses::total 219
+system.cpu.l2cache.demand_misses::cpu.inst 803
+system.cpu.l2cache.demand_misses::cpu.data 29243
+system.cpu.l2cache.demand_misses::total 30046
+system.cpu.l2cache.overall_misses::cpu.inst 803
+system.cpu.l2cache.overall_misses::cpu.data 29243
+system.cpu.l2cache.overall_misses::total 30046
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1755983000
+system.cpu.l2cache.ReadExReq_miss_latency::total 1755983000
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 48585000
+system.cpu.l2cache.ReadCleanReq_miss_latency::total 48585000
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13249500
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 13249500
+system.cpu.l2cache.demand_miss_latency::cpu.inst 48585000
+system.cpu.l2cache.demand_miss_latency::cpu.data 1769232500
+system.cpu.l2cache.demand_miss_latency::total 1817817500
+system.cpu.l2cache.overall_miss_latency::cpu.inst 48585000
+system.cpu.l2cache.overall_miss_latency::cpu.data 1769232500
+system.cpu.l2cache.overall_miss_latency::total 1817817500
+system.cpu.l2cache.WritebackDirty_accesses::writebacks 2062482
+system.cpu.l2cache.WritebackDirty_accesses::total 2062482
+system.cpu.l2cache.WritebackClean_accesses::writebacks 24
+system.cpu.l2cache.WritebackClean_accesses::total 24
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109
+system.cpu.l2cache.ReadExReq_accesses::total 106109
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 808
+system.cpu.l2cache.ReadCleanReq_accesses::total 808
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1960720
+system.cpu.l2cache.ReadSharedReq_accesses::total 1960720
+system.cpu.l2cache.demand_accesses::cpu.inst 808
+system.cpu.l2cache.demand_accesses::cpu.data 2066829
+system.cpu.l2cache.demand_accesses::total 2067637
+system.cpu.l2cache.overall_accesses::cpu.inst 808
+system.cpu.l2cache.overall_accesses::cpu.data 2066829
+system.cpu.l2cache.overall_accesses::total 2067637
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273530
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.273530
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993812
+system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993812
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000112
+system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000112
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993812
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.014149
+system.cpu.l2cache.demand_miss_rate::total 0.014532
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.014149
+system.cpu.l2cache.overall_miss_rate::total 0.014532
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60501.068082
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60501.068082
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60504.358655
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60504.358655
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60504.358655
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.060083
+system.cpu.l2cache.demand_avg_miss_latency::total 60501.148239
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60504.358655
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.060083
+system.cpu.l2cache.overall_avg_miss_latency::total 60501.148239
+system.cpu.l2cache.blocked_cycles::no_mshrs 0
+system.cpu.l2cache.blocked_cycles::no_targets 0
+system.cpu.l2cache.blocked::no_mshrs 0
+system.cpu.l2cache.blocked::no_targets 0
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan
+system.cpu.l2cache.writebacks::writebacks 104
+system.cpu.l2cache.writebacks::total 104
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024
+system.cpu.l2cache.ReadExReq_mshr_misses::total 29024
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 803
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 803
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 219
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 219
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 803
+system.cpu.l2cache.demand_mshr_misses::cpu.data 29243
+system.cpu.l2cache.demand_mshr_misses::total 30046
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 803
+system.cpu.l2cache.overall_mshr_misses::cpu.data 29243
+system.cpu.l2cache.overall_mshr_misses::total 30046
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1465743000
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1465743000
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 40555000
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 40555000
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11059500
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11059500
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40555000
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1476802500
+system.cpu.l2cache.demand_mshr_miss_latency::total 1517357500
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40555000
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1476802500
+system.cpu.l2cache.overall_mshr_miss_latency::total 1517357500
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993812
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993812
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000112
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000112
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014149
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.014532
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014149
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.014532
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50501.068082
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50501.068082
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50504.358655
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50504.358655
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50504.358655
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.060083
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.148239
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50504.358655
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.060083
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.148239
+system.cpu.toL2Bus.snoop_filter.tot_requests 4130394
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 2062757
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0
+system.cpu.toL2Bus.snoop_filter.tot_snoops 197
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 197
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366229314500
+system.cpu.toL2Bus.trans_dist::ReadResp 1961528
+system.cpu.toL2Bus.trans_dist::WritebackDirty 2062586
+system.cpu.toL2Bus.trans_dist::WritebackClean 24
+system.cpu.toL2Bus.trans_dist::CleanEvict 462
+system.cpu.toL2Bus.trans_dist::ReadExReq 106109
+system.cpu.toL2Bus.trans_dist::ReadExResp 106109
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 808
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 1960720
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196391
+system.cpu.toL2Bus.pkt_count::total 6198031
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53248
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264275904
+system.cpu.toL2Bus.pkt_size::total 264329152
+system.cpu.toL2Bus.snoops 315
+system.cpu.toL2Bus.snoopTraffic 6656
+system.cpu.toL2Bus.snoop_fanout::samples 2067952
+system.cpu.toL2Bus.snoop_fanout::mean 0.000095
+system.cpu.toL2Bus.snoop_fanout::stdev 0.009760
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu.toL2Bus.snoop_fanout::0 2067755 99.99% 99.99%
+system.cpu.toL2Bus.snoop_fanout::1 197 0.01% 100.00%
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::min_value 0
+system.cpu.toL2Bus.snoop_fanout::max_value 1
+system.cpu.toL2Bus.snoop_fanout::total 2067952
+system.cpu.toL2Bus.reqLayer0.occupancy 4127703000
+system.cpu.toL2Bus.reqLayer0.utilization 1.1
+system.cpu.toL2Bus.respLayer0.occupancy 1212000
+system.cpu.toL2Bus.respLayer0.utilization 0.0
+system.cpu.toL2Bus.respLayer1.occupancy 3100243500
+system.cpu.toL2Bus.respLayer1.utilization 0.8
+system.membus.snoop_filter.tot_requests 30164
+system.membus.snoop_filter.hit_single_requests 118
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 366229314500
+system.membus.trans_dist::ReadResp 1022
+system.membus.trans_dist::WritebackDirty 104
+system.membus.trans_dist::CleanEvict 14
+system.membus.trans_dist::ReadExReq 29024
+system.membus.trans_dist::ReadExResp 29024
+system.membus.trans_dist::ReadSharedReq 1022
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60210
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60210
+system.membus.pkt_count::total 60210
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929600
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929600
+system.membus.pkt_size::total 1929600
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 30046
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 30046 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 30046
+system.membus.reqLayer0.occupancy 30614500
+system.membus.reqLayer0.utilization 0.0
+system.membus.respLayer1.occupancy 150230000
+system.membus.respLayer1.utilization 0.0
---------- End Simulation Statistics ----------