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-rw-r--r--tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini29
-rwxr-xr-xtests/long/se/20.parser/ref/arm/linux/o3-timing/simout8
-rw-r--r--tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt1224
-rw-r--r--tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini23
-rwxr-xr-xtests/long/se/20.parser/ref/arm/linux/simple-atomic/simout8
-rw-r--r--tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt12
-rw-r--r--tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini33
-rwxr-xr-xtests/long/se/20.parser/ref/arm/linux/simple-timing/simout8
-rw-r--r--tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt12
9 files changed, 684 insertions, 673 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
index d7217517d..0d4631b4b 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -95,7 +96,6 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
-phase=0
predType=tournament
profile=0
progress_interval=0
@@ -129,16 +129,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=1
forward_snoops=true
hash_delay=1
+hit_latency=1000
is_top_level=true
-latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=1000
size=262144
subblock_size=0
system=system
@@ -157,8 +159,8 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
-max_backoff=100000
-min_backoff=0
+clock=1
+num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
@@ -430,16 +432,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=1
forward_snoops=true
hash_delay=1
+hit_latency=1000
is_top_level=true
-latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=1000
size=131072
subblock_size=0
system=system
@@ -461,8 +465,8 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
-max_backoff=100000
-min_backoff=0
+clock=1
+num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
@@ -471,16 +475,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=1
forward_snoops=true
hash_delay=1
+hit_latency=1000
is_top_level=false
-latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=1000
size=2097152
subblock_size=0
system=system
@@ -512,9 +518,9 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/parser
+executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/parser
gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
@@ -535,8 +541,9 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
index 2e50d7c5a..ccc3391a2 100755
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 26 2012 21:40:00
-gem5 started Jul 27 2012 01:18:01
-gem5 executing on zizzer
+gem5 compiled Sep 21 2012 11:19:00
+gem5 started Sep 21 2012 12:11:01
+gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -67,4 +67,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 213305827500 because target called exit()
+Exiting @ tick 205972871500 because target called exit()
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
index c461f7be8..5b82c90b2 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -1,39 +1,39 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.213288 # Number of seconds simulated
-sim_ticks 213288042000 # Number of ticks simulated
-final_tick 213288042000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.205973 # Number of seconds simulated
+sim_ticks 205972871500 # Number of ticks simulated
+final_tick 205972871500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 175103 # Simulator instruction rate (inst/s)
-host_op_rate 197255 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 73380577 # Simulator tick rate (ticks/s)
-host_mem_usage 239036 # Number of bytes of host memory used
-host_seconds 2906.60 # Real time elapsed on the host
-sim_insts 508955143 # Number of instructions simulated
-sim_ops 573341703 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 218176 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10017792 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10235968 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 218176 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 218176 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 6680384 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6680384 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 3409 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 156528 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 159937 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 104381 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 104381 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1022917 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 46968372 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 47991289 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1022917 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1022917 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 31320950 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 31320950 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 31320950 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1022917 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 46968372 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 79312238 # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate 120709 # Simulator instruction rate (inst/s)
+host_op_rate 135980 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 48850733 # Simulator tick rate (ticks/s)
+host_mem_usage 233344 # Number of bytes of host memory used
+host_seconds 4216.37 # Real time elapsed on the host
+sim_insts 508955133 # Number of instructions simulated
+sim_ops 573341693 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 219008 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10022656 # Number of bytes read from this memory
+system.physmem.bytes_read::total 10241664 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 219008 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 219008 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 6678912 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6678912 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 3422 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 156604 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 160026 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 104358 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 104358 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1063286 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 48660078 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 49723364 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1063286 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1063286 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 32426173 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 32426173 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 32426173 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1063286 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 48660078 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 82149537 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@@ -77,319 +77,319 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
-system.cpu.numCycles 426576085 # number of cpu cycles simulated
+system.cpu.numCycles 411945744 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 180740413 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 143314852 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 7747678 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 94843879 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 87610894 # Number of BTB hits
+system.cpu.BPredUnit.lookups 184506499 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 144023121 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 7811219 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 98943918 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 90574887 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 12444215 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 117322 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 121008241 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 797329554 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 180740413 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 100055109 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 177305493 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 41694280 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 95788373 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 733 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 114354334 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 2502299 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 425002999 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.155911 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.022478 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 12841570 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 116417 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 119775248 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 774733961 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 184506499 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 103416457 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 173948363 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 37641339 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 87608822 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 852 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 115427194 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 2630422 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 410365766 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.121718 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.964259 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 247710334 58.28% 58.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 14399236 3.39% 61.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 20683472 4.87% 66.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 22949546 5.40% 71.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 21027590 4.95% 76.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 13189722 3.10% 79.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 13290408 3.13% 83.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 12169042 2.86% 85.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 59583649 14.02% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 236430239 57.61% 57.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 14468090 3.53% 61.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 23474699 5.72% 66.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 23086036 5.63% 72.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 21070083 5.13% 77.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 13375231 3.26% 80.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 13311792 3.24% 84.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 12219273 2.98% 87.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 52930323 12.90% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 425002999 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.423700 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.869138 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 133837358 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 89905115 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 165211809 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 5224015 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 30824702 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 26552626 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 78407 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 873532911 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 312665 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 30824702 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 144300164 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 8880120 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 66226908 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 159798205 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 14972900 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 818719964 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 1527 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 2831804 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 8232958 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 169 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 966624126 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3574819006 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3574814464 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 4542 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 672200163 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 294423963 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 5324035 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 5323684 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 70502461 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 172694215 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 75173419 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 27528293 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 15558221 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 763633649 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 6775757 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 672560408 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1538791 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 194774219 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 494406883 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 3054641 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 425002999 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.582484 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.714723 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 410365766 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.447890 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.880670 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 130418481 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 81705760 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 163995815 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 5288696 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 28957014 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 26711151 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 78514 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 846352874 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 312360 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 28957014 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 138753027 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 8994220 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 57785261 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 160771479 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 15104765 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 816103533 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 1687 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 2833405 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 8341364 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 82 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 971919658 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3572964194 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3572962534 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1660 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 672200147 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 299719511 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 3043063 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 3043057 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 48313295 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 173521024 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 75304332 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 27654560 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 15950244 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 766864948 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 4467940 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 673990845 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1544807 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 195857289 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 503525509 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 746826 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 410365766 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.642415 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.726112 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 161186473 37.93% 37.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 79207972 18.64% 56.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 71181654 16.75% 73.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 52720158 12.40% 85.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 30652473 7.21% 92.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 16004592 3.77% 96.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 9408207 2.21% 98.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 3385200 0.80% 99.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1256270 0.30% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 148669222 36.23% 36.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 76514251 18.65% 54.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 69467282 16.93% 71.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 54325200 13.24% 85.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 31258060 7.62% 92.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 16137199 3.93% 96.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 9372373 2.28% 98.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 3363475 0.82% 99.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 1258704 0.31% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 425002999 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 410365766 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 468819 4.82% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 6672896 68.60% 73.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 2585103 26.58% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 465577 4.81% 4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 6648335 68.74% 73.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 2557266 26.44% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 451779647 67.17% 67.17% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 385833 0.06% 67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 224 0.00% 67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 155287999 23.09% 90.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 65106702 9.68% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 452813787 67.18% 67.18% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 386318 0.06% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 122 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 155728522 23.11% 90.35% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 65062093 9.65% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 672560408 # Type of FU issued
-system.cpu.iq.rate 1.576648 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 9726818 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.014462 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1781388941 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 965987028 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 652168068 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 483 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 954 # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total 673990845 # Type of FU issued
+system.cpu.iq.rate 1.636116 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 9671178 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.014349 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1769563162 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 967995399 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 653126941 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 279 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 382 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 682286983 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 243 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 8456716 # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses 683661882 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 141 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 8511001 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 45921176 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 43296 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 808281 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 17569458 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 46747987 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 44107 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 809559 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 17700373 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 19481 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1162 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 19520 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 1145 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 30824702 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 4157242 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 268994 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 776579176 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 1213475 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 172694215 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 75173419 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 5287043 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 138286 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 7916 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 808281 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 4709079 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 6438741 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 11147820 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 662598495 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 151749553 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 9961913 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 28957014 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 4178303 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 271851 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 772908179 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 1249751 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 173521024 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 75304332 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 2979209 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 139047 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 8399 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 809559 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 4765794 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 4187317 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 8953111 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 663675930 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 152077702 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 10314915 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 6169770 # number of nop insts executed
-system.cpu.iew.exec_refs 215449893 # number of memory reference insts executed
-system.cpu.iew.exec_branches 137324622 # Number of branches executed
-system.cpu.iew.exec_stores 63700340 # Number of stores executed
-system.cpu.iew.exec_rate 1.553295 # Inst execution rate
-system.cpu.iew.wb_sent 657360539 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 652168084 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 375706484 # num instructions producing a value
-system.cpu.iew.wb_consumers 644527400 # num instructions consuming a value
+system.cpu.iew.exec_nop 1575291 # number of nop insts executed
+system.cpu.iew.exec_refs 215744053 # number of memory reference insts executed
+system.cpu.iew.exec_branches 139807568 # Number of branches executed
+system.cpu.iew.exec_stores 63666351 # Number of stores executed
+system.cpu.iew.exec_rate 1.611076 # Inst execution rate
+system.cpu.iew.wb_sent 658363692 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 653126957 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 376897633 # num instructions producing a value
+system.cpu.iew.wb_consumers 649094102 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.528844 # insts written-back per cycle
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system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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-system.cpu.commit.committed_per_cycle::7 3743908 0.95% 94.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 21000112 5.33% 100.00% # Number of insts commited each cycle
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system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
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system.cpu.commit.function_calls 9757362 # Number of function calls committed.
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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-system.cpu.idleCycles 1573086 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 508955143 # Number of Instructions Simulated
-system.cpu.committedOps 573341703 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 508955143 # Number of Instructions Simulated
-system.cpu.cpi 0.838141 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.838141 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.193117 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.193117 # IPC: Total IPC of All Threads
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+system.cpu.idleCycles 1579978 # Total number of cycles that the CPU has spent unscheduled due to idling
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+system.cpu.committedOps 573341693 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 508955133 # Number of Instructions Simulated
+system.cpu.cpi 0.809395 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.809395 # CPI: Total CPI of All Threads
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+system.cpu.ipc_total 1.235491 # IPC: Total IPC of All Threads
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+system.cpu.icache.replacements 15737 # number of replacements
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -398,258 +398,254 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu.dcache.ReadReq_avg_miss_latency::total 12257.560395 # average ReadReq miss latency
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-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12597.560976 # average LoadLockedReq miss latency
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-system.cpu.dcache.overall_avg_miss_latency::cpu.data 17224.133324 # average overall miss latency
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+system.cpu.dcache.ReadReq_avg_miss_latency::total 12274.009083 # average ReadReq miss latency
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+system.cpu.dcache.demand_avg_miss_latency::total 17241.124801 # average overall miss latency
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+system.cpu.dcache.overall_avg_miss_latency::total 17241.124801 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 3250000 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 3198500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 557 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 556 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 5834.829443 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 5752.697842 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 1102963 # number of writebacks
-system.cpu.dcache.writebacks::total 1102963 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422886 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 422886 # number of ReadReq MSHR hits
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-system.cpu.dcache.WriteReq_mshr_hits::total 1206451 # number of WriteReq MSHR hits
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-system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits
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-system.cpu.dcache.overall_mshr_hits::total 1629337 # number of overall MSHR hits
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-system.cpu.dcache.ReadReq_mshr_misses::total 844475 # number of ReadReq MSHR misses
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-system.cpu.dcache.overall_mshr_misses::total 1192653 # number of overall MSHR misses
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-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4797282000 # number of ReadReq MSHR miss cycles
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-system.cpu.dcache.WriteReq_mshr_miss_latency::total 4282442001 # number of WriteReq MSHR miss cycles
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-system.cpu.dcache.overall_mshr_miss_latency::total 9079724001 # number of overall MSHR miss cycles
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-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 5680.786287 # average ReadReq mshr miss latency
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-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 12299.576656 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7613.047551 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 7613.047551 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7613.047551 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 7613.047551 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 1103627 # number of writebacks
+system.cpu.dcache.writebacks::total 1103627 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 426551 # number of ReadReq MSHR hits
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+system.cpu.dcache.LoadLockedReq_mshr_hits::total 43 # number of LoadLockedReq MSHR hits
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+system.cpu.dcache.overall_avg_mshr_miss_latency::total 7618.970026 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 128744 # number of replacements
-system.cpu.l2cache.tagsinuse 26549.966960 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1724517 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 159966 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 10.780522 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 109550119000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 22719.596227 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 306.601446 # Average occupied blocks per requestor
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-system.cpu.l2cache.ReadReq_hits::cpu.inst 14447 # number of ReadReq hits
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-system.cpu.l2cache.Writeback_hits::total 1102963 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 44 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 44 # number of UpgradeReq hits
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-system.cpu.l2cache.overall_hits::cpu.data 1036047 # number of overall hits
-system.cpu.l2cache.overall_hits::total 1050494 # number of overall hits
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-system.cpu.l2cache.ReadReq_misses::cpu.data 53074 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 56489 # number of ReadReq misses
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-system.cpu.l2cache.UpgradeReq_misses::total 8 # number of UpgradeReq misses
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+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4881219000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 4991549000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110330000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4881219000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 4991549000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.194509 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.063164 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.065855 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.074074 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.074074 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.293923 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.293923 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.194509 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.131240 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.132159 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.194509 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.131240 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.132159 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32241.379310 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31403.118354 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31453.835817 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31047.298995 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31047.298995 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32220.299208 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31168.566208 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31190.983381 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32220.299208 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31168.566208 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31190.983381 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31048.744539 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31048.744539 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32241.379310 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31168.985665 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31191.917614 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32241.379310 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31168.985665 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31191.917614 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
index b319ef658..b8f82bdb1 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
@@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -48,7 +49,6 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
@@ -68,8 +68,8 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
-max_backoff=100000
-min_backoff=0
+clock=1
+num_squash_per_cycle=2
sys=system
port=system.membus.slave[4]
@@ -84,8 +84,8 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
-max_backoff=100000
-min_backoff=0
+clock=1
+num_squash_per_cycle=2
sys=system
port=system.membus.slave[3]
@@ -95,14 +95,14 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
-cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic
+cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/parser
+executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/parser
gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
@@ -117,14 +117,15 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
-width=64
-master=system.physmem.port[0]
+width=8
+master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
index 5020b6420..44b6f8e46 100755
--- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 28 2012 22:10:14
-gem5 started Jun 29 2012 00:45:54
-gem5 executing on zizzer
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic
+gem5 compiled Sep 21 2012 11:19:00
+gem5 started Sep 21 2012 11:53:48
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
index d3328d763..c1ae2a092 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.290499 # Nu
sim_ticks 290498967000 # Number of ticks simulated
final_tick 290498967000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3026360 # Simulator instruction rate (inst/s)
-host_op_rate 3411010 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1735464120 # Simulator tick rate (ticks/s)
-host_mem_usage 228428 # Number of bytes of host memory used
-host_seconds 167.39 # Real time elapsed on the host
+host_inst_rate 2312706 # Simulator instruction rate (inst/s)
+host_op_rate 2606651 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1326219887 # Simulator tick rate (ticks/s)
+host_mem_usage 222284 # Number of bytes of host memory used
+host_seconds 219.04 # Real time elapsed on the host
sim_insts 506581607 # Number of instructions simulated
sim_ops 570968167 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 2066445500 # Number of bytes read from this memory
@@ -84,7 +84,7 @@ system.cpu.committedOps 570968167 # Nu
system.cpu.num_int_alu_accesses 470727695 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 19311615 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 94894804 # number of instructions that are conditional controls
+system.cpu.num_conditional_control_insts 94895872 # number of instructions that are conditional controls
system.cpu.num_int_insts 470727695 # number of integer instructions
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_int_register_reads 2465023683 # number of times the integer registers were read
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
index ffe909bf7..b61e69811 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
@@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -47,7 +48,6 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
system=system
@@ -61,16 +61,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=1
forward_snoops=true
hash_delay=1
+hit_latency=1000
is_top_level=true
-latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=1000
size=262144
subblock_size=0
system=system
@@ -89,8 +91,8 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
-max_backoff=100000
-min_backoff=0
+clock=1
+num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
@@ -99,16 +101,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=1
forward_snoops=true
hash_delay=1
+hit_latency=1000
is_top_level=true
-latency=1000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=1000
size=131072
subblock_size=0
system=system
@@ -130,8 +134,8 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
-max_backoff=100000
-min_backoff=0
+clock=1
+num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
@@ -140,16 +144,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=1
forward_snoops=true
hash_delay=1
+hit_latency=10000
is_top_level=false
-latency=10000
max_miss_count=0
mshrs=10
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=10000
size=2097152
subblock_size=0
system=system
@@ -176,14 +182,14 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
-cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing
+cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/parser
+executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/parser
gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
@@ -199,13 +205,14 @@ clock=1000
header_cycles=1
use_default_range=false
width=8
-master=system.physmem.port[0]
+master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
index 384283516..256134bc2 100755
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 2 2012 09:08:16
-gem5 started Jul 2 2012 15:48:14
-gem5 executing on zizzer
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing
+gem5 compiled Sep 21 2012 11:19:00
+gem5 started Sep 21 2012 12:31:48
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
index b8350e4f6..3143a40a6 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.720346 # Nu
sim_ticks 720345914000 # Number of ticks simulated
final_tick 720345914000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 808443 # Simulator instruction rate (inst/s)
-host_op_rate 910979 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1153216038 # Simulator tick rate (ticks/s)
-host_mem_usage 236932 # Number of bytes of host memory used
-host_seconds 624.64 # Real time elapsed on the host
+host_inst_rate 1112468 # Simulator instruction rate (inst/s)
+host_op_rate 1253563 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1586896277 # Simulator tick rate (ticks/s)
+host_mem_usage 231144 # Number of bytes of host memory used
+host_seconds 453.93 # Real time elapsed on the host
sim_insts 504986853 # Number of instructions simulated
sim_ops 569034839 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 178368 # Number of bytes read from this memory
@@ -85,7 +85,7 @@ system.cpu.committedOps 569034839 # Nu
system.cpu.num_int_alu_accesses 470727695 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 19311615 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 94894804 # number of instructions that are conditional controls
+system.cpu.num_conditional_control_insts 94895872 # number of instructions that are conditional controls
system.cpu.num_int_insts 470727695 # number of integer instructions
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_int_register_reads 2844375179 # number of times the integer registers were read