diff options
Diffstat (limited to 'tests/long/se/30.eon/ref/alpha/tru64/simple-timing')
3 files changed, 102 insertions, 102 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini index b05b7d5ce..b7b2de2d4 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini @@ -158,7 +158,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout index 39e268f04..535f9cae3 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout @@ -1,14 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 13:47:31 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:12:10 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.566667 -Exiting @ tick 567343170000 because target called exit() +Exiting @ tick 567342918000 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index f16fecb77..049129481 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.567343 # Number of seconds simulated -sim_ticks 567343170000 # Number of ticks simulated -final_tick 567343170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 567342918000 # Number of ticks simulated +final_tick 567342918000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1377504 # Simulator instruction rate (inst/s) -host_op_rate 1377504 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1960338494 # Simulator tick rate (ticks/s) -host_mem_usage 220796 # Number of bytes of host memory used -host_seconds 289.41 # Real time elapsed on the host +host_inst_rate 2055836 # Simulator instruction rate (inst/s) +host_op_rate 2055836 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2925676505 # Simulator tick rate (ticks/s) +host_mem_usage 224040 # Number of bytes of host memory used +host_seconds 193.92 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 254400 # Number of bytes read from this memory -system.physmem.bytes_read::total 459520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory +system.physmem.bytes_read::total 459136 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 205120 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 205120 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 3205 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3975 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7180 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7174 # Number of read requests responded to by this memory system.physmem.bw_read::cpu.inst 361545 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 448406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 809951 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 447729 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 809274 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 361545 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 361545 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu.inst 361545 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 448406 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 809951 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 447729 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 809274 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 1134686340 # number of cpu cycles simulated +system.cpu.numCycles 1134685836 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664609 # Number of instructions committed @@ -79,16 +79,16 @@ system.cpu.num_mem_refs 168275276 # nu system.cpu.num_load_insts 94754511 # Number of load instructions system.cpu.num_store_insts 73520765 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1134686340 # Number of busy cycles +system.cpu.num_busy_cycles 1134685836 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1769 # number of replacements -system.cpu.icache.tagsinuse 1795.131074 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1795.131072 # Cycle average of tags in use system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 108538.250204 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1795.131074 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1795.131072 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.876529 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.876529 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits @@ -161,12 +161,12 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47648.516199 system.cpu.icache.overall_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements -system.cpu.dcache.tagsinuse 3288.912598 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3288.912595 # Cycle average of tags in use system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3288.912598 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 3288.912595 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.802957 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.802957 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits @@ -185,14 +185,14 @@ system.cpu.dcache.demand_misses::cpu.data 4152 # n system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses system.cpu.dcache.overall_misses::total 4152 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 48286000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 48286000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 48034000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 48034000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 176792000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 176792000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 225078000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 225078000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 225078000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 225078000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 224826000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 224826000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 224826000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 224826000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) @@ -209,14 +209,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50827.368421 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50827.368421 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50562.105263 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50562.105263 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55212.991880 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 55212.991880 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54209.537572 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54209.537572 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54209.537572 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54209.537572 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54148.843931 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54148.843931 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54148.843931 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54148.843931 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -235,14 +235,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45436000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 45436000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45184000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 45184000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167186000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 167186000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212622000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 212622000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212622000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 212622000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212370000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 212370000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212370000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 212370000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -251,63 +251,63 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47827.368421 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47827.368421 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47562.105263 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47562.105263 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52212.991880 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52212.991880 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51209.537572 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51209.537572 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51209.537572 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51209.537572 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 13 # number of replacements -system.cpu.l2cache.tagsinuse 3768.712262 # Cycle average of tags in use -system.cpu.l2cache.total_refs 656 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4572 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.143482 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 3772.462815 # Cycle average of tags in use +system.cpu.l2cache.total_refs 674 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 4566 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.147613 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 371.536808 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2770.454482 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 626.720973 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 371.536806 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2770.454477 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 630.471532 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.011338 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019126 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.115012 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.019240 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.115126 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 468 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 117 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 585 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 591 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 468 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 177 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 645 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 651 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 468 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 177 # number of overall hits -system.cpu.l2cache.overall_hits::total 645 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits +system.cpu.l2cache.overall_hits::total 651 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 3205 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 833 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4038 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 827 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4032 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 3142 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 3142 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 3205 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3975 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7180 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3969 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7174 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 3205 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3975 # number of overall misses -system.cpu.l2cache.overall_misses::total 7180 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses +system.cpu.l2cache.overall_misses::total 7174 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 166660000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43316000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 209976000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43004000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 209664000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 163384000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 163384000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 166660000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 206700000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 373360000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 206388000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 373048000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 166660000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 206700000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 373360000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 206388000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 373048000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 3673 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 950 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 4623 # number of ReadReq accesses(hits+misses) @@ -322,16 +322,16 @@ system.cpu.l2cache.overall_accesses::cpu.inst 3673 system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 7825 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.872584 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.876842 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.873459 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.870526 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.872161 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981262 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.981262 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.872584 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.957370 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.917572 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # 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