diff options
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/arm/linux/simple-timing')
3 files changed, 159 insertions, 159 deletions
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini index 1dd9a3ff2..a14c026cf 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini @@ -176,7 +176,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing +cwd=build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout index 579afd945..e82eb191d 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:24:05 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 01:12:18 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -1385,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 2369901960000 because target called exit() +Exiting @ tick 2369826854000 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 4610b3f7b..a105f9616 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.369902 # Number of seconds simulated -sim_ticks 2369901960000 # Number of ticks simulated -final_tick 2369901960000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.369827 # Number of seconds simulated +sim_ticks 2369826854000 # Number of ticks simulated +final_tick 2369826854000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 768078 # Simulator instruction rate (inst/s) -host_op_rate 1041952 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1317503901 # Simulator tick rate (ticks/s) -host_mem_usage 235416 # Number of bytes of host memory used -host_seconds 1798.78 # Real time elapsed on the host -sim_insts 1381604347 # Number of instructions simulated -sim_ops 1874244950 # Number of ops (including micro ops) simulated +host_inst_rate 1185646 # Simulator instruction rate (inst/s) +host_op_rate 1608413 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2033704433 # Simulator tick rate (ticks/s) +host_mem_usage 241756 # Number of bytes of host memory used +host_seconds 1165.28 # Real time elapsed on the host +sim_insts 1381604339 # Number of instructions simulated +sim_ops 1874244941 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 144448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 94551872 # Number of bytes read from this memory -system.physmem.bytes_read::total 94696320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94437440 # Number of bytes read from this memory +system.physmem.bytes_read::total 94581888 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 144448 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 144448 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 2257 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1477373 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1479630 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1475585 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1477842 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 60951 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 39896955 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 39957906 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 60951 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 60951 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1785026 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1785026 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1785026 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 60951 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 39896955 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41742932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 60953 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 39849932 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 39910885 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 60953 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 60953 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1785082 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1785082 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1785082 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 60953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 39849932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41695968 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,43 +77,43 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 4739803920 # number of cpu cycles simulated +system.cpu.numCycles 4739653708 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1381604347 # Number of instructions committed -system.cpu.committedOps 1874244950 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1653698876 # Number of integer alu accesses +system.cpu.committedInsts 1381604339 # Number of instructions committed +system.cpu.committedOps 1874244941 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1653698868 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses -system.cpu.num_func_calls 80344203 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 223735906 # number of instructions that are conditional controls -system.cpu.num_int_insts 1653698876 # number of integer instructions +system.cpu.num_func_calls 80372855 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 223735905 # number of instructions that are conditional controls +system.cpu.num_int_insts 1653698868 # number of integer instructions system.cpu.num_fp_insts 52289415 # number of float instructions -system.cpu.num_int_register_reads 10466679954 # number of times the integer registers were read -system.cpu.num_int_register_writes 1874331406 # number of times the integer registers were written +system.cpu.num_int_register_reads 10466679913 # number of times the integer registers were read +system.cpu.num_int_register_writes 1874331393 # number of times the integer registers were written system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written -system.cpu.num_mem_refs 908382480 # number of memory refs -system.cpu.num_load_insts 631387182 # Number of load instructions +system.cpu.num_mem_refs 908382479 # number of memory refs +system.cpu.num_load_insts 631387181 # Number of load instructions system.cpu.num_store_insts 276995298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4739803920 # Number of busy cycles +system.cpu.num_busy_cycles 4739653708 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 18364 # number of replacements -system.cpu.icache.tagsinuse 1392.324437 # Cycle average of tags in use -system.cpu.icache.total_refs 1390251708 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1392.324421 # Cycle average of tags in use +system.cpu.icache.total_refs 1390251699 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 19803 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 70204.095743 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 70204.095289 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1392.324437 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1392.324421 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.679846 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.679846 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1390251708 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1390251708 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1390251708 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1390251708 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1390251708 # number of overall hits -system.cpu.icache.overall_hits::total 1390251708 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 1390251699 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1390251699 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1390251699 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1390251699 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1390251699 # number of overall hits +system.cpu.icache.overall_hits::total 1390251699 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 19803 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 19803 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 19803 # number of demand (read+write) misses @@ -126,12 +126,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 372036000 system.cpu.icache.demand_miss_latency::total 372036000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 372036000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 372036000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1390271511 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1390271511 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1390271511 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1390271511 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1390271511 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1390271511 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 1390271502 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1390271502 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1390271502 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1390271502 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1390271502 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1390271502 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000014 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000014 # miss rate for demand accesses @@ -178,26 +178,26 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15786.850477 system.cpu.icache.overall_avg_mshr_miss_latency::total 15786.850477 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1529557 # number of replacements -system.cpu.dcache.tagsinuse 4094.960333 # Cycle average of tags in use -system.cpu.dcache.total_refs 895757409 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4094.960317 # Cycle average of tags in use +system.cpu.dcache.total_refs 895757408 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1533653 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 584.067849 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 997882000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.960333 # Average occupied blocks per requestor +system.cpu.dcache.avg_refs 584.067848 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 997872000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.960317 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999746 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999746 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 618874541 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 618874541 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 618874540 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 618874540 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 276862898 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 276862898 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9985 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9985 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 895737439 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 895737439 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 895737439 # number of overall hits -system.cpu.dcache.overall_hits::total 895737439 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 895737438 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 895737438 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 895737438 # number of overall hits +system.cpu.dcache.overall_hits::total 895737438 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1460873 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1460873 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 72780 # number of WriteReq misses @@ -206,26 +206,26 @@ system.cpu.dcache.demand_misses::cpu.data 1533653 # n system.cpu.dcache.demand_misses::total 1533653 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1533653 # number of overall misses system.cpu.dcache.overall_misses::total 1533653 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 79725982000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 79725982000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 79650886000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 79650886000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 3794826000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 3794826000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83520808000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83520808000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83520808000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83520808000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 620335414 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 620335414 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 83445712000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83445712000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83445712000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83445712000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 620335413 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 620335413 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 9985 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 9985 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 897271092 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 897271092 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 897271092 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 897271092 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 897271091 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 897271091 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 897271091 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 897271091 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002355 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002355 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000263 # miss rate for WriteReq accesses @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.001709 system.cpu.dcache.demand_miss_rate::total 0.001709 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.001709 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.001709 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54574.204602 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54574.204602 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54522.799723 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54522.799723 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52141.055235 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 52141.055235 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54458.738711 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54458.738711 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54458.738711 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54458.738711 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54409.773267 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54409.773267 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54409.773267 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54409.773267 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -250,8 +250,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 107259 # number of writebacks -system.cpu.dcache.writebacks::total 107259 # number of writebacks +system.cpu.dcache.writebacks::writebacks 109047 # number of writebacks +system.cpu.dcache.writebacks::total 109047 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460873 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1460873 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72780 # number of WriteReq MSHR misses @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1533653 system.cpu.dcache.demand_mshr_misses::total 1533653 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1533653 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1533653 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75343363000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75343363000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75268267000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75268267000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3576486000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3576486000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78919849000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 78919849000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78919849000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 78919849000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78844753000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 78844753000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78844753000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 78844753000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002355 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000263 # mshr miss rate for WriteReq accesses @@ -276,68 +276,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001709 system.cpu.dcache.demand_mshr_miss_rate::total 0.001709 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001709 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51574.204602 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51574.204602 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51522.799723 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51522.799723 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.055235 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.055235 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51458.738711 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51458.738711 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51458.738711 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51458.738711 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51409.773267 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51409.773267 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51409.773267 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51409.773267 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1478755 # number of replacements -system.cpu.l2cache.tagsinuse 31934.844118 # Cycle average of tags in use -system.cpu.l2cache.total_refs 75453 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1511475 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.049920 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1478696 # number of replacements +system.cpu.l2cache.tagsinuse 32689.777876 # Cycle average of tags in use +system.cpu.l2cache.total_refs 77413 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1511439 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.051218 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3041.423322 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 32.598415 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28860.822381 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.092817 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000995 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.880762 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.974574 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 3194.588699 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 32.929350 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 29462.259827 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.097491 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001005 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.899117 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.997613 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 17546 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 49593 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 67139 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 107259 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 107259 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.data 51381 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 68927 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 109047 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 109047 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 6687 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 6687 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 17546 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 56280 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 73826 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 58068 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 75614 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 17546 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 56280 # number of overall hits -system.cpu.l2cache.overall_hits::total 73826 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 58068 # number of overall hits +system.cpu.l2cache.overall_hits::total 75614 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 2257 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1411280 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1413537 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1409492 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1411749 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 66093 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66093 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 2257 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1477373 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1479630 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1475585 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1477842 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 2257 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1477373 # number of overall misses -system.cpu.l2cache.overall_misses::total 1479630 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1475585 # number of overall misses +system.cpu.l2cache.overall_misses::total 1477842 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 117364000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 73386560000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 73503924000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 73293584000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 73410948000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3436836000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3436836000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 117364000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 76823396000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 76940760000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 76730420000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 76847784000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 117364000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 76823396000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 76940760000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 76730420000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 76847784000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 19803 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1460873 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1480676 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 107259 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 107259 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 109047 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 109047 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 72780 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 72780 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 19803 # number of demand (read+write) accesses @@ -347,16 +347,16 @@ system.cpu.l2cache.overall_accesses::cpu.inst 19803 system.cpu.l2cache.overall_accesses::cpu.data 1533653 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 1553456 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113973 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.966052 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.954657 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.964829 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.953449 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.908120 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.908120 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113973 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.963303 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.952476 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.962137 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.951325 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113973 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.963303 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.952476 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.962137 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.951325 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency @@ -379,38 +379,38 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks system.cpu.l2cache.writebacks::total 66099 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2257 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1411280 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1413537 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1409492 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1411749 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964829 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.953449 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908120 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.908120 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963303 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.952476 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.962137 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.951325 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963303 # 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