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-rw-r--r--tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini2
-rwxr-xr-xtests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout8
-rw-r--r--tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt294
3 files changed, 152 insertions, 152 deletions
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
index 5c77a44a2..643e6799d 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
@@ -179,7 +179,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing
+cwd=build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing
egid=100
env=
errout=cerr
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
index 11192711e..5dc44ec4f 100755
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 4 2012 13:44:28
-gem5 started Jun 4 2012 16:08:32
+gem5 compiled Jun 28 2012 22:08:09
+gem5 started Jun 28 2012 23:47:42
gem5 executing on zizzer
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
@@ -24,4 +24,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 5923548078000 because target called exit()
+Exiting @ tick 5900695290000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
index e2cb03bbf..faa206e56 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
@@ -1,41 +1,41 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 5.923548 # Number of seconds simulated
-sim_ticks 5923548078000 # Number of ticks simulated
-final_tick 5923548078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.900695 # Number of seconds simulated
+sim_ticks 5900695290000 # Number of ticks simulated
+final_tick 5900695290000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 633731 # Simulator instruction rate (inst/s)
-host_op_rate 987410 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1247949692 # Simulator tick rate (ticks/s)
-host_mem_usage 225520 # Number of bytes of host memory used
-host_seconds 4746.62 # Real time elapsed on the host
+host_inst_rate 1070782 # Simulator instruction rate (inst/s)
+host_op_rate 1668375 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2100461088 # Simulator tick rate (ticks/s)
+host_mem_usage 228516 # Number of bytes of host memory used
+host_seconds 2809.24 # Real time elapsed on the host
sim_insts 3008081057 # Number of instructions simulated
sim_ops 4686862651 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 173866880 # Number of bytes read from this memory
-system.physmem.bytes_read::total 173910080 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 139043584 # Number of bytes read from this memory
+system.physmem.bytes_read::total 139086784 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 75176384 # Number of bytes written to this memory
-system.physmem.bytes_written::total 75176384 # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks 67393856 # Number of bytes written to this memory
+system.physmem.bytes_written::total 67393856 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 2716670 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 2717345 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1174631 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1174631 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 7293 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 29351814 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 29359107 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 7293 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 7293 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 12691107 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 12691107 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 12691107 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 7293 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 29351814 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 42050214 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::cpu.data 2172556 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 2173231 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1053029 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1053029 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 7321 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 23563932 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 23571253 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 7321 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 7321 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 11421342 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 11421342 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 11421342 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 7321 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 23563932 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 34992595 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 46 # Number of system calls
-system.cpu.numCycles 11847096156 # number of cpu cycles simulated
+system.cpu.numCycles 11801390580 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 3008081057 # Number of instructions committed
@@ -54,18 +54,18 @@ system.cpu.num_mem_refs 1677713086 # nu
system.cpu.num_load_insts 1239184749 # Number of load instructions
system.cpu.num_store_insts 438528337 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 11847096156 # Number of busy cycles
+system.cpu.num_busy_cycles 11801390580 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 10 # number of replacements
-system.cpu.icache.tagsinuse 555.713137 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 555.745205 # Cycle average of tags in use
system.cpu.icache.total_refs 4013232252 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 5945529.262222 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 555.713137 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.271344 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.271344 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst 555.745205 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.271360 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.271360 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 4013232252 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 4013232252 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 4013232252 # number of demand (read+write) hits
@@ -136,14 +136,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9108581 # number of replacements
-system.cpu.dcache.tagsinuse 4084.662246 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4084.618409 # Cycle average of tags in use
system.cpu.dcache.total_refs 1668600409 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 58862779000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4084.662246 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.997232 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.997232 # Average percentage of cache occupancy
+system.cpu.dcache.warmup_cycle 58862653000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4084.618409 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.997221 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.997221 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1231961899 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1231961899 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 436638510 # number of WriteReq hits
@@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 9112677 # n
system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses
system.cpu.dcache.overall_misses::total 9112677 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 177808540000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 177808540000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 63869078000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 63869078000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 241677618000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 241677618000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 241677618000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 241677618000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 159193930000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 159193930000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 59630900000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 59630900000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 218824830000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 218824830000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 218824830000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 218824830000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1239184749 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1239184749 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 438528337 # number of WriteReq accesses(hits+misses)
@@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005432
system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24617.504171 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 24617.504171 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33796.256483 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 33796.256483 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 26521.034159 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 26521.034159 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 26521.034159 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 26521.034159 # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22040.320649 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 22040.320649 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31553.628983 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 31553.628983 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 24013.232336 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 24013.232336 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 24013.232336 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 24013.232336 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -200,8 +200,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 3053391 # number of writebacks
-system.cpu.dcache.writebacks::total 3053391 # number of writebacks
+system.cpu.dcache.writebacks::writebacks 3375759 # number of writebacks
+system.cpu.dcache.writebacks::total 3375759 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses
@@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9112677
system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 156139990000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 156139990000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58199597000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 58199597000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 214339587000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 214339587000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 214339587000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 214339587000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137525380000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 137525380000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53961419000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 53961419000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191486799000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 191486799000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191486799000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 191486799000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses
@@ -226,65 +226,65 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432
system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21617.504171 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21617.504171 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30796.256483 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30796.256483 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23521.034159 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 23521.034159 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23521.034159 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 23521.034159 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19040.320649 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19040.320649 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28553.628983 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28553.628983 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21013.232336 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 21013.232336 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21013.232336 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 21013.232336 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 2706631 # number of replacements
-system.cpu.l2cache.tagsinuse 26507.350069 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 7537629 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 2732923 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 2.758083 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 1324806325000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 11028.544571 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 19.163936 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 15459.641562 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.336564 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.000585 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.471791 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.808940 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.data 5396930 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 5396930 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 3053391 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 3053391 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 999077 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 999077 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.data 6396007 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 6396007 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.data 6396007 # number of overall hits
-system.cpu.l2cache.overall_hits::total 6396007 # number of overall hits
+system.cpu.l2cache.replacements 2158210 # number of replacements
+system.cpu.l2cache.tagsinuse 30851.506102 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 8410861 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 2187939 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 3.844194 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 1317336331000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 14661.525978 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 21.582601 # Average occupied blocks per requestor
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