diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic')
-rwxr-xr-x | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout | 7 | ||||
-rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt | 228 |
2 files changed, 117 insertions, 118 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout index 92dc7ad3d..d842316f6 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout @@ -1,12 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:07:23 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:10:03 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1829332258000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 4492aa0b0..e2a65cb45 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,109 +4,109 @@ sim_seconds 1.829332 # Nu sim_ticks 1829332258000 # Number of ticks simulated final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2878195 # Simulator instruction rate (inst/s) -host_op_rate 2878193 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 87696777763 # Simulator tick rate (ticks/s) -host_mem_usage 296144 # Number of bytes of host memory used -host_seconds 20.86 # Real time elapsed on the host +host_inst_rate 4017982 # Simulator instruction rate (inst/s) +host_op_rate 4017978 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 122425314574 # Simulator tick rate (ticks/s) +host_mem_usage 297960 # Number of bytes of host memory used +host_seconds 14.94 # Real time elapsed on the host sim_insts 60038305 # Number of instructions simulated sim_ops 60038305 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 955904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 68042304 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652608 # Number of bytes read from this memory -system.physmem.bytes_read::total 71650816 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 955904 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 955904 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10156864 # Number of bytes written to this memory -system.physmem.bytes_written::total 10156864 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 14936 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1063161 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41447 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1119544 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 158701 # Number of write requests responded to by this memory -system.physmem.num_writes::total 158701 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 522543 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 37195159 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1450042 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 39167743 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 522543 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 522543 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 5552225 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5552225 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 5552225 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 522543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 37195159 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1450042 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 44719968 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 1045877 # number of replacements -system.l2c.tagsinuse 33807.015903 # Cycle average of tags in use -system.l2c.total_refs 2291835 # Total number of references to valid blocks. -system.l2c.sampled_refs 1077848 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.126306 # Average number of references to valid blocks. -system.l2c.warmup_cycle 765422500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 23613.410409 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 3680.391656 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6513.213838 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.360312 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.056158 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.099384 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.515854 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.inst 905267 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 794128 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1699395 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 825291 # number of Writeback hits -system.l2c.Writeback_hits::total 825291 # number of Writeback hits +system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 66839424 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory +system.physmem.bytes_read::total 70349696 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7411392 # Number of bytes written to this memory +system.physmem.bytes_written::total 7411392 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1044366 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1099214 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115803 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115803 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36537607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1449867 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 38456489 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4051419 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4051419 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4051419 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36537607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1449867 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42507908 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 992301 # number of replacements +system.l2c.tagsinuse 65424.374305 # Cycle average of tags in use +system.l2c.total_refs 2433195 # Total number of references to valid blocks. +system.l2c.sampled_refs 1057464 # Sample count of references to valid blocks. +system.l2c.avg_refs 2.300972 # Average number of references to valid blocks. +system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 56309.122439 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 4867.329747 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 4247.922119 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.998297 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.inst 906797 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 811183 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1717980 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 833599 # number of Writeback hits +system.l2c.Writeback_hits::total 833599 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 185383 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 185383 # number of ReadExReq hits -system.l2c.demand_hits::cpu.inst 905267 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 979511 # number of demand (read+write) hits -system.l2c.demand_hits::total 1884778 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.inst 905267 # number of overall hits -system.l2c.overall_hits::cpu.data 979511 # number of overall hits -system.l2c.overall_hits::total 1884778 # number of overall hits -system.l2c.ReadReq_misses::cpu.inst 14936 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 944693 # number of ReadReq misses -system.l2c.ReadReq_misses::total 959629 # number of ReadReq misses +system.l2c.ReadExReq_hits::cpu.data 187125 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 187125 # number of ReadExReq hits +system.l2c.demand_hits::cpu.inst 906797 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 998308 # number of demand (read+write) hits +system.l2c.demand_hits::total 1905105 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.inst 906797 # number of overall hits +system.l2c.overall_hits::cpu.data 998308 # number of overall hits +system.l2c.overall_hits::total 1905105 # number of overall hits +system.l2c.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 927640 # number of ReadReq misses +system.l2c.ReadReq_misses::total 941046 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 12 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 118859 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 118859 # number of ReadExReq misses -system.l2c.demand_misses::cpu.inst 14936 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 1063552 # number of demand (read+write) misses -system.l2c.demand_misses::total 1078488 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.inst 14936 # number of overall misses -system.l2c.overall_misses::cpu.data 1063552 # number of overall misses -system.l2c.overall_misses::total 1078488 # number of overall misses +system.l2c.ReadExReq_misses::cpu.data 117117 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 117117 # number of ReadExReq misses +system.l2c.demand_misses::cpu.inst 13406 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 1044757 # number of demand (read+write) misses +system.l2c.demand_misses::total 1058163 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.inst 13406 # number of overall misses +system.l2c.overall_misses::cpu.data 1044757 # number of overall misses +system.l2c.overall_misses::total 1058163 # number of overall misses system.l2c.ReadReq_accesses::cpu.inst 920203 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1738821 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2659024 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 825291 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 825291 # number of Writeback accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1738823 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2659026 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 833599 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 833599 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu.data 13 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 13 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu.data 304242 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 304242 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu.inst 920203 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 2043063 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2963266 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 2043065 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2963268 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu.inst 920203 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 2043063 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2963266 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.016231 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.543295 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.360895 # miss rate for ReadReq accesses +system.l2c.overall_accesses::cpu.data 2043065 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2963268 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.533487 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.353906 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.923077 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.923077 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.390673 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.390673 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.inst 0.016231 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.520567 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.363952 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.inst 0.016231 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.520567 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.363952 # miss rate for overall accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.384947 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.384947 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.511367 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.357093 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.511367 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.357093 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -115,8 +115,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 117189 # number of writebacks -system.l2c.writebacks::total 117189 # number of writebacks +system.l2c.writebacks::writebacks 74291 # number of writebacks +system.l2c.writebacks::total 74291 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41686 # number of replacements system.iocache.tagsinuse 1.225570 # Cycle average of tags in use @@ -388,37 +388,37 @@ system.cpu.icache.cache_copies 0 # nu system.cpu.icache.writebacks::writebacks 108 # number of writebacks system.cpu.icache.writebacks::total 108 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2042700 # number of replacements +system.cpu.dcache.replacements 2042702 # number of replacements system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use -system.cpu.dcache.total_refs 14038433 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2043212 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 6.870767 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 14038431 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2043214 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 6.870759 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7807782 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7807782 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 7807780 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7807780 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 5848212 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 5848212 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13655994 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13655994 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13655994 # number of overall hits -system.cpu.dcache.overall_hits::total 13655994 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1721705 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1721705 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 13655992 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13655992 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13655992 # number of overall hits +system.cpu.dcache.overall_hits::total 13655992 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1721707 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1721707 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2026067 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2026067 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2026067 # number of overall misses -system.cpu.dcache.overall_misses::total 2026067 # number of overall misses +system.cpu.dcache.demand_misses::cpu.data 2026069 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2026069 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2026069 # number of overall misses +system.cpu.dcache.overall_misses::total 2026069 # number of overall misses system.cpu.dcache.ReadReq_accesses::cpu.data 9529487 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6152574 # number of WriteReq accesses(hits+misses) @@ -431,16 +431,16 @@ system.cpu.dcache.demand_accesses::cpu.data 15682061 # system.cpu.dcache.demand_accesses::total 15682061 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 15682061 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180671 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.180671 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.129196 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.129196 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.129196 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.129196 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -449,8 +449,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 825183 # number of writebacks -system.cpu.dcache.writebacks::total 825183 # number of writebacks +system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks +system.cpu.dcache.writebacks::total 833491 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |