diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/linux/inorder-timing')
3 files changed, 228 insertions, 228 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini index 5cc0911e9..e1fc4e09c 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini @@ -181,7 +181,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -213,7 +213,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout index b9f1a2caf..da63093c1 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:15:31 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 09:08:18 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 21234500 because target called exit() +Exiting @ tick 21985500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 6887d118d..b38d65b68 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 21234500 # Number of ticks simulated -final_tick 21234500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000022 # Number of seconds simulated +sim_ticks 21985500 # Number of ticks simulated +final_tick 21985500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 73768 # Simulator instruction rate (inst/s) -host_op_rate 73752 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 244499363 # Simulator tick rate (ticks/s) -host_mem_usage 214444 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 65949 # Simulator instruction rate (inst/s) +host_op_rate 65938 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 226330541 # Simulator tick rate (ticks/s) +host_mem_usage 218192 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated sim_ops 6404 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19264 # Nu system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 469 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 907202901 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 506345805 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1413548706 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 907202901 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 907202901 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 907202901 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 506345805 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1413548706 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 876213868 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 489049601 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1365263469 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 876213868 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 876213868 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 876213868 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 489049601 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1365263469 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -35,14 +35,14 @@ system.cpu.dtb.read_hits 1186 # DT system.cpu.dtb.read_misses 7 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_accesses 1193 # DTB read accesses -system.cpu.dtb.write_hits 898 # DTB write hits +system.cpu.dtb.write_hits 900 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 901 # DTB write accesses -system.cpu.dtb.data_hits 2084 # DTB hits +system.cpu.dtb.write_accesses 903 # DTB write accesses +system.cpu.dtb.data_hits 2086 # DTB hits system.cpu.dtb.data_misses 10 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2094 # DTB accesses +system.cpu.dtb.data_accesses 2096 # DTB accesses system.cpu.itb.fetch_hits 908 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv @@ -60,26 +60,26 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 42470 # number of cpu cycles simulated +system.cpu.numCycles 43972 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 1608 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 1127 # Number of conditional branches predicted +system.cpu.branch_predictor.lookups 1607 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 1126 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 712 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1187 # Number of BTB lookups +system.cpu.branch_predictor.BTBLookups 1186 # Number of BTB lookups system.cpu.branch_predictor.BTBHits 314 # Number of BTB hits system.cpu.branch_predictor.usedRAS 126 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 26.453243 # BTB Hit Percentage +system.cpu.branch_predictor.BTBHitPct 26.475548 # BTB Hit Percentage system.cpu.branch_predictor.predictedTaken 464 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 1144 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5213 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedNotTaken 1143 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5212 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 4580 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9793 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9792 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 2970 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 2971 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 2183 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 284 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 367 # Number of Branches Incorrectly Predicted As Not Taken). @@ -90,12 +90,12 @@ system.cpu.execution_unit.executions 4474 # Nu system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 11434 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 12078 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 443 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35079 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 7391 # Number of cycles cpu stages are processed. -system.cpu.activity 17.402873 # Percentage of cycles cpu is active +system.cpu.timesIdled 536 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 36557 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 7415 # Number of cycles cpu stages are processed. +system.cpu.activity 16.863004 # Percentage of cycles cpu is active system.cpu.comLoads 1185 # Number of Load instructions committed system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comBranches 1051 # Number of Branches instructions committed @@ -107,72 +107,72 @@ system.cpu.committedInsts 6404 # Nu system.cpu.committedOps 6404 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 6404 # Number of Instructions committed (Total) -system.cpu.cpi 6.631793 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.866334 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.631793 # CPI: Total CPI of All Threads -system.cpu.ipc 0.150789 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.866334 # CPI: Total CPI of All Threads +system.cpu.ipc 0.145638 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.150789 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 37550 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4920 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 11.584648 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 38585 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3885 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 9.147634 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 38290 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 4180 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 9.842242 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 41130 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 1340 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.155168 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 38002 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 4468 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 10.520367 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.145638 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 39051 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4921 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 11.191213 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 40084 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3888 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 8.841990 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 39791 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 4181 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 9.508323 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 42630 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 1342 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 3.051942 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 39502 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 4470 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 10.165560 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 138.955928 # Cycle average of tags in use -system.cpu.icache.total_refs 558 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 138.644500 # Cycle average of tags in use +system.cpu.icache.total_refs 557 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.853821 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.850498 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 138.955928 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.067850 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.067850 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 558 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 558 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 558 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 558 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 558 # number of overall hits -system.cpu.icache.overall_hits::total 558 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses -system.cpu.icache.overall_misses::total 350 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19343500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19343500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19343500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19343500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19343500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19343500 # number of overall miss cycles +system.cpu.icache.occ_blocks::cpu.inst 138.644500 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.067698 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.067698 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 557 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 557 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 557 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 557 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 557 # number of overall hits +system.cpu.icache.overall_hits::total 557 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 351 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 351 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 351 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 351 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 351 # number of overall misses +system.cpu.icache.overall_misses::total 351 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19781500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19781500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19781500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19781500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19781500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19781500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 908 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 908 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 908 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 908 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 908 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.385463 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.385463 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.385463 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.385463 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.385463 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.385463 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55267.142857 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55267.142857 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55267.142857 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55267.142857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55267.142857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55267.142857 # average overall miss latency +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.386564 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.386564 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.386564 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.386564 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.386564 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.386564 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56357.549858 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56357.549858 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56357.549858 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56357.549858 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56357.549858 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56357.549858 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -181,70 +181,70 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 48 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 48 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 48 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 48 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 49 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 49 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 49 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 49 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 49 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16051500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16051500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16051500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16051500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16051500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16051500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16493500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16493500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16493500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16493500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16493500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16493500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.332599 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.332599 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.332599 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53150.662252 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53150.662252 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53150.662252 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53150.662252 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53150.662252 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53150.662252 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54614.238411 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54614.238411 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54614.238411 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54614.238411 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54614.238411 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54614.238411 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 102.711534 # Cycle average of tags in use -system.cpu.dcache.total_refs 1703 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 102.468585 # Cycle average of tags in use +system.cpu.dcache.total_refs 1702 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 10.136905 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 10.130952 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 102.711534 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025076 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025076 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 102.468585 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025017 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025017 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 615 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 615 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1703 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1703 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1703 # number of overall hits -system.cpu.dcache.overall_hits::total 1703 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 614 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 614 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1702 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1702 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1702 # number of overall hits +system.cpu.dcache.overall_hits::total 1702 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 347 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 347 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 347 # number of overall misses -system.cpu.dcache.overall_misses::total 347 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5507500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5507500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 13555000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 13555000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19062500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19062500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19062500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19062500 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 251 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 251 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 348 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 348 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 348 # number of overall misses +system.cpu.dcache.overall_misses::total 348 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5918000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5918000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 15290000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15290000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 21208000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 21208000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 21208000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 21208000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -255,36 +255,36 @@ system.cpu.dcache.overall_accesses::cpu.data 2050 system.cpu.dcache.overall_accesses::total 2050 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081857 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.081857 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289017 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289017 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.169268 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.169268 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.169268 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.169268 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56778.350515 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56778.350515 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54220 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54220 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54935.158501 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54935.158501 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54935.158501 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54935.158501 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.290173 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.290173 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.169756 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.169756 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.169756 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.169756 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61010.309278 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61010.309278 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60916.334661 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60916.334661 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60942.528736 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60942.528736 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60942.528736 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60942.528736 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1656000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1689000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 36 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 37 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 46000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 45648.648649 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 177 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 177 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 179 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 179 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 179 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 179 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 178 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 178 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 180 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 180 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 180 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 180 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses @@ -293,14 +293,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5113000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5113000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3909500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3909500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9022500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9022500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9022500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9022500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5509500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5509500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4096500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4096500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9606000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9606000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9606000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9606000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -309,26 +309,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 system.cpu.dcache.demand_mshr_miss_rate::total 0.081951 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.081951 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53821.052632 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53821.052632 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53554.794521 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53554.794521 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53705.357143 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53705.357143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53705.357143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53705.357143 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57994.736842 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57994.736842 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56116.438356 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56116.438356 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57178.571429 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 57178.571429 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57178.571429 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 57178.571429 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 195.300582 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 194.857279 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 139.031748 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.268833 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004243 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001717 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005960 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 138.715070 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.142209 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004233 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001713 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005947 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -346,17 +346,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15708000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4994000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 20702000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3821500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3821500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15708000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8815500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 24523500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15708000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8815500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 24523500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16152000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5390000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 21542000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4007500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4007500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16152000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9397500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 25549500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16152000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9397500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 25549500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -379,17 +379,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52186.046512 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52568.421053 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52277.777778 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52349.315068 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52349.315068 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52186.046512 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52473.214286 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52288.912580 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52186.046512 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52473.214286 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52288.912580 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53661.129568 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56736.842105 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 54398.989899 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54897.260274 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54897.260274 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53661.129568 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55937.500000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 54476.545842 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53661.129568 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55937.500000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 54476.545842 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -409,17 +409,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12038500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3838000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15876500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2942500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2942500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12038500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6780500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18819000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12038500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6780500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18819000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12487000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4239000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16726000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3129500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3129500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12487000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7368500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19855500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12487000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7368500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19855500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses @@ -431,17 +431,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39995.016611 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40400 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40092.171717 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40308.219178 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40308.219178 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39995.016611 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40360.119048 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40125.799574 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39995.016611 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40360.119048 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40125.799574 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41485.049834 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44621.052632 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42237.373737 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42869.863014 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42869.863014 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41485.049834 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43860.119048 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42335.820896 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41485.049834 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43860.119048 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42335.820896 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |