diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/tru64/simple-timing')
3 files changed, 36 insertions, 36 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini index 3d54d7382..b94afa836 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -148,7 +148,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -180,7 +180,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout index 803a08b4e..95893429b 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:39:41 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 09:08:33 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 16769000 because target called exit() +Exiting @ tick 17541000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index fab613981..aabb78aae 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 16769000 # Number of ticks simulated -final_tick 16769000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000018 # Number of seconds simulated +sim_ticks 17541000 # Number of ticks simulated +final_tick 17541000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 308591 # Simulator instruction rate (inst/s) -host_op_rate 307918 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1999557615 # Simulator tick rate (ticks/s) -host_mem_usage 213304 # Number of bytes of host memory used +host_inst_rate 207586 # Simulator instruction rate (inst/s) +host_op_rate 207300 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1409208031 # Simulator tick rate (ticks/s) +host_mem_usage 216876 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 10432 # Nu system.physmem.num_reads::cpu.inst 163 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 82 # Number of read requests responded to by this memory system.physmem.num_reads::total 245 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 622100304 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 312958435 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 935058739 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 622100304 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 622100304 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 622100304 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 312958435 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 935058739 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 594720940 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 299184767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 893905707 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 594720940 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 594720940 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 594720940 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 299184767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 893905707 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 33538 # number of cpu cycles simulated +system.cpu.numCycles 35082 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2577 # Number of instructions committed @@ -79,18 +79,18 @@ system.cpu.num_mem_refs 717 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_store_insts 298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 33538 # Number of busy cycles +system.cpu.num_busy_cycles 35082 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 80.003762 # Cycle average of tags in use +system.cpu.icache.tagsinuse 80.027768 # Cycle average of tags in use system.cpu.icache.total_refs 2423 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 14.865031 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 80.003762 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.039064 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.039064 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 80.027768 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.039076 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.039076 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 2423 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2423 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2423 # number of demand (read+write) hits @@ -161,14 +161,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 47.418751 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 47.439715 # Cycle average of tags in use system.cpu.dcache.total_refs 627 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 47.418751 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.011577 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.011577 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 47.439715 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.011582 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.011582 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits @@ -259,16 +259,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 107.101205 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 107.121835 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 218 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 80.120406 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 26.980800 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.002445 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 80.139278 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 26.982557 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.002446 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000823 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.003268 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.003269 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 218 # number of ReadReq misses |