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-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini4
-rwxr-xr-xtests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout8
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt462
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini4
-rwxr-xr-xtests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout8
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt64
6 files changed, 275 insertions, 275 deletions
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
index d62e06b17..dd53d4220 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
@@ -181,7 +181,7 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
-width=64
+width=8
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@@ -213,7 +213,7 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
-width=64
+width=8
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
index 76c88733e..a234b881d 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 4 2012 12:01:47
-gem5 started Jun 4 2012 14:44:31
+gem5 compiled Jul 2 2012 08:54:18
+gem5 started Jul 2 2012 11:30:03
gem5 executing on zizzer
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
-Hello World!Exiting @ tick 18196500 because target called exit()
+Hello World!Exiting @ tick 18885500 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
index b45b5b881..fa8b51b5a 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000018 # Number of seconds simulated
-sim_ticks 18196500 # Number of ticks simulated
-final_tick 18196500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000019 # Number of seconds simulated
+sim_ticks 18885500 # Number of ticks simulated
+final_tick 18885500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 58781 # Simulator instruction rate (inst/s)
-host_op_rate 58769 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 200221364 # Simulator tick rate (ticks/s)
-host_mem_usage 221628 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
+host_inst_rate 37135 # Simulator instruction rate (inst/s)
+host_op_rate 37131 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 131302803 # Simulator tick rate (ticks/s)
+host_mem_usage 220012 # Number of bytes of host memory used
+host_seconds 0.14 # Real time elapsed on the host
sim_insts 5340 # Number of instructions simulated
sim_ops 5340 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory
@@ -19,28 +19,28 @@ system.physmem.bytes_inst_read::total 18496 # Nu
system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
system.physmem.num_reads::total 423 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1016459209 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 471299426 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1487758635 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1016459209 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1016459209 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1016459209 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 471299426 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1487758635 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 979375712 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 454105001 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1433480713 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 979375712 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 979375712 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 979375712 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 454105001 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1433480713 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 11 # Number of system calls
-system.cpu.numCycles 36394 # number of cpu cycles simulated
+system.cpu.numCycles 37772 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 1617 # Number of BP lookups
+system.cpu.branch_predictor.lookups 1615 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 1022 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 899 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 1172 # Number of BTB lookups
+system.cpu.branch_predictor.BTBLookups 1170 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 435 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 37.116041 # BTB Hit Percentage
+system.cpu.branch_predictor.BTBHitPct 37.179487 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken 1115 # Number of Branches Predicted As Not Taken (False).
+system.cpu.branch_predictor.predictedNotTaken 1113 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 5634 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 4000 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 9634 # Total Accesses (Read+Write) to the Int. Register File
@@ -58,12 +58,12 @@ system.cpu.execution_unit.executions 3979 # Nu
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 9708 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 10178 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 421 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 30167 # Number of cycles cpu's stages were not processed
-system.cpu.runCycles 6227 # Number of cycles cpu stages are processed.
-system.cpu.activity 17.109963 # Percentage of cycles cpu is active
+system.cpu.timesIdled 501 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 31527 # Number of cycles cpu's stages were not processed
+system.cpu.runCycles 6245 # Number of cycles cpu stages are processed.
+system.cpu.activity 16.533411 # Percentage of cycles cpu is active
system.cpu.comLoads 716 # Number of Load instructions committed
system.cpu.comStores 673 # Number of Store instructions committed
system.cpu.comBranches 1116 # Number of Branches instructions committed
@@ -75,72 +75,72 @@ system.cpu.committedInsts 5340 # Nu
system.cpu.committedOps 5340 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 5340 # Number of Instructions committed (Total)
-system.cpu.cpi 6.815356 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi 7.073408 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
-system.cpu.cpi_total 6.815356 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.146727 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total 7.073408 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.141375 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
-system.cpu.ipc_total 0.146727 # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles 31821 # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles 4573 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 12.565258 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 33191 # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles 3203 # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization 8.800901 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 33344 # Number of cycles 0 instructions are processed.
+system.cpu.ipc_total 0.141375 # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles 33203 # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles 4569 # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization 12.096262 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 34575 # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles 3197 # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization 8.463942 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles 34722 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 3050 # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 8.380502 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles 35411 # Number of cycles 0 instructions are processed.
+system.cpu.stage2.utilization 8.074764 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles 36789 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 983 # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization 2.700995 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 33220 # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles 3174 # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization 8.721218 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.utilization 2.602457 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles 34600 # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles 3172 # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization 8.397755 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.tagsinuse 136.672418 # Cycle average of tags in use
-system.cpu.icache.total_refs 827 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 136.494329 # Cycle average of tags in use
+system.cpu.icache.total_refs 825 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 2.841924 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 2.835052 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 136.672418 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.066735 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.066735 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 827 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 827 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 827 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 827 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 827 # number of overall hits
-system.cpu.icache.overall_hits::total 827 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 347 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 347 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 347 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 347 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 347 # number of overall misses
-system.cpu.icache.overall_misses::total 347 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 19107000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 19107000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 19107000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 19107000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 19107000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 19107000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 1174 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 1174 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 1174 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 1174 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 1174 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 1174 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.295571 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.295571 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.295571 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.295571 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.295571 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.295571 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55063.400576 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 55063.400576 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 55063.400576 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 55063.400576 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 55063.400576 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 55063.400576 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 136.494329 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.066648 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.066648 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 825 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 825 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 825 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 825 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 825 # number of overall hits
+system.cpu.icache.overall_hits::total 825 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses
+system.cpu.icache.overall_misses::total 350 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 19647000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 19647000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 19647000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 19647000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 19647000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 19647000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 1175 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 1175 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 1175 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 1175 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1175 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1175 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.297872 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.297872 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.297872 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.297872 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.297872 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.297872 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56134.285714 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 56134.285714 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 56134.285714 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 56134.285714 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 56134.285714 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 56134.285714 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 106000 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -149,70 +149,70 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets 35333.333333 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 56 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 56 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 56 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 56 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 59 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 59 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 59 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 59 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 59 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15468000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 15468000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15468000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 15468000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15468000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 15468000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.247871 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.247871 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.247871 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.247871 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.247871 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.247871 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53154.639175 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53154.639175 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53154.639175 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 53154.639175 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53154.639175 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 53154.639175 # average overall mshr miss latency
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@@ -221,38 +221,38 @@ system.cpu.dcache.demand_accesses::cpu.data 1389 #
system.cpu.dcache.demand_accesses::total 1389 # number of demand (read+write) accesses
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
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@@ -261,14 +261,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135
system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
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@@ -277,26 +277,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097192
system.cpu.dcache.demand_mshr_miss_rate::total 0.097192 # mshr miss rate for demand accesses
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system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks.
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@@ -317,17 +317,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu
system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses
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@@ -350,17 +350,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 #
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+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56330.188679 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 54507.309942 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54746.913580 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54746.913580 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54173.010381 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55373.134328 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 54553.191489 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54173.010381 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55373.134328 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 54553.191489 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -380,17 +380,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423
system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11603500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2143500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13747000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3255500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3255500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11603500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5399000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 17002500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11603500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5399000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 17002500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12139500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2343500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14483000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3454500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3454500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12139500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5798000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 17937500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12139500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5798000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 17937500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses
@@ -402,17 +402,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40150.519031 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40443.396226 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40195.906433 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40191.358025 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40191.358025 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40150.519031 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40291.044776 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40195.035461 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40150.519031 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40291.044776 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40195.035461 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42005.190311 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44216.981132 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42347.953216 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42648.148148 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42648.148148 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42005.190311 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43268.656716 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42405.437352 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42005.190311 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43268.656716 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42405.437352 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
index 232d3350e..53f402a63 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
@@ -148,7 +148,7 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
-width=64
+width=8
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@@ -180,7 +180,7 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
-width=64
+width=8
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
index e4af58bc7..81bff15c4 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 4 2012 12:01:47
-gem5 started Jun 4 2012 14:44:42
+gem5 compiled Jul 2 2012 08:54:18
+gem5 started Jul 2 2012 11:30:26
gem5 executing on zizzer
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
-Hello World!Exiting @ tick 28206000 because target called exit()
+Hello World!Exiting @ tick 29541000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
index 3580b75db..d0e2c9d97 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000028 # Number of seconds simulated
-sim_ticks 28206000 # Number of ticks simulated
-final_tick 28206000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000030 # Number of seconds simulated
+sim_ticks 29541000 # Number of ticks simulated
+final_tick 29541000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 427855 # Simulator instruction rate (inst/s)
-host_op_rate 427237 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2253599179 # Simulator tick rate (ticks/s)
-host_mem_usage 221156 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
+host_inst_rate 73924 # Simulator instruction rate (inst/s)
+host_op_rate 73907 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 408761366 # Simulator tick rate (ticks/s)
+host_mem_usage 220016 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
sim_insts 5340 # Number of instructions simulated
sim_ops 5340 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory
@@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 16320 # Nu
system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
system.physmem.num_reads::total 389 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 578600298 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 304048784 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 882649082 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 578600298 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 578600298 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 578600298 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 304048784 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 882649082 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 552452524 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 290308385 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 842760909 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 552452524 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 552452524 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 552452524 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 290308385 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 842760909 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 11 # Number of system calls
-system.cpu.numCycles 56412 # number of cpu cycles simulated
+system.cpu.numCycles 59082 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 5340 # Number of instructions committed
@@ -47,18 +47,18 @@ system.cpu.num_mem_refs 1402 # nu
system.cpu.num_load_insts 724 # Number of load instructions
system.cpu.num_store_insts 678 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 56412 # Number of busy cycles
+system.cpu.num_busy_cycles 59082 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.tagsinuse 116.975932 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 117.079183 # Cycle average of tags in use
system.cpu.icache.total_refs 5127 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 19.949416 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 116.975932 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.057117 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.057117 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst 117.079183 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.057168 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.057168 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 5127 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 5127 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 5127 # number of demand (read+write) hits
@@ -129,14 +129,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751
system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 82.065697 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 82.107175 # Cycle average of tags in use
system.cpu.dcache.total_refs 1254 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 9.288889 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 82.065697 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.020036 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.020036 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data 82.107175 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.020046 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.020046 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 662 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 662 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits
@@ -227,16 +227,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 142.102892 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 142.223187 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 308 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.009740 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst 116.450335 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 25.652557 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst 0.003554 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.004337 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst 116.548564 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 25.674623 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst 0.003557 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.000784 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.004340 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits