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-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt389
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt283
2 files changed, 341 insertions, 331 deletions
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
index 951c5abaa..33e0e9c43 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu
sim_ticks 20927500 # Number of ticks simulated
final_tick 20927500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 61359 # Simulator instruction rate (inst/s)
-host_op_rate 61351 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 240990471 # Simulator tick rate (ticks/s)
-host_mem_usage 234980 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
+host_inst_rate 82286 # Simulator instruction rate (inst/s)
+host_op_rate 82268 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 323129777 # Simulator tick rate (ticks/s)
+host_mem_usage 289972 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -220,53 +220,34 @@ system.physmem.readRowHitRate 80.14 # Ro
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 49309.69 # Average gap between requests
system.physmem.pageHitRate 80.14 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 13500 # Time in different power states
-system.physmem.memoryStateTime::REF 520000 # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 15312750 # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem.actEnergy::0 294840 # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1 196560 # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0 160875 # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1 107250 # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0 1497600 # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1 1107600 # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0 10702035 # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1 10576350 # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0 111750 # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1 222000 # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0 13784220 # Total energy per rank (pJ)
-system.physmem.totalEnergy::1 13226880 # Total energy per rank (pJ)
-system.physmem.averagePower::0 870.628138 # Core power per rank (mW)
-system.physmem.averagePower::1 835.425865 # Core power per rank (mW)
-system.membus.trans_dist::ReadReq 342 # Transaction distribution
-system.membus.trans_dist::ReadResp 342 # Transaction distribution
-system.membus.trans_dist::ReadExReq 81 # Transaction distribution
-system.membus.trans_dist::ReadExResp 81 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 846 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 846 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27072 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 27072 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 423 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 423 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 423 # Request fanout histogram
-system.membus.reqLayer0.occupancy 501500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 2.4 # Layer utilization (%)
-system.membus.respLayer1.occupancy 3931250 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 18.8 # Layer utilization (%)
-system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 1497600 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 10702035 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 111750 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 13784220 # Total energy per rank (pJ)
+system.physmem_0.averagePower 870.628138 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 116500 # Time in different power states
+system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 15209750 # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.physmem_1.actEnergy 196560 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 107250 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 1107600 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 10576350 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 222000 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 13226880 # Total energy per rank (pJ)
+system.physmem_1.averagePower 835.425865 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 328000 # Time in different power states
+system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 14998250 # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 1636 # Number of BP lookups
system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 897 # Number of conditional branches incorrect
@@ -276,6 +257,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu
system.cpu.branchPred.BTBHitPct 43.484736 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 41856 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
@@ -337,6 +319,118 @@ system.cpu.stage3.utilization 2.329415 # Pe
system.cpu.stage4.idleCycles 38699 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 7.542527 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.dcache.tags.replacements 0 # number of replacements
+system.cpu.dcache.tags.tagsinuse 85.369863 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 914 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 6.770370 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 85.369863 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.020842 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.020842 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 260 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 914 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 914 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 914 # number of overall hits
+system.cpu.dcache.overall_hits::total 914 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 413 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 413 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses
+system.cpu.dcache.overall_misses::total 474 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 4588750 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 4588750 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 28972250 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 28972250 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 33561000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 33561000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 33561000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 33561000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085315 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.085315 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.613670 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.613670 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75225.409836 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 75225.409836 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70150.726392 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 70150.726392 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 70803.797468 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 70803.797468 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 70803.797468 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 70803.797468 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 818 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 31 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.387097 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 332 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 332 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 339 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 339 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 339 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 339 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4091500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4091500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6091750 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 6091750 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10183250 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 10183250 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10183250 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 10183250 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75768.518519 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75768.518519 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75206.790123 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75206.790123 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75431.481481 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 75431.481481 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75431.481481 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 75431.481481 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 142.708262 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 892 # Total number of references to valid blocks.
@@ -427,34 +521,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 70926.116838
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70926.116838 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 70926.116838 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 345 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 852 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 27264 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 426 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 426 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 426 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 486500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 216750 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 169.161112 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks.
@@ -589,117 +655,56 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57807.958478
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62561.567164 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59313.829787 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 85.369863 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 914 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 6.770370 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 85.369863 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.020842 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.020842 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 260 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 914 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 914 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 914 # number of overall hits
-system.cpu.dcache.overall_hits::total 914 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 413 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 413 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses
-system.cpu.dcache.overall_misses::total 474 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 4588750 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 4588750 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 28972250 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 28972250 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 33561000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 33561000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 33561000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 33561000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085315 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.085315 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.613670 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.613670 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75225.409836 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 75225.409836 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70150.726392 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 70150.726392 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 70803.797468 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 70803.797468 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 70803.797468 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 70803.797468 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 818 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 31 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.387097 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 332 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 332 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 339 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 339 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 339 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 339 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4091500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4091500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6091750 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 6091750 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10183250 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 10183250 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10183250 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 10183250 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75768.518519 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75768.518519 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75206.790123 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75206.790123 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75431.481481 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 75431.481481 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75431.481481 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 75431.481481 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq 345 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 852 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 27264 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 426 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 426 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 426 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 486500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 216750 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
+system.membus.trans_dist::ReadReq 342 # Transaction distribution
+system.membus.trans_dist::ReadResp 342 # Transaction distribution
+system.membus.trans_dist::ReadExReq 81 # Transaction distribution
+system.membus.trans_dist::ReadExResp 81 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 846 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 846 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27072 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 27072 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 423 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 423 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 423 # Request fanout histogram
+system.membus.reqLayer0.occupancy 501500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 2.4 # Layer utilization (%)
+system.membus.respLayer1.occupancy 3931250 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 18.8 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
index 0a40cf084..51b100b5f 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000096 # Number of seconds simulated
-sim_ticks 95992 # Number of ticks simulated
-final_tick 95992 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 95989 # Number of ticks simulated
+final_tick 95989 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 28429 # Simulator instruction rate (inst/s)
-host_op_rate 28426 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 512186 # Simulator tick rate (ticks/s)
-host_mem_usage 435856 # Number of bytes of host memory used
-host_seconds 0.19 # Real time elapsed on the host
+host_inst_rate 73101 # Simulator instruction rate (inst/s)
+host_op_rate 73087 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1316740 # Simulator tick rate (ticks/s)
+host_mem_usage 448980 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -21,12 +21,12 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1289 #
system.mem_ctrls.num_reads::total 1289 # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::ruby.dir_cntrl0 1285 # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total 1285 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 859404950 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 859404950 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 856738062 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 856738062 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 1716143012 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 1716143012 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 859431810 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 859431810 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 856764838 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 856764838 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 1716196648 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 1716196648 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs 1289 # Number of read requests accepted
system.mem_ctrls.writeReqs 1285 # Number of write requests accepted
system.mem_ctrls.readBursts 1289 # Number of DRAM read bursts, including those serviced by the write queue
@@ -73,7 +73,7 @@ system.mem_ctrls.perBankWrBursts::14 18 # Pe
system.mem_ctrls.perBankWrBursts::15 8 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 95928 # Total gap between requests
+system.mem_ctrls.totGap 95925 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
@@ -217,16 +217,16 @@ system.mem_ctrls.wrPerTurnAround::17 1 2.33% 83.72% # Wr
system.mem_ctrls.wrPerTurnAround::18 2 4.65% 88.37% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::19 5 11.63% 100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total 43 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 8746 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 22027 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totQLat 8743 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 22024 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.totBusLat 3495 # Total ticks spent in databus transfers
system.mem_ctrls.avgQLat 12.51 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
system.mem_ctrls.avgMemAccLat 31.51 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 466.04 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 472.04 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 859.40 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 856.74 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBW 466.05 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 472.05 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 859.43 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 856.76 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.mem_ctrls.busUtil 7.33 # Data bus utilization in percentage
system.mem_ctrls.busUtilRead 3.64 # Data bus utilization in percentage for reads
@@ -239,29 +239,94 @@ system.mem_ctrls.readRowHitRate 70.96 # Ro
system.mem_ctrls.writeRowHitRate 92.86 # Row buffer hit rate for writes
system.mem_ctrls.avgGap 37.27 # Average gap between requests
system.mem_ctrls.pageHitRate 82.13 # Row buffer hit rate, read and write combined
-system.mem_ctrls.memoryStateTime::IDLE 3037 # Time in different power states
-system.mem_ctrls.memoryStateTime::REF 3120 # Time in different power states
-system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls.memoryStateTime::ACT 87552 # Time in different power states
-system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.mem_ctrls.actEnergy::0 1035720 # Energy for activate commands per rank (pJ)
-system.mem_ctrls.actEnergy::1 672840 # Energy for activate commands per rank (pJ)
-system.mem_ctrls.preEnergy::0 575400 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls.preEnergy::1 373800 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls.readEnergy::0 5229120 # Energy for read commands per rank (pJ)
-system.mem_ctrls.readEnergy::1 3257280 # Energy for read commands per rank (pJ)
-system.mem_ctrls.writeEnergy::0 4271616 # Energy for write commands per rank (pJ)
-system.mem_ctrls.writeEnergy::1 2716416 # Energy for write commands per rank (pJ)
-system.mem_ctrls.refreshEnergy::0 6102720 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls.refreshEnergy::1 6102720 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls.actBackEnergy::0 59194044 # Energy for active background per rank (pJ)
-system.mem_ctrls.actBackEnergy::1 56254896 # Energy for active background per rank (pJ)
-system.mem_ctrls.preBackEnergy::0 4292400 # Energy for precharge background per rank (pJ)
-system.mem_ctrls.preBackEnergy::1 6870600 # Energy for precharge background per rank (pJ)
-system.mem_ctrls.totalEnergy::0 80701020 # Total energy per rank (pJ)
-system.mem_ctrls.totalEnergy::1 76248552 # Total energy per rank (pJ)
-system.mem_ctrls.averagePower::0 861.316185 # Core power per rank (mW)
-system.mem_ctrls.averagePower::1 813.795315 # Core power per rank (mW)
+system.mem_ctrls_0.actEnergy 1035720 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy 575400 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy 5229120 # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy 4271616 # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy 59194044 # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy 4292400 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy 80701020 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 861.316185 # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE 6799 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF 3120 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT 83841 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.mem_ctrls_1.actEnergy 672840 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy 373800 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy 3257280 # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy 2716416 # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy 56250108 # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy 6873000 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy 76246164 # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower 813.795884 # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE 11133 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF 3120 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT 79453 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.cpu.clk_domain.clock 1 # Clock period in ticks
+system.cpu.workload.num_syscalls 11 # Number of system calls
+system.cpu.numCycles 95989 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.committedInsts 5327 # Number of instructions committed
+system.cpu.committedOps 5327 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
+system.cpu.num_func_calls 146 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls
+system.cpu.num_int_insts 4505 # number of integer instructions
+system.cpu.num_fp_insts 0 # number of float instructions
+system.cpu.num_int_register_reads 10598 # number of times the integer registers were read
+system.cpu.num_int_register_writes 4845 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
+system.cpu.num_mem_refs 1401 # number of memory refs
+system.cpu.num_load_insts 723 # Number of load instructions
+system.cpu.num_store_insts 678 # Number of store instructions
+system.cpu.num_idle_cycles 0.999990 # Number of idle cycles
+system.cpu.num_busy_cycles 95988.000010 # Number of busy cycles
+system.cpu.not_idle_fraction 0.999990 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.000010 # Percentage of idle cycles
+system.cpu.Branches 1121 # Number of branches fetched
+system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction
+system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction
+system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction
+system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 73.91% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 73.91% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 73.91% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 73.91% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 73.91% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 73.91% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction
+system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction
+system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::total 5370 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
@@ -278,9 +343,9 @@ system.ruby.outstanding_req_hist::total 6759
system.ruby.latency_hist::bucket_size 64
system.ruby.latency_hist::max_bucket 639
system.ruby.latency_hist::samples 6758
-system.ruby.latency_hist::mean 13.204202
-system.ruby.latency_hist::gmean 5.149414
-system.ruby.latency_hist::stdev 25.350800
+system.ruby.latency_hist::mean 13.203759
+system.ruby.latency_hist::gmean 5.149407
+system.ruby.latency_hist::stdev 25.345890
system.ruby.latency_hist | 6535 96.70% 96.70% | 182 2.69% 99.39% | 30 0.44% 99.84% | 2 0.03% 99.87% | 8 0.12% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.latency_hist::total 6758
system.ruby.hit_latency_hist::bucket_size 1
@@ -293,18 +358,17 @@ system.ruby.hit_latency_hist::total 5469
system.ruby.miss_latency_hist::bucket_size 64
system.ruby.miss_latency_hist::max_bucket 639
system.ruby.miss_latency_hist::samples 1289
-system.ruby.miss_latency_hist::mean 56.498836
-system.ruby.miss_latency_hist::gmean 50.965885
-system.ruby.miss_latency_hist::stdev 32.457285
+system.ruby.miss_latency_hist::mean 56.496509
+system.ruby.miss_latency_hist::gmean 50.965481
+system.ruby.miss_latency_hist::stdev 32.440273
system.ruby.miss_latency_hist | 1066 82.70% 82.70% | 182 14.12% 96.82% | 30 2.33% 99.15% | 2 0.16% 99.30% | 8 0.62% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist::total 1289
system.ruby.Directory.incomplete_times 1288
-system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
system.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 # Number of cache demand hits
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1289 # Number of cache demand misses
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 6758 # Number of cache demand accesses
-system.cpu.clk_domain.clock 1 # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized 6.703684
+system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
+system.ruby.network.routers0.percent_links_utilized 6.703893
system.ruby.network.routers0.msg_count.Control::2 1289
system.ruby.network.routers0.msg_count.Data::2 1285
system.ruby.network.routers0.msg_count.Response_Data::4 1289
@@ -313,7 +377,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 10312
system.ruby.network.routers0.msg_bytes.Data::2 92520
system.ruby.network.routers0.msg_bytes.Response_Data::4 92808
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10280
-system.ruby.network.routers1.percent_links_utilized 6.703684
+system.ruby.network.routers1.percent_links_utilized 6.703893
system.ruby.network.routers1.msg_count.Control::2 1289
system.ruby.network.routers1.msg_count.Data::2 1285
system.ruby.network.routers1.msg_count.Response_Data::4 1289
@@ -322,7 +386,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 10312
system.ruby.network.routers1.msg_bytes.Data::2 92520
system.ruby.network.routers1.msg_bytes.Response_Data::4 92808
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10280
-system.ruby.network.routers2.percent_links_utilized 6.703684
+system.ruby.network.routers2.percent_links_utilized 6.703893
system.ruby.network.routers2.msg_count.Control::2 1289
system.ruby.network.routers2.msg_count.Data::2 1285
system.ruby.network.routers2.msg_count.Response_Data::4 1289
@@ -339,91 +403,32 @@ system.ruby.network.msg_byte.Control 30936
system.ruby.network.msg_byte.Data 277560
system.ruby.network.msg_byte.Response_Data 278424
system.ruby.network.msg_byte.Writeback_Control 30840
-system.cpu.workload.num_syscalls 11 # Number of system calls
-system.cpu.numCycles 95992 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 5327 # Number of instructions committed
-system.cpu.committedOps 5327 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_func_calls 146 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls
-system.cpu.num_int_insts 4505 # number of integer instructions
-system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 10598 # number of times the integer registers were read
-system.cpu.num_int_register_writes 4845 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 1401 # number of memory refs
-system.cpu.num_load_insts 723 # Number of load instructions
-system.cpu.num_store_insts 678 # Number of store instructions
-system.cpu.num_idle_cycles 0.999990 # Number of idle cycles
-system.cpu.num_busy_cycles 95991.000010 # Number of busy cycles
-system.cpu.not_idle_fraction 0.999990 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.000010 # Percentage of idle cycles
-system.cpu.Branches 1121 # Number of branches fetched
-system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction
-system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction
-system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 73.91% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 73.91% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 73.91% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 73.91% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 73.91% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 73.91% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 73.91% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction
-system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction
-system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 5370 # Class of executed instruction
-system.ruby.network.routers0.throttle0.link_utilization 6.712018
+system.ruby.network.routers0.throttle0.link_utilization 6.712227
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1289
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1285
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 92808
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 10280
-system.ruby.network.routers0.throttle1.link_utilization 6.695350
+system.ruby.network.routers0.throttle1.link_utilization 6.695559
system.ruby.network.routers0.throttle1.msg_count.Control::2 1289
system.ruby.network.routers0.throttle1.msg_count.Data::2 1285
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 10312
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 92520
-system.ruby.network.routers1.throttle0.link_utilization 6.695350
+system.ruby.network.routers1.throttle0.link_utilization 6.695559
system.ruby.network.routers1.throttle0.msg_count.Control::2 1289
system.ruby.network.routers1.throttle0.msg_count.Data::2 1285
system.ruby.network.routers1.throttle0.msg_bytes.Control::2 10312
system.ruby.network.routers1.throttle0.msg_bytes.Data::2 92520
-system.ruby.network.routers1.throttle1.link_utilization 6.712018
+system.ruby.network.routers1.throttle1.link_utilization 6.712227
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1289
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1285
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 92808
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 10280
-system.ruby.network.routers2.throttle0.link_utilization 6.712018
+system.ruby.network.routers2.throttle0.link_utilization 6.712227
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1289
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1285
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 92808
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 10280
-system.ruby.network.routers2.throttle1.link_utilization 6.695350
+system.ruby.network.routers2.throttle1.link_utilization 6.695559
system.ruby.network.routers2.throttle1.msg_count.Control::2 1289
system.ruby.network.routers2.throttle1.msg_count.Data::2 1285
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 10312
@@ -441,9 +446,9 @@ system.ruby.delayVCHist.vnet_2::total 1285 # de
system.ruby.LD.latency_hist::bucket_size 32
system.ruby.LD.latency_hist::max_bucket 319
system.ruby.LD.latency_hist::samples 715
-system.ruby.LD.latency_hist::mean 30.928671
-system.ruby.LD.latency_hist::gmean 13.876476
-system.ruby.LD.latency_hist::stdev 34.808507
+system.ruby.LD.latency_hist::mean 30.924476
+system.ruby.LD.latency_hist::gmean 13.876278
+system.ruby.LD.latency_hist::stdev 34.776798
system.ruby.LD.latency_hist | 320 44.76% 44.76% | 330 46.15% 90.91% | 50 6.99% 97.90% | 2 0.28% 98.18% | 3 0.42% 98.60% | 6 0.84% 99.44% | 1 0.14% 99.58% | 0 0.00% 99.58% | 2 0.28% 99.86% | 1 0.14% 100.00%
system.ruby.LD.latency_hist::total 715
system.ruby.LD.hit_latency_hist::bucket_size 1
@@ -456,9 +461,9 @@ system.ruby.LD.hit_latency_hist::total 320
system.ruby.LD.miss_latency_hist::bucket_size 32
system.ruby.LD.miss_latency_hist::max_bucket 319
system.ruby.LD.miss_latency_hist::samples 395
-system.ruby.LD.miss_latency_hist::mean 53.554430
-system.ruby.LD.miss_latency_hist::gmean 47.988958
-system.ruby.LD.miss_latency_hist::stdev 32.387704
+system.ruby.LD.miss_latency_hist::mean 53.546835
+system.ruby.LD.miss_latency_hist::gmean 47.987716
+system.ruby.LD.miss_latency_hist::stdev 32.331244
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 330 83.54% 83.54% | 50 12.66% 96.20% | 2 0.51% 96.71% | 3 0.76% 97.47% | 6 1.52% 98.99% | 1 0.25% 99.24% | 0 0.00% 99.24% | 2 0.51% 99.75% | 1 0.25% 100.00%
system.ruby.LD.miss_latency_hist::total 395
system.ruby.ST.latency_hist::bucket_size 32
@@ -510,9 +515,9 @@ system.ruby.IFETCH.miss_latency_hist::total 715
system.ruby.Directory.miss_mach_latency_hist::bucket_size 64
system.ruby.Directory.miss_mach_latency_hist::max_bucket 639
system.ruby.Directory.miss_mach_latency_hist::samples 1289
-system.ruby.Directory.miss_mach_latency_hist::mean 56.498836
-system.ruby.Directory.miss_mach_latency_hist::gmean 50.965885
-system.ruby.Directory.miss_mach_latency_hist::stdev 32.457285
+system.ruby.Directory.miss_mach_latency_hist::mean 56.496509
+system.ruby.Directory.miss_mach_latency_hist::gmean 50.965481
+system.ruby.Directory.miss_mach_latency_hist::stdev 32.440273
system.ruby.Directory.miss_mach_latency_hist | 1066 82.70% 82.70% | 182 14.12% 96.82% | 30 2.33% 99.15% | 2 0.16% 99.30% | 8 0.62% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_mach_latency_hist::total 1289
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1
@@ -544,9 +549,9 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::total
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319
system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 395
-system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 53.554430
-system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 47.988958
-system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 32.387704
+system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 53.546835
+system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 47.987716
+system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 32.331244
system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 330 83.54% 83.54% | 50 12.66% 96.20% | 2 0.51% 96.71% | 3 0.76% 97.47% | 6 1.52% 98.99% | 1 0.25% 99.24% | 0 0.00% 99.24% | 2 0.51% 99.75% | 1 0.25% 100.00%
system.ruby.LD.Directory.miss_type_mach_latency_hist::total 395
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 32
@@ -565,6 +570,14 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 51.762329
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 34.218674
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 591 82.66% 82.66% | 101 14.13% 96.78% | 16 2.24% 99.02% | 1 0.14% 99.16% | 5 0.70% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 715
+system.ruby.Directory_Controller.GETX 1289 0.00% 0.00%
+system.ruby.Directory_Controller.PUTX 1285 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Data 1289 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Ack 1285 0.00% 0.00%
+system.ruby.Directory_Controller.I.GETX 1289 0.00% 0.00%
+system.ruby.Directory_Controller.M.PUTX 1285 0.00% 0.00%
+system.ruby.Directory_Controller.IM.Memory_Data 1289 0.00% 0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack 1285 0.00% 0.00%
system.ruby.L1Cache_Controller.Load 715 0.00% 0.00%
system.ruby.L1Cache_Controller.Ifetch 5370 0.00% 0.00%
system.ruby.L1Cache_Controller.Store 673 0.00% 0.00%
@@ -581,13 +594,5 @@ system.ruby.L1Cache_Controller.M.Replacement 1285 0.00% 0.00%
system.ruby.L1Cache_Controller.MI.Writeback_Ack 1285 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Data 1110 0.00% 0.00%
system.ruby.L1Cache_Controller.IM.Data 179 0.00% 0.00%
-system.ruby.Directory_Controller.GETX 1289 0.00% 0.00%
-system.ruby.Directory_Controller.PUTX 1285 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 1289 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Ack 1285 0.00% 0.00%
-system.ruby.Directory_Controller.I.GETX 1289 0.00% 0.00%
-system.ruby.Directory_Controller.M.PUTX 1285 0.00% 0.00%
-system.ruby.Directory_Controller.IM.Memory_Data 1289 0.00% 0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack 1285 0.00% 0.00%
---------- End Simulation Statistics ----------