diff options
Diffstat (limited to 'tests/quick/se/02.insttest/ref/riscv/linux-rv64d')
25 files changed, 5837 insertions, 2124 deletions
diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.ini index 91d76ecd0..69960a800 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.ini @@ -116,9 +116,11 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system threadPolicy=RoundRobin tracer=system.cpu.tracer +wait_for_remote_gdb=false workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side @@ -745,7 +747,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=insttest cwd= drivers= @@ -754,14 +756,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.json index e97e6327e..f3a80b0d1 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.json +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.json @@ -297,6 +297,7 @@ "max_loads_all_threads": 0, "executeMemoryIssueLimit": 1, "decodeCycleInput": true, + "syscallRetryLatency": 10000, "max_loads_any_thread": 0, "executeLSQTransfersQueueSize": 2, "p_state_clk_gate_max": 1000000000000, @@ -1058,21 +1059,22 @@ "uid": 100, "pid": 100, "kvmInSE": false, - "cxx_class": "LiveProcess", - "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest", + "cxx_class": "Process", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest", "drivers": [], "system": "system", "gid": 100, "eventq_index": 0, "env": [], - "input": "cin", - "ppid": 99, - "type": "LiveProcess", + "maxStackSize": 67108864, + "ppid": 0, + "type": "Process", "cwd": "", + "pgid": 100, "simpoint": 0, "euid": 100, + "input": "cin", "path": "system.cpu.workload", - "max_stack_size": 67108864, "name": "workload", "cmd": [ "insttest" @@ -1084,6 +1086,7 @@ } ], "name": "cpu", + "wait_for_remote_gdb": false, "dtb": { "name": "dtb", "eventq_index": 0, diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simerr index 85a6a33ad..4a90578af 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simerr +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simerr @@ -1,4 +1,6 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Unknown operating system; assuming Linux. warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings. + Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest' +info: Increasing stack size by one page. diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simout index fa339d512..46beb4178 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simout +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simout @@ -3,14 +3,12 @@ Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv6 gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 30 2016 14:33:35 -gem5 started Nov 30 2016 16:18:31 -gem5 executing on zizzer, pid 34070 -command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/minor-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/minor-timing +gem5 compiled Jul 13 2017 17:09:45 +gem5 started Jul 13 2017 17:09:50 +gem5 executing on boldrock, pid 1350 +command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/minor-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/minor-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. fld: PASS fsd: PASS fmadd.d: PASS @@ -165,4 +163,62 @@ fcvt.w.d, truncate negative: PASS fcvt.w.d, 0.0: PASS fcvt.w.d, -0.0: PASS fcvt.w.d, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) -Exiting @ tick 339160000 because target called exit() +fcvt.w.d, underflow: PASS +fcvt.w.d, infinity: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +fcvt.w.d, -infinity: PASS +fcvt.w.d, quiet NaN: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +fcvt.w.d, quiet -NaN: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +fcvt.w.d, signaling NaN: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +fcvt.wu.d, truncate positive: PASS +fcvt.wu.d, truncate negative: PASS +fcvt.wu.d, 0.0: PASS +fcvt.wu.d, -0.0: PASS +fcvt.wu.d, overflow: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.d, underflow: PASS +fcvt.wu.d, infinity: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.d, -infinity: PASS +fcvt.wu.d, quiet NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.d, quiet -NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.d, signaling NaN: PASS +fcvt.d.w, 0: PASS +fcvt.d.w, negative: PASS +fcvt.d.w, truncate: PASS +fcvt.d.wu, 0: PASS +fcvt.d.wu: PASS +fcvt.d.wu, truncate: PASS +fcvt.l.d, truncate positive: PASS +fcvt.l.d, truncate negative: PASS +fcvt.l.d, 0.0: PASS +fcvt.l.d, -0.0: PASS +fcvt.l.d, 32-bit overflow: PASS +fcvt.l.d, overflow: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.l.d, underflow: PASS +fcvt.l.d, infinity: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.l.d, -infinity: PASS +fcvt.l.d, quiet NaN: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.l.d, quiet -NaN: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.l.d, signaling NaN: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.lu.d, truncate positive: PASS +fcvt.lu.d, truncate negative: PASS +fcvt.lu.d, 0.0: PASS +fcvt.lu.d, -0.0: PASS +fcvt.lu.d, 32-bit overflow: PASS +fcvt.lu.d, overflow: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.lu.d, underflow: PASS +fcvt.lu.d, infinity: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.lu.d, -infinity: PASS +fcvt.lu.d, quiet NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 9223372036854775808) +fcvt.lu.d, quiet -NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 9223372036854775808) +fcvt.lu.d, signaling NaN: PASS +fmv.x.d, positive: PASS +fmv.x.d, negative: PASS +fmv.x.d, 0.0: PASS +fmv.x.d, -0.0: PASS +fcvt.d.l, 0: PASS +fcvt.d.l, negative: PASS +fcvt.d.l, 32-bit truncate: PASS +fcvt.d.lu, 0: PASS +fcvt.d.lu: PASS +fcvt.d.lu, 32-bit truncate: PASS +fmv.d.x: PASS +Exiting @ tick 432134500 because exiting with last active thread context diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt index 3ac8f22bf..88923d3c0 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt @@ -1,763 +1,796 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000339 # Number of seconds simulated -sim_ticks 339173000 # Number of ticks simulated -final_tick 339173000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 215547 # Simulator instruction rate (inst/s) -host_op_rate 215545 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 244214530 # Simulator tick rate (ticks/s) -host_mem_usage 263004 # Number of bytes of host memory used -host_seconds 1.39 # Real time elapsed on the host -sim_insts 299354 # Number of instructions simulated -sim_ops 299354 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 74688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 20352 # Number of bytes read from this memory -system.physmem.bytes_read::total 95040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 74688 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 74688 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 1167 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 318 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1485 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 220206207 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 60004776 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 280210984 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 220206207 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 220206207 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 220206207 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 60004776 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 280210984 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1485 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 1485 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 95040 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 95040 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 175 # Per bank write bursts -system.physmem.perBankRdBursts::1 68 # Per bank write bursts -system.physmem.perBankRdBursts::2 18 # Per bank write bursts -system.physmem.perBankRdBursts::3 72 # Per bank write bursts -system.physmem.perBankRdBursts::4 169 # Per bank write bursts -system.physmem.perBankRdBursts::5 291 # Per bank write bursts -system.physmem.perBankRdBursts::6 95 # Per bank write bursts -system.physmem.perBankRdBursts::7 4 # Per bank write bursts -system.physmem.perBankRdBursts::8 9 # Per bank write bursts -system.physmem.perBankRdBursts::9 115 # Per bank write bursts -system.physmem.perBankRdBursts::10 155 # Per bank write bursts -system.physmem.perBankRdBursts::11 169 # Per bank write bursts -system.physmem.perBankRdBursts::12 48 # Per bank write bursts -system.physmem.perBankRdBursts::13 55 # Per bank write bursts -system.physmem.perBankRdBursts::14 15 # Per bank write bursts -system.physmem.perBankRdBursts::15 27 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 338956500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1485 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1419 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 63 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 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-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 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-system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 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-system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 285 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 327.859649 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 221.082687 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 283.652997 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 68 23.86% 23.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 71 24.91% 48.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 38 13.33% 62.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 36 12.63% 74.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 28 9.82% 84.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 14 4.91% 89.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7 2.46% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 0.70% 92.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21 7.37% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 285 # Bytes accessed per row activation -system.physmem.totQLat 20061750 # Total ticks spent queuing -system.physmem.totMemAccLat 47905500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 7425000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13509.60 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32259.60 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 280.21 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 280.21 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.19 # Data bus utilization in percentage -system.physmem.busUtilRead 2.19 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 1195 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.47 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 228253.54 # Average gap between requests -system.physmem.pageHitRate 80.47 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1106700 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 576840 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6368880 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 27044160.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 16018710 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 699840 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 123298980 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 12114720 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 619740.000000 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 187848570 # Total energy per rank (pJ) -system.physmem_0.averagePower 553.841711 # Core power per rank (mW) -system.physmem_0.totalIdleTime 301380500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 552000 # Time in different power states -system.physmem_0.memoryStateTime::REF 11446000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 280750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 31555500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 24953750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 270385000 # Time in different power states -system.physmem_1.actEnergy 963900 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 504735 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4234020 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 27044160.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 12906510 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 3648480 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 105703080 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 26147040 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 905640.000000 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 182057565 # Total energy per rank (pJ) -system.physmem_1.averagePower 536.767851 # Core power per rank (mW) -system.physmem_1.totalIdleTime 301140750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 8284250 # Time in different power states -system.physmem_1.memoryStateTime::REF 11446000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1471750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 68075000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 18122250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 231773750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 80662 # Number of BP lookups -system.cpu.branchPred.condPredicted 51937 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5790 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 60622 # Number of BTB lookups -system.cpu.branchPred.BTBHits 38260 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 63.112401 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 13147 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 7489 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5658 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 3210 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 162 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 339173000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 678346 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 299354 # Number of instructions committed -system.cpu.committedOps 299354 # Number of ops (including micro ops) committed -system.cpu.discardedOps 13899 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 2.266033 # CPI: cycles per instruction -system.cpu.ipc 0.441300 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 162 0.05% 0.05% # Class of committed instruction -system.cpu.op_class_0::IntAlu 179913 60.10% 60.15% # Class of committed instruction -system.cpu.op_class_0::IntMult 466 0.16% 60.31% # Class of committed instruction -system.cpu.op_class_0::IntDiv 40 0.01% 60.32% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 120 0.04% 60.36% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 157 0.05% 60.42% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 60 0.02% 60.44% # Class of committed instruction -system.cpu.op_class_0::FloatMult 30 0.01% 60.45% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 11 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 5 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.45% # Class of committed instruction -system.cpu.op_class_0::MemRead 69348 23.17% 83.62% # Class of committed instruction -system.cpu.op_class_0::MemWrite 48400 16.17% 99.79% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 495 0.17% 99.95% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 147 0.05% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 299354 # Class of committed instruction -system.cpu.tickCycles 449143 # Number of cycles that the object actually ticked -system.cpu.idleCycles 229203 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 254.242270 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 119892 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 320 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 374.662500 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 254.242270 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.062071 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.062071 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 320 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.078125 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 241126 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 241126 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 71739 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 71739 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 48153 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 48153 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 119892 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 119892 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 119892 # number of overall hits -system.cpu.dcache.overall_hits::total 119892 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 118 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 118 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 393 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 393 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 511 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 511 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 511 # number of overall misses -system.cpu.dcache.overall_misses::total 511 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10980000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10980000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31520500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31520500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 42500500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 42500500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 42500500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 42500500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 71857 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 71857 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 48546 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 48546 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 120403 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 120403 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 120403 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 120403 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001642 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.001642 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008095 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.008095 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.004244 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.004244 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004244 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004244 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 93050.847458 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 93050.847458 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80204.834606 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 80204.834606 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 83171.232877 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 83171.232877 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 83171.232877 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 83171.232877 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 191 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 191 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 191 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 191 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 191 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 191 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 118 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 118 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 202 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 202 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 320 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 320 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 320 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 320 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10862000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10862000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16122000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 16122000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26984000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26984000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26984000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26984000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001642 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001642 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004161 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004161 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002658 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002658 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002658 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002658 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 92050.847458 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 92050.847458 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79811.881188 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79811.881188 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84325 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 84325 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84325 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 84325 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 80 # number of replacements -system.cpu.icache.tags.tagsinuse 641.197715 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 134928 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1178 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 114.539898 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 641.197715 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.313085 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.313085 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1098 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 846 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.536133 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 273390 # Number of tag accesses -system.cpu.icache.tags.data_accesses 273390 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 134928 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 134928 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 134928 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 134928 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 134928 # number of overall hits -system.cpu.icache.overall_hits::total 134928 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1178 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1178 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1178 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1178 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1178 # number of overall misses -system.cpu.icache.overall_misses::total 1178 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 100185000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 100185000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 100185000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 100185000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 100185000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 100185000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 136106 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 136106 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 136106 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 136106 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 136106 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 136106 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008655 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008655 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008655 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008655 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008655 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008655 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 85046.689304 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 85046.689304 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 85046.689304 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 85046.689304 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 85046.689304 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 85046.689304 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 80 # number of writebacks -system.cpu.icache.writebacks::total 80 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1178 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1178 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1178 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1178 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1178 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1178 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 99007000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 99007000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 99007000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 99007000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 99007000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 99007000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008655 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008655 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008655 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.008655 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008655 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.008655 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84046.689304 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84046.689304 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84046.689304 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 84046.689304 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84046.689304 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 84046.689304 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 924.252410 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 93 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1485 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.062626 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 671.453398 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 252.799011 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020491 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.007715 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.028206 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 1485 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1201 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.045319 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 14109 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 14109 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackClean_hits::writebacks 80 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 80 # number of WritebackClean hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 11 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 11 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 2 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 11 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 11 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2 # number of overall hits -system.cpu.l2cache.overall_hits::total 13 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 202 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 202 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1167 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1167 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 116 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 116 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1167 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 318 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1485 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1167 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 318 # number of overall misses -system.cpu.l2cache.overall_misses::total 1485 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15818500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 15818500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 97124500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 97124500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10659000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 10659000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 97124500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 26477500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 123602000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 97124500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 26477500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 123602000 # number of overall miss cycles -system.cpu.l2cache.WritebackClean_accesses::writebacks 80 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 80 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 202 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 202 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1178 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1178 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 118 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 118 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1178 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 320 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1498 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1178 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 320 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1498 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.990662 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.990662 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.983051 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.983051 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.990662 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.993750 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.991322 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990662 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.993750 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.991322 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78309.405941 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78309.405941 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83225.792631 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83225.792631 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91887.931034 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91887.931034 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83225.792631 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83262.578616 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 83233.670034 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83225.792631 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83262.578616 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 83233.670034 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 202 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 202 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1167 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1167 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 116 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 116 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1167 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 318 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1485 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1167 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 318 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1485 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13798500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13798500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 85454500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 85454500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9499000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9499000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85454500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23297500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 108752000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85454500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23297500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 108752000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990662 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.990662 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.983051 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.983051 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990662 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.993750 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.991322 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990662 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993750 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.991322 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68309.405941 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68309.405941 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73225.792631 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73225.792631 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81887.931034 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81887.931034 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73225.792631 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73262.578616 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73233.670034 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73225.792631 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73262.578616 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73233.670034 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1578 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 82 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1296 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 80 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 202 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 202 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1178 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 118 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2436 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 640 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3076 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 80512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 20480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 100992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1498 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001335 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.036527 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1496 99.87% 99.87% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2 0.13% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1498 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 869000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1767000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 480000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 1485 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1283 # Transaction distribution -system.membus.trans_dist::ReadExReq 202 # Transaction distribution -system.membus.trans_dist::ReadExResp 202 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1283 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2970 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2970 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 95040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 95040 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1485 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1485 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1485 # Request fanout histogram -system.membus.reqLayer0.occupancy 1721500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 7876000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.3 # Layer utilization (%) +sim_seconds 0.000432 +sim_ticks 432134500 +final_tick 432134500 +sim_freq 1000000000000 +host_inst_rate 3359 +host_op_rate 3369 +host_tick_rate 3337861 +host_mem_usage 272860 +host_seconds 129.46 +sim_insts 434949 +sim_ops 436252 +system.voltage_domain.voltage 1 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0 +system.physmem.bytesReadSys 119616 +system.physmem.bytesWrittenSys 0 +system.physmem.servicedByWrQ 0 +system.physmem.mergedWrBursts 0 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 257 +system.physmem.perBankRdBursts::1 275 +system.physmem.perBankRdBursts::2 180 +system.physmem.perBankRdBursts::3 185 +system.physmem.perBankRdBursts::4 157 +system.physmem.perBankRdBursts::5 101 +system.physmem.perBankRdBursts::6 126 +system.physmem.perBankRdBursts::7 65 +system.physmem.perBankRdBursts::8 51 +system.physmem.perBankRdBursts::9 72 +system.physmem.perBankRdBursts::10 18 +system.physmem.perBankRdBursts::11 38 +system.physmem.perBankRdBursts::12 89 +system.physmem.perBankRdBursts::13 78 +system.physmem.perBankRdBursts::14 74 +system.physmem.perBankRdBursts::15 103 +system.physmem.perBankWrBursts::0 0 +system.physmem.perBankWrBursts::1 0 +system.physmem.perBankWrBursts::2 0 +system.physmem.perBankWrBursts::3 0 +system.physmem.perBankWrBursts::4 0 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14520.46 +system.physmem.avgBusLat 5000.00 +system.physmem.avgMemAccLat 33270.46 +system.physmem.avgRdBW 276.80 +system.physmem.avgWrBW 0.00 +system.physmem.avgRdBWSys 276.80 +system.physmem.avgWrBWSys 0.00 +system.physmem.peakBW 12800.00 +system.physmem.busUtil 2.16 +system.physmem.busUtilRead 2.16 +system.physmem.busUtilWrite 0.00 +system.physmem.avgRdQLen 1.06 +system.physmem.avgWrQLen 0.00 +system.physmem.readRowHits 1445 +system.physmem.writeRowHits 0 +system.physmem.readRowHitRate 77.31 +system.physmem.writeRowHitRate nan +system.physmem.avgGap 231159.97 +system.physmem.pageHitRate 77.31 +system.physmem_0.actEnergy 2156280 +system.physmem_0.preEnergy 1130910 +system.physmem_0.readEnergy 9610440 +system.physmem_0.writeEnergy 0 +system.physmem_0.refreshEnergy 33805200 +system.physmem_0.actBackEnergy 22735020 +system.physmem_0.preBackEnergy 728640 +system.physmem_0.actPowerDownEnergy 167294430 +system.physmem_0.prePowerDownEnergy 5186400 +system.physmem_0.selfRefreshEnergy 0 +system.physmem_0.totalEnergy 242647320 +system.physmem_0.averagePower 561.508139 +system.physmem_0.totalIdleTime 380124250 +system.physmem_0.memoryStateTime::IDLE 312000 +system.physmem_0.memoryStateTime::REF 14300000 +system.physmem_0.memoryStateTime::SREF 0 +system.physmem_0.memoryStateTime::PRE_PDN 13499750 +system.physmem_0.memoryStateTime::ACT 37116000 +system.physmem_0.memoryStateTime::ACT_PDN 366906750 +system.physmem_1.actEnergy 871080 +system.physmem_1.preEnergy 440220 +system.physmem_1.readEnergy 3734220 +system.physmem_1.writeEnergy 0 +system.physmem_1.refreshEnergy 15366000 +system.physmem_1.actBackEnergy 9609630 +system.physmem_1.preBackEnergy 719520 +system.physmem_1.actPowerDownEnergy 53643840 +system.physmem_1.prePowerDownEnergy 14784960 +system.physmem_1.selfRefreshEnergy 62387520 +system.physmem_1.totalEnergy 161556990 +system.physmem_1.averagePower 373.857683 +system.physmem_1.totalIdleTime 409147000 +system.physmem_1.memoryStateTime::IDLE 1209000 +system.physmem_1.memoryStateTime::REF 6518000 +system.physmem_1.memoryStateTime::SREF 253044500 +system.physmem_1.memoryStateTime::PRE_PDN 38497750 +system.physmem_1.memoryStateTime::ACT 15214500 +system.physmem_1.memoryStateTime::ACT_PDN 117650750 +system.pwrStateResidencyTicks::UNDEFINED 432134500 +system.cpu.branchPred.lookups 119617 +system.cpu.branchPred.condPredicted 84602 +system.cpu.branchPred.condIncorrect 8795 +system.cpu.branchPred.BTBLookups 74150 +system.cpu.branchPred.BTBHits 39240 +system.cpu.branchPred.BTBCorrect 0 +system.cpu.branchPred.BTBHitPct 52.919757 +system.cpu.branchPred.usedRAS 0 +system.cpu.branchPred.RASInCorrect 0 +system.cpu.branchPred.indirectLookups 24116 +system.cpu.branchPred.indirectHits 14470 +system.cpu.branchPred.indirectMisses 9646 +system.cpu.branchPredindirectMispredicted 4958 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_hits 0 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0.03% 59.30% +system.cpu.op_class_0::FloatCmp 170 0.03% 59.34% +system.cpu.op_class_0::FloatCvt 128 0.02% 59.37% +system.cpu.op_class_0::FloatMult 30 0.00% 59.38% +system.cpu.op_class_0::FloatMultAcc 0 0.00% 59.38% +system.cpu.op_class_0::FloatDiv 11 0.00% 59.38% +system.cpu.op_class_0::FloatMisc 0 0.00% 59.38% +system.cpu.op_class_0::FloatSqrt 5 0.00% 59.38% +system.cpu.op_class_0::SimdAdd 0 0.00% 59.38% +system.cpu.op_class_0::SimdAddAcc 0 0.00% 59.38% +system.cpu.op_class_0::SimdAlu 0 0.00% 59.38% +system.cpu.op_class_0::SimdCmp 0 0.00% 59.38% +system.cpu.op_class_0::SimdCvt 0 0.00% 59.38% +system.cpu.op_class_0::SimdMisc 0 0.00% 59.38% +system.cpu.op_class_0::SimdMult 0 0.00% 59.38% +system.cpu.op_class_0::SimdMultAcc 0 0.00% 59.38% +system.cpu.op_class_0::SimdShift 0 0.00% 59.38% +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 59.38% +system.cpu.op_class_0::SimdSqrt 0 0.00% 59.38% +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 59.38% +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 59.38% 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+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2791 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1079 +system.cpu.toL2Bus.pkt_count::total 3870 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92928 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 34560 +system.cpu.toL2Bus.pkt_size::total 127488 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 1878 +system.cpu.toL2Bus.snoop_fanout::mean 0.000532 +system.cpu.toL2Bus.snoop_fanout::stdev 0.023075 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 1877 99.94% 99.94% +system.cpu.toL2Bus.snoop_fanout::1 1 0.05% 99.99% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 99.99% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 99.99% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 1878 +system.cpu.toL2Bus.reqLayer0.occupancy 1111500 +system.cpu.toL2Bus.reqLayer0.utilization 0.2 +system.cpu.toL2Bus.respLayer0.occupancy 2007000 +system.cpu.toL2Bus.respLayer0.utilization 0.4 +system.cpu.toL2Bus.respLayer1.occupancy 808500 +system.cpu.toL2Bus.respLayer1.utilization 0.1 +system.membus.snoop_filter.tot_requests 1869 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 432134500 +system.membus.trans_dist::ReadResp 1641 +system.membus.trans_dist::ReadExReq 228 +system.membus.trans_dist::ReadExResp 228 +system.membus.trans_dist::ReadSharedReq 1641 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3738 +system.membus.pkt_count::total 3738 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 119616 +system.membus.pkt_size::total 119616 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 1869 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev -0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 1869 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 1869 +system.membus.reqLayer0.occupancy 2203500 +system.membus.reqLayer0.utilization 0.5 +system.membus.respLayer1.occupancy 9944750 +system.membus.respLayer1.utilization 2.3 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/config.ini new file mode 100644 index 000000000..0585c188f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/config.ini @@ -0,0 +1,876 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +default_p_state=UNDEFINED +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=0 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatAdd +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatCmp +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatCvt +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 opList3 opList4 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatMult +opLat=4 +pipelined=true + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatDiv +opLat=12 +pipelined=false + +[system.cpu.fuPool.FUList3.opList4] +type=OpDesc +eventq_index=0 +opClass=FloatSqrt +opLat=24 +pipelined=false + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 + +[system.cpu.fuPool.FUList5.opList00] +type=OpDesc +eventq_index=0 +opClass=SimdAdd +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList01] +type=OpDesc +eventq_index=0 +opClass=SimdAddAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList02] +type=OpDesc +eventq_index=0 +opClass=SimdAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList03] +type=OpDesc +eventq_index=0 +opClass=SimdCmp +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList04] +type=OpDesc +eventq_index=0 +opClass=SimdCvt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList05] +type=OpDesc +eventq_index=0 +opClass=SimdMisc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList06] +type=OpDesc +eventq_index=0 +opClass=SimdMult +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList07] +type=OpDesc +eventq_index=0 +opClass=SimdMultAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList08] +type=OpDesc +eventq_index=0 +opClass=SimdShift +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList09] +type=OpDesc +eventq_index=0 +opClass=SimdShiftAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList10] +type=OpDesc +eventq_index=0 +opClass=SimdSqrt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList11] +type=OpDesc +eventq_index=0 +opClass=SimdFloatAdd +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList12] +type=OpDesc +eventq_index=0 +opClass=SimdFloatAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList13] +type=OpDesc +eventq_index=0 +opClass=SimdFloatCmp +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList14] +type=OpDesc +eventq_index=0 +opClass=SimdFloatCvt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList15] +type=OpDesc +eventq_index=0 +opClass=SimdFloatDiv +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList16] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMisc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList17] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMult +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList18] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMultAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList19] +type=OpDesc +eventq_index=0 +opClass=SimdFloatSqrt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 opList1 opList2 opList3 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList1] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList8.opList + +[system.cpu.fuPool.FUList8.opList] +type=OpDesc +eventq_index=0 +opClass=IprAccess +opLat=3 +pipelined=false + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 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"path": "system.cpu.fuPool.FUList5.opList18", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatSqrt", + "opLat": 1, + "name": "opList19", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList19", + "type": "OpDesc" + } + ], + "name": "FUList5", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList5", + "type": "FUDesc" + }, + { + "count": 0, + "opList": [ + { + "opClass": "MemWrite", + "opLat": 1, + "name": "opList0", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList6.opList0", + "type": "OpDesc" + }, + { + "opClass": "FloatMemWrite", + "opLat": 1, + "name": "opList1", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList6.opList1", + "type": "OpDesc" + } + ], + "name": "FUList6", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList6", + "type": "FUDesc" + }, + { + "count": 4, + "opList": [ + { + "opClass": "MemRead", + "opLat": 1, + "name": "opList0", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList0", + "type": "OpDesc" + }, + { + "opClass": "MemWrite", + "opLat": 1, + "name": "opList1", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList1", + "type": "OpDesc" + }, + { + "opClass": "FloatMemRead", + "opLat": 1, + "name": "opList2", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList2", + "type": "OpDesc" + }, + { + "opClass": "FloatMemWrite", + "opLat": 1, + "name": "opList3", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList3", + "type": "OpDesc" + } + ], + "name": "FUList7", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList7", + "type": "FUDesc" + }, + { + "count": 1, + "opList": [ + { + "opClass": "IprAccess", + "opLat": 3, + "name": "opList", + "pipelined": false, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList8.opList", + "type": "OpDesc" + } + ], + "name": "FUList8", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList8", + "type": "FUDesc" + } + ], + "eventq_index": 0, + "cxx_class": "FUPool", + "path": "system.cpu.fuPool", + "type": "FUPool" + }, + "socket_id": 0, + "renameToFetchDelay": 1, + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 131072, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "data_latency": 2, + "tag_latency": 2, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "path": "system.cpu", + "numRobs": 1, + "switched_out": false, + "smtLSQPolicy": "Partitioned", + "fetchBufferSize": 64, + "wait_for_remote_gdb": false, + "cacheStorePorts": 200, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "smtROBThreshold": 100, + "numIQEntries": 64, + "branchPred": { + "numThreads": 1, + "BTBEntries": 4096, + "cxx_class": "TournamentBP", + "indirectPathLength": 3, + "globalCtrBits": 2, + "choicePredictorSize": 8192, + "indirectHashGHR": true, + "eventq_index": 0, + "localHistoryTableSize": 2048, + "type": "TournamentBP", + "indirectSets": 256, + "indirectWays": 2, + "choiceCtrBits": 2, + "useIndirect": true, + "localCtrBits": 2, + "path": "system.cpu.branchPred", + "localPredictorSize": 2048, + "RASSize": 16, + "globalPredictorSize": 8192, + "name": "branchPred", + "indirectHashTargets": true, + "instShiftAmt": 2, + "indirectTagSize": 16, + "BTBTagSize": 16 + }, + "LFSTSize": 1024, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "smtROBPolicy": "Partitioned", + "iewToFetchDelay": 1, + "do_statistics_insts": true, + "dispatchWidth": 8, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "commitToDecodeDelay": 1, + "smtIQPolicy": "Partitioned", + "issueWidth": 8, + "LSQCheckLoads": true, + "commitToRenameDelay": 1, + "system": "system", + "checker": null, + "numPhysFloatRegs": 256, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "type": "DerivO3CPU", + "wbWidth": 8, + "numPhysVecRegs": 256, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "smtCommitPolicy": "RoundRobin", + "issueToExecuteDelay": 1, + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "numROBEntries": 192, + "fetchQueueSize": 32, + "iewToCommitDelay": 1, + "smtNumFetchingThreads": 1, + "forwardComSize": 5, + "do_checkpoint_insts": true, + "cxx_class": "DerivO3CPU", + "commitToIEWDelay": 1, + "commitWidth": 8, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 0, + "renameToIEWDelay": 2, + "p_state_clk_gate_bins": 20, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/simerr new file mode 100755 index 000000000..4a90578af --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/simerr @@ -0,0 +1,6 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Sockets disabled, not accepting gdb connections +info: Entering event queue @ 0. Starting simulation... +warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings. + Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest' +info: Increasing stack size by one page. diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/simout new file mode 100755 index 000000000..303ab5a4c --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/simout @@ -0,0 +1,224 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/o3-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/o3-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jul 13 2017 17:09:45 +gem5 started Jul 13 2017 17:25:07 +gem5 executing on boldrock, pid 6006 +command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/o3-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/o3-timing + +Global frequency set at 1000000000000 ticks per second +fld: PASS +fsd: PASS +fmadd.d: PASS +fmadd.d, quiet NaN: PASS +fmadd.d, signaling NaN: PASS +fmadd.d, infinity: PASS +fmadd.d, -infinity: PASS +fmsub.d: PASS +fmsub.d, quiet NaN: PASS +fmsub.d, signaling NaN: PASS +fmsub.d, infinity: PASS +fmsub.d, -infinity: PASS +fmsub.d, subtract infinity: PASS +fnmsub.d: PASS +fnmsub.d, quiet NaN: PASS +fnmsub.d, signaling NaN: PASS +fnmsub.d, infinity: PASS +fnmsub.d, -infinity: PASS +fnmsub.d, subtract infinity: PASS +fnmadd.d: PASS +fnmadd.d, quiet NaN: PASS +fnmadd.d, signaling NaN: PASS +fnmadd.d, infinity: PASS +fnmadd.d, -infinity: PASS +fadd.d: PASS +fadd.d, quiet NaN: PASS +fadd.d, signaling NaN: PASS +fadd.d, infinity: PASS +fadd.d, -infinity: PASS +fsub.d: PASS +fsub.d, quiet NaN: PASS +fsub.d, signaling NaN: PASS +fsub.d, infinity: PASS +fsub.d, -infinity: PASS +fsub.d, subtract infinity: PASS +fmul.d: PASS +fmul.d, quiet NaN: PASS +fmul.d, signaling NaN: PASS +fmul.d, infinity: PASS +fmul.d, -infinity: PASS +fmul.d, 0*infinity: PASS +fmul.d, overflow: PASS +fmul.d, underflow: PASS +fdiv.d: PASS +fdiv.d, quiet NaN: PASS +fdiv.d, signaling NaN: PASS +fdiv.d/0: PASS +fdiv.d/infinity: PASS +fdiv.d, infinity/infinity: PASS +fdiv.d, 0/0: PASS +fdiv.d, infinity/0: PASS +fdiv.d, 0/infinity: PASS +fdiv.d, underflow: PASS +fdiv.d, overflow: PASS +fsqrt.d: PASS +fsqrt.d, NaN: PASS +fsqrt.d, quiet NaN: PASS +fsqrt.d, signaling NaN: PASS +fsqrt.d, infinity: PASS +fsgnj.d, ++: PASS +fsgnj.d, +-: PASS +fsgnj.d, -+: PASS +fsgnj.d, --: PASS +fsgnj.d, quiet NaN: PASS +fsgnj.d, signaling NaN: PASS +fsgnj.d, inject NaN: PASS +fsgnj.d, inject -NaN: PASS +fsgnjn.d, ++: PASS +fsgnjn.d, +-: PASS +fsgnjn.d, -+: PASS +fsgnjn.d, --: PASS +fsgnjn.d, quiet NaN: PASS +fsgnjn.d, signaling NaN: PASS +fsgnjn.d, inject NaN: PASS +fsgnjn.d, inject NaN: PASS +fsgnjx.d, ++: PASS +fsgnjx.d, +-: PASS +fsgnjx.d, -+: PASS +fsgnjx.d, --: PASS +fsgnjx.d, quiet NaN: PASS +fsgnjx.d, signaling NaN: PASS +fsgnjx.d, inject NaN: PASS +fsgnjx.d, inject NaN: PASS +fmin.d: PASS +fmin.d, -infinity: PASS +fmin.d, infinity: PASS +fmin.d, quiet NaN first: PASS +fmin.d, quiet NaN second: PASS +fmin.d, quiet NaN both: PASS +fmin.d, signaling NaN first: PASS +fmin.d, signaling NaN second: PASS +fmin.d, signaling NaN both: PASS +fmax.d: PASS +fmax.d, -infinity: PASS +fmax.d, infinity: PASS +fmax.d, quiet NaN first: PASS +fmax.d, quiet NaN second: PASS +fmax.d, quiet NaN both: PASS +fmax.d, signaling NaN first: PASS +fmax.d, signaling NaN second: PASS +fmax.d, signaling NaN both: PASS +fcvt.s.d: PASS +fcvt.s.d, quiet NaN: PASS +fcvt.s.d, signaling NaN: PASS +fcvt.s.d, infinity: PASS +fcvt.s.d, overflow: PASS +fcvt.s.d, underflow: PASS +fcvt.d.s: PASS +fcvt.d.s, quiet NaN: PASS +fcvt.d.s, signaling NaN: PASS +fcvt.d.s, infinity: PASS +feq.d, equal: PASS +feq.d, not equal: PASS +feq.d, 0 == -0: PASS +feq.d, quiet NaN first: PASS +feq.d, quiet NaN second: PASS +feq.d, quiet NaN both: PASS +feq.d, signaling NaN first: PASS +feq.d, signaling NaN second: PASS +feq.d, signaling NaN both: PASS +flt.d, equal: PASS +flt.d, less: PASS +flt.d, greater: PASS +flt.d, quiet NaN first: PASS +flt.d, quiet NaN second: PASS +flt.d, quiet NaN both: PASS +flt.d, signaling NaN first: PASS +flt.d, signaling NaN second: PASS +flt.d, signaling NaN both: PASS +fle.d, equal: PASS +fle.d, less: PASS +fle.d, greater: PASS +fle.d, 0 == -0: PASS +fle.d, quiet NaN first: PASS +fle.d, quiet NaN second: PASS +fle.d, quiet NaN both: PASS +fle.d, signaling NaN first: PASS +fle.d, signaling NaN second: PASS +fle.d, signaling NaN both: PASS +fclass.d, -infinity: PASS +fclass.d, -normal: PASS +fclass.d, -subnormal: PASS +fclass.d, -0.0: PASS +fclass.d, 0.0: PASS +fclass.d, subnormal: PASS +fclass.d, normal: PASS +fclass.d, infinity: PASS +fclass.d, signaling NaN: PASS +fclass.s, quiet NaN: PASS +fcvt.w.d, truncate positive: PASS +fcvt.w.d, truncate negative: PASS +fcvt.w.d, 0.0: PASS +fcvt.w.d, -0.0: PASS +fcvt.w.d, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +fcvt.w.d, underflow: PASS +fcvt.w.d, infinity: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +fcvt.w.d, -infinity: PASS +fcvt.w.d, quiet NaN: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +fcvt.w.d, quiet -NaN: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +fcvt.w.d, signaling NaN: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +fcvt.wu.d, truncate positive: PASS +fcvt.wu.d, truncate negative: PASS +fcvt.wu.d, 0.0: PASS +fcvt.wu.d, -0.0: PASS +fcvt.wu.d, overflow: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.d, underflow: PASS +fcvt.wu.d, infinity: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.d, -infinity: PASS +fcvt.wu.d, quiet NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.d, quiet -NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.d, signaling NaN: PASS +fcvt.d.w, 0: PASS +fcvt.d.w, negative: PASS +fcvt.d.w, truncate: PASS +fcvt.d.wu, 0: PASS +fcvt.d.wu: PASS +fcvt.d.wu, truncate: PASS +fcvt.l.d, truncate positive: PASS +fcvt.l.d, truncate negative: PASS +fcvt.l.d, 0.0: PASS +fcvt.l.d, -0.0: PASS +fcvt.l.d, 32-bit overflow: PASS +fcvt.l.d, overflow: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.l.d, underflow: PASS +fcvt.l.d, infinity: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.l.d, -infinity: PASS +fcvt.l.d, quiet NaN: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.l.d, quiet -NaN: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.l.d, signaling NaN: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.lu.d, truncate positive: PASS +fcvt.lu.d, truncate negative: PASS +fcvt.lu.d, 0.0: PASS +fcvt.lu.d, -0.0: PASS +fcvt.lu.d, 32-bit overflow: PASS +fcvt.lu.d, overflow: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.lu.d, underflow: PASS +fcvt.lu.d, infinity: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.lu.d, -infinity: PASS +fcvt.lu.d, quiet NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 9223372036854775808) +fcvt.lu.d, quiet -NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 9223372036854775808) +fcvt.lu.d, signaling NaN: PASS +fmv.x.d, positive: PASS +fmv.x.d, negative: PASS +fmv.x.d, 0.0: PASS +fmv.x.d, -0.0: PASS +fcvt.d.l, 0: PASS +fcvt.d.l, negative: PASS +fcvt.d.l, 32-bit truncate: PASS +fcvt.d.lu, 0: PASS +fcvt.d.lu: PASS +fcvt.d.lu, 32-bit truncate: PASS +fmv.d.x: PASS +Exiting @ tick 357345500 because exiting with last active thread context diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/stats.txt new file mode 100644 index 000000000..98cb2e5f2 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/stats.txt @@ -0,0 +1,1059 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000357 +sim_ticks 357345500 +final_tick 357345500 +sim_freq 1000000000000 +host_inst_rate 5089 +host_op_rate 5104 +host_tick_rate 4183343 +host_mem_usage 272348 +host_seconds 85.42 +sim_insts 434729 +sim_ops 436032 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 357345500 +system.physmem.bytes_read::cpu.inst 79680 +system.physmem.bytes_read::cpu.data 34816 +system.physmem.bytes_read::total 114496 +system.physmem.bytes_inst_read::cpu.inst 79680 +system.physmem.bytes_inst_read::total 79680 +system.physmem.num_reads::cpu.inst 1245 +system.physmem.num_reads::cpu.data 544 +system.physmem.num_reads::total 1789 +system.physmem.bw_read::cpu.inst 222977482 +system.physmem.bw_read::cpu.data 97429518 +system.physmem.bw_read::total 320407001 +system.physmem.bw_inst_read::cpu.inst 222977482 +system.physmem.bw_inst_read::total 222977482 +system.physmem.bw_total::cpu.inst 222977482 +system.physmem.bw_total::cpu.data 97429518 +system.physmem.bw_total::total 320407001 +system.physmem.readReqs 1789 +system.physmem.writeReqs 0 +system.physmem.readBursts 1789 +system.physmem.writeBursts 0 +system.physmem.bytesReadDRAM 114496 +system.physmem.bytesReadWrQ 0 +system.physmem.bytesWritten 0 +system.physmem.bytesReadSys 114496 +system.physmem.bytesWrittenSys 0 +system.physmem.servicedByWrQ 0 +system.physmem.mergedWrBursts 0 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 257 +system.physmem.perBankRdBursts::1 275 +system.physmem.perBankRdBursts::2 173 +system.physmem.perBankRdBursts::3 193 +system.physmem.perBankRdBursts::4 150 +system.physmem.perBankRdBursts::5 95 +system.physmem.perBankRdBursts::6 117 +system.physmem.perBankRdBursts::7 59 +system.physmem.perBankRdBursts::8 47 +system.physmem.perBankRdBursts::9 59 +system.physmem.perBankRdBursts::10 19 +system.physmem.perBankRdBursts::11 34 +system.physmem.perBankRdBursts::12 85 +system.physmem.perBankRdBursts::13 69 +system.physmem.perBankRdBursts::14 57 +system.physmem.perBankRdBursts::15 100 +system.physmem.perBankWrBursts::0 0 +system.physmem.perBankWrBursts::1 0 +system.physmem.perBankWrBursts::2 0 +system.physmem.perBankWrBursts::3 0 +system.physmem.perBankWrBursts::4 0 +system.physmem.perBankWrBursts::5 0 +system.physmem.perBankWrBursts::6 0 +system.physmem.perBankWrBursts::7 0 +system.physmem.perBankWrBursts::8 0 +system.physmem.perBankWrBursts::9 0 +system.physmem.perBankWrBursts::10 0 +system.physmem.perBankWrBursts::11 0 +system.physmem.perBankWrBursts::12 0 +system.physmem.perBankWrBursts::13 0 +system.physmem.perBankWrBursts::14 0 +system.physmem.perBankWrBursts::15 0 +system.physmem.numRdRetry 0 +system.physmem.numWrRetry 0 +system.physmem.totGap 357180500 +system.physmem.readPktSize::0 0 +system.physmem.readPktSize::1 0 +system.physmem.readPktSize::2 0 +system.physmem.readPktSize::3 0 +system.physmem.readPktSize::4 0 +system.physmem.readPktSize::5 0 +system.physmem.readPktSize::6 1789 +system.physmem.writePktSize::0 0 +system.physmem.writePktSize::1 0 +system.physmem.writePktSize::2 0 +system.physmem.writePktSize::3 0 +system.physmem.writePktSize::4 0 +system.physmem.writePktSize::5 0 +system.physmem.writePktSize::6 0 +system.physmem.rdQLenPdf::0 1144 +system.physmem.rdQLenPdf::1 452 +system.physmem.rdQLenPdf::2 140 +system.physmem.rdQLenPdf::3 40 +system.physmem.rdQLenPdf::4 12 +system.physmem.rdQLenPdf::5 1 +system.physmem.rdQLenPdf::6 0 +system.physmem.rdQLenPdf::7 0 +system.physmem.rdQLenPdf::8 0 +system.physmem.rdQLenPdf::9 0 +system.physmem.rdQLenPdf::10 0 +system.physmem.rdQLenPdf::11 0 +system.physmem.rdQLenPdf::12 0 +system.physmem.rdQLenPdf::13 0 +system.physmem.rdQLenPdf::14 0 +system.physmem.rdQLenPdf::15 0 +system.physmem.rdQLenPdf::16 0 +system.physmem.rdQLenPdf::17 0 +system.physmem.rdQLenPdf::18 0 +system.physmem.rdQLenPdf::19 0 +system.physmem.rdQLenPdf::20 0 +system.physmem.rdQLenPdf::21 0 +system.physmem.rdQLenPdf::22 0 +system.physmem.rdQLenPdf::23 0 +system.physmem.rdQLenPdf::24 0 +system.physmem.rdQLenPdf::25 0 +system.physmem.rdQLenPdf::26 0 +system.physmem.rdQLenPdf::27 0 +system.physmem.rdQLenPdf::28 0 +system.physmem.rdQLenPdf::29 0 +system.physmem.rdQLenPdf::30 0 +system.physmem.rdQLenPdf::31 0 +system.physmem.wrQLenPdf::0 0 +system.physmem.wrQLenPdf::1 0 +system.physmem.wrQLenPdf::2 0 +system.physmem.wrQLenPdf::3 0 +system.physmem.wrQLenPdf::4 0 +system.physmem.wrQLenPdf::5 0 +system.physmem.wrQLenPdf::6 0 +system.physmem.wrQLenPdf::7 0 +system.physmem.wrQLenPdf::8 0 +system.physmem.wrQLenPdf::9 0 +system.physmem.wrQLenPdf::10 0 +system.physmem.wrQLenPdf::11 0 +system.physmem.wrQLenPdf::12 0 +system.physmem.wrQLenPdf::13 0 +system.physmem.wrQLenPdf::14 0 +system.physmem.wrQLenPdf::15 0 +system.physmem.wrQLenPdf::16 0 +system.physmem.wrQLenPdf::17 0 +system.physmem.wrQLenPdf::18 0 +system.physmem.wrQLenPdf::19 0 +system.physmem.wrQLenPdf::20 0 +system.physmem.wrQLenPdf::21 0 +system.physmem.wrQLenPdf::22 0 +system.physmem.wrQLenPdf::23 0 +system.physmem.wrQLenPdf::24 0 +system.physmem.wrQLenPdf::25 0 +system.physmem.wrQLenPdf::26 0 +system.physmem.wrQLenPdf::27 0 +system.physmem.wrQLenPdf::28 0 +system.physmem.wrQLenPdf::29 0 +system.physmem.wrQLenPdf::30 0 +system.physmem.wrQLenPdf::31 0 +system.physmem.wrQLenPdf::32 0 +system.physmem.wrQLenPdf::33 0 +system.physmem.wrQLenPdf::34 0 +system.physmem.wrQLenPdf::35 0 +system.physmem.wrQLenPdf::36 0 +system.physmem.wrQLenPdf::37 0 +system.physmem.wrQLenPdf::38 0 +system.physmem.wrQLenPdf::39 0 +system.physmem.wrQLenPdf::40 0 +system.physmem.wrQLenPdf::41 0 +system.physmem.wrQLenPdf::42 0 +system.physmem.wrQLenPdf::43 0 +system.physmem.wrQLenPdf::44 0 +system.physmem.wrQLenPdf::45 0 +system.physmem.wrQLenPdf::46 0 +system.physmem.wrQLenPdf::47 0 +system.physmem.wrQLenPdf::48 0 +system.physmem.wrQLenPdf::49 0 +system.physmem.wrQLenPdf::50 0 +system.physmem.wrQLenPdf::51 0 +system.physmem.wrQLenPdf::52 0 +system.physmem.wrQLenPdf::53 0 +system.physmem.wrQLenPdf::54 0 +system.physmem.wrQLenPdf::55 0 +system.physmem.wrQLenPdf::56 0 +system.physmem.wrQLenPdf::57 0 +system.physmem.wrQLenPdf::58 0 +system.physmem.wrQLenPdf::59 0 +system.physmem.wrQLenPdf::60 0 +system.physmem.wrQLenPdf::61 0 +system.physmem.wrQLenPdf::62 0 +system.physmem.wrQLenPdf::63 0 +system.physmem.bytesPerActivate::samples 426 +system.physmem.bytesPerActivate::mean 261.258215 +system.physmem.bytesPerActivate::gmean 177.377467 +system.physmem.bytesPerActivate::stdev 241.871281 +system.physmem.bytesPerActivate::0-127 137 32.15% 32.15% +system.physmem.bytesPerActivate::128-255 116 27.23% 59.38% +system.physmem.bytesPerActivate::256-383 55 12.91% 72.30% +system.physmem.bytesPerActivate::384-511 53 12.44% 84.74% +system.physmem.bytesPerActivate::512-639 26 6.10% 90.84% +system.physmem.bytesPerActivate::640-767 12 2.81% 93.66% +system.physmem.bytesPerActivate::768-895 8 1.87% 95.53% +system.physmem.bytesPerActivate::896-1023 6 1.40% 96.94% +system.physmem.bytesPerActivate::1024-1151 13 3.05% 99.99% +system.physmem.bytesPerActivate::total 426 +system.physmem.totQLat 29198750 +system.physmem.totMemAccLat 62742500 +system.physmem.totBusLat 8945000 +system.physmem.avgQLat 16321.26 +system.physmem.avgBusLat 5000.00 +system.physmem.avgMemAccLat 35071.26 +system.physmem.avgRdBW 320.40 +system.physmem.avgWrBW 0.00 +system.physmem.avgRdBWSys 320.40 +system.physmem.avgWrBWSys 0.00 +system.physmem.peakBW 12800.00 +system.physmem.busUtil 2.50 +system.physmem.busUtilRead 2.50 +system.physmem.busUtilWrite 0.00 +system.physmem.avgRdQLen 1.36 +system.physmem.avgWrQLen 0.00 +system.physmem.readRowHits 1349 +system.physmem.writeRowHits 0 +system.physmem.readRowHitRate 75.40 +system.physmem.writeRowHitRate nan +system.physmem.avgGap 199653.71 +system.physmem.pageHitRate 75.40 +system.physmem_0.actEnergy 2156280 +system.physmem_0.preEnergy 1119525 +system.physmem_0.readEnergy 9417660 +system.physmem_0.writeEnergy 0 +system.physmem_0.refreshEnergy 27658800 +system.physmem_0.actBackEnergy 19175370 +system.physmem_0.preBackEnergy 595200 +system.physmem_0.actPowerDownEnergy 135115080 +system.physmem_0.prePowerDownEnergy 6696960 +system.physmem_0.selfRefreshEnergy 0 +system.physmem_0.totalEnergy 201934875 +system.physmem_0.averagePower 565.095827 +system.physmem_0.totalIdleTime 313626500 +system.physmem_0.memoryStateTime::IDLE 257500 +system.physmem_0.memoryStateTime::REF 11700000 +system.physmem_0.memoryStateTime::SREF 0 +system.physmem_0.memoryStateTime::PRE_PDN 17432500 +system.physmem_0.memoryStateTime::ACT 31632750 +system.physmem_0.memoryStateTime::ACT_PDN 296322750 +system.physmem_1.actEnergy 985320 +system.physmem_1.preEnergy 497145 +system.physmem_1.readEnergy 3355800 +system.physmem_1.writeEnergy 0 +system.physmem_1.refreshEnergy 13522080 +system.physmem_1.actBackEnergy 8332260 +system.physmem_1.preBackEnergy 718560 +system.physmem_1.actPowerDownEnergy 39862380 +system.physmem_1.prePowerDownEnergy 14924160 +system.physmem_1.selfRefreshEnergy 52829760 +system.physmem_1.totalEnergy 135027465 +system.physmem_1.averagePower 377.861709 +system.physmem_1.totalIdleTime 336590000 +system.physmem_1.memoryStateTime::IDLE 1334500 +system.physmem_1.memoryStateTime::REF 5744000 +system.physmem_1.memoryStateTime::SREF 210920500 +system.physmem_1.memoryStateTime::PRE_PDN 38865500 +system.physmem_1.memoryStateTime::ACT 13057250 +system.physmem_1.memoryStateTime::ACT_PDN 87423750 +system.pwrStateResidencyTicks::UNDEFINED 357345500 +system.cpu.branchPred.lookups 137963 +system.cpu.branchPred.condPredicted 96949 +system.cpu.branchPred.condIncorrect 28208 +system.cpu.branchPred.BTBLookups 88594 +system.cpu.branchPred.BTBHits 49630 +system.cpu.branchPred.BTBCorrect 0 +system.cpu.branchPred.BTBHitPct 56.019595 +system.cpu.branchPred.usedRAS 0 +system.cpu.branchPred.RASInCorrect 0 +system.cpu.branchPred.indirectLookups 28658 +system.cpu.branchPred.indirectHits 15467 +system.cpu.branchPred.indirectMisses 13191 +system.cpu.branchPredindirectMispredicted 5179 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 220 +system.cpu.pwrStateResidencyTicks::ON 357345500 +system.cpu.numCycles 714692 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.fetch.icacheStallCycles 135613 +system.cpu.fetch.Insts 614596 +system.cpu.fetch.Branches 137963 +system.cpu.fetch.predictedBranches 65097 +system.cpu.fetch.Cycles 444701 +system.cpu.fetch.SquashCycles 57212 +system.cpu.fetch.MiscStallCycles 165 +system.cpu.fetch.PendingTrapStallCycles 1046 +system.cpu.fetch.IcacheWaitRetryStallCycles 11 +system.cpu.fetch.CacheLines 93453 +system.cpu.fetch.IcacheSquashes 2267 +system.cpu.fetch.rateDist::samples 610142 +system.cpu.fetch.rateDist::mean 1.009502 +system.cpu.fetch.rateDist::stdev 0.972916 +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% +system.cpu.fetch.rateDist::0 177437 29.08% 29.08% +system.cpu.fetch.rateDist::1 317234 51.99% 81.07% +system.cpu.fetch.rateDist::2 74911 12.27% 93.35% +system.cpu.fetch.rateDist::3 21754 3.56% 96.91% +system.cpu.fetch.rateDist::4 13865 2.27% 99.19% +system.cpu.fetch.rateDist::5 2714 0.44% 99.63% +system.cpu.fetch.rateDist::6 1405 0.23% 99.86% +system.cpu.fetch.rateDist::7 414 0.06% 99.93% +system.cpu.fetch.rateDist::8 408 0.06% 99.99% +system.cpu.fetch.rateDist::overflows 0 0.00% 99.99% +system.cpu.fetch.rateDist::min_value 0 +system.cpu.fetch.rateDist::max_value 8 +system.cpu.fetch.rateDist::total 610142 +system.cpu.fetch.branchRate 0.193038 +system.cpu.fetch.rate 0.859945 +system.cpu.decode.IdleCycles 160289 +system.cpu.decode.BlockedCycles 52081 +system.cpu.decode.RunCycles 377160 +system.cpu.decode.UnblockCycles 2852 +system.cpu.decode.SquashCycles 17760 +system.cpu.decode.BranchResolved 47857 +system.cpu.decode.BranchMispred 11488 +system.cpu.decode.DecodedInsts 555576 +system.cpu.decode.SquashedInsts 15205 +system.cpu.rename.SquashCycles 17760 +system.cpu.rename.IdleCycles 181774 +system.cpu.rename.BlockCycles 4611 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+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3578 +system.membus.pkt_count::total 3578 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 114496 +system.membus.pkt_size::total 114496 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 1789 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev -0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 1789 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 1789 +system.membus.reqLayer0.occupancy 2212500 +system.membus.reqLayer0.utilization 0.6 +system.membus.respLayer1.occupancy 9488750 +system.membus.respLayer1.utilization 2.6 + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/config.ini index 287aed562..eca83b4cb 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/config.ini +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/config.ini @@ -88,8 +88,10 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer +wait_for_remote_gdb=false width=1 workload=system.cpu.workload dcache_port=system.membus.slave[2] @@ -118,7 +120,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=insttest cwd= drivers= @@ -127,14 +129,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/config.json index f654bdba2..579c929d2 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/config.json +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/config.json @@ -192,6 +192,7 @@ }, "p_state_clk_gate_bins": 20, "p_state_clk_gate_min": 1000, + "syscallRetryLatency": 10000, "interrupts": [ { "eventq_index": 0, @@ -216,21 +217,22 @@ "uid": 100, "pid": 100, "kvmInSE": false, - "cxx_class": "LiveProcess", - "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest", + "cxx_class": "Process", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest", "drivers": [], "system": "system", "gid": 100, "eventq_index": 0, "env": [], - "input": "cin", - "ppid": 99, - "type": "LiveProcess", + "maxStackSize": 67108864, + "ppid": 0, + "type": "Process", "cwd": "", + "pgid": 100, "simpoint": 0, "euid": 100, + "input": "cin", "path": "system.cpu.workload", - "max_stack_size": 67108864, "name": "workload", "cmd": [ "insttest" @@ -242,6 +244,7 @@ } ], "name": "cpu", + "wait_for_remote_gdb": false, "dtb": { "name": "dtb", "eventq_index": 0, diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/simerr index fd133b12b..1b7fba635 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/simerr +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/simerr @@ -1,3 +1,5 @@ -warn: Unknown operating system; assuming Linux. warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings. + Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest' +info: Increasing stack size by one page. diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/simout index 0379b0893..93ababb29 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/simout +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/simout @@ -3,14 +3,12 @@ Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv6 gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 30 2016 14:33:35 -gem5 started Nov 30 2016 16:18:31 -gem5 executing on zizzer, pid 34072 -command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-atomic -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/simple-atomic +gem5 compiled Jul 13 2017 17:09:45 +gem5 started Jul 13 2017 17:12:11 +gem5 executing on boldrock, pid 2055 +command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. fld: PASS fsd: PASS fmadd.d: PASS @@ -165,4 +163,62 @@ fcvt.w.d, truncate negative: PASS fcvt.w.d, 0.0: PASS fcvt.w.d, -0.0: PASS fcvt.w.d, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) -Exiting @ tick 149676500 because target called exit() +fcvt.w.d, underflow: PASS +fcvt.w.d, infinity: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +fcvt.w.d, -infinity: PASS +fcvt.w.d, quiet NaN: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +fcvt.w.d, quiet -NaN: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +fcvt.w.d, signaling NaN: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +fcvt.wu.d, truncate positive: PASS +fcvt.wu.d, truncate negative: PASS +fcvt.wu.d, 0.0: PASS +fcvt.wu.d, -0.0: PASS +fcvt.wu.d, overflow: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.d, underflow: PASS +fcvt.wu.d, infinity: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.d, -infinity: PASS +fcvt.wu.d, quiet NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.d, quiet -NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.d, signaling NaN: PASS +fcvt.d.w, 0: PASS +fcvt.d.w, negative: PASS +fcvt.d.w, truncate: PASS +fcvt.d.wu, 0: PASS +fcvt.d.wu: PASS +fcvt.d.wu, truncate: PASS +fcvt.l.d, truncate positive: PASS +fcvt.l.d, truncate negative: PASS +fcvt.l.d, 0.0: PASS +fcvt.l.d, -0.0: PASS +fcvt.l.d, 32-bit overflow: PASS +fcvt.l.d, overflow: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.l.d, underflow: PASS +fcvt.l.d, infinity: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.l.d, -infinity: PASS +fcvt.l.d, quiet NaN: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.l.d, quiet -NaN: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.l.d, signaling NaN: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.lu.d, truncate positive: PASS +fcvt.lu.d, truncate negative: PASS +fcvt.lu.d, 0.0: PASS +fcvt.lu.d, -0.0: PASS +fcvt.lu.d, 32-bit overflow: PASS +fcvt.lu.d, overflow: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.lu.d, underflow: PASS +fcvt.lu.d, infinity: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.lu.d, -infinity: PASS +fcvt.lu.d, quiet NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 9223372036854775808) +fcvt.lu.d, quiet -NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 9223372036854775808) +fcvt.lu.d, signaling NaN: PASS +fmv.x.d, positive: PASS +fmv.x.d, negative: PASS +fmv.x.d, 0.0: PASS +fmv.x.d, -0.0: PASS +fcvt.d.l, 0: PASS +fcvt.d.l, negative: PASS +fcvt.d.l, 32-bit truncate: PASS +fcvt.d.lu, 0: PASS +fcvt.d.lu: PASS +fcvt.d.lu, 32-bit truncate: PASS +fmv.d.x: PASS +Exiting @ tick 255853000 because exiting with last active thread context diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/stats.txt index 392691780..65d874af9 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/stats.txt @@ -1,153 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000150 # Number of seconds simulated -sim_ticks 149676500 # Number of ticks simulated -final_tick 149676500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 28553 # Simulator instruction rate (inst/s) -host_op_rate 28553 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14284274 # Simulator tick rate (ticks/s) -host_mem_usage 234416 # Number of bytes of host memory used -host_seconds 10.48 # Real time elapsed on the host -sim_insts 299191 # Number of instructions simulated -sim_ops 299191 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 149676500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 1197416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 459717 # Number of bytes read from this memory -system.physmem.bytes_read::total 1657133 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1197416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1197416 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 301409 # Number of bytes written to this memory -system.physmem.bytes_written::total 301409 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 299354 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 69843 # Number of read requests responded to by this memory -system.physmem.num_reads::total 369197 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 48546 # Number of write requests responded to by this memory -system.physmem.num_writes::total 48546 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 8000026724 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3071403995 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11071430719 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8000026724 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8000026724 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 2013736291 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2013736291 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8000026724 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5085140286 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13085167010 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 149676500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 162 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 149676500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 299354 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 299191 # Number of instructions committed -system.cpu.committedOps 299191 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 299008 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 1025 # Number of float alu accesses -system.cpu.num_func_calls 21816 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 44561 # number of instructions that are conditional controls -system.cpu.num_int_insts 299008 # number of integer instructions -system.cpu.num_fp_insts 1025 # number of float instructions -system.cpu.num_int_register_reads 394163 # number of times the integer registers were read -system.cpu.num_int_register_writes 205779 # number of times the integer registers were written -system.cpu.num_fp_register_reads 851 # number of times the floating registers were read -system.cpu.num_fp_register_writes 688 # number of times the floating registers were written -system.cpu.num_mem_refs 118390 # number of memory refs -system.cpu.num_load_insts 69843 # Number of load instructions -system.cpu.num_store_insts 48547 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 299354 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 66377 # Number of branches fetched -system.cpu.op_class::No_OpClass 162 0.05% 0.05% # Class of executed instruction -system.cpu.op_class::IntAlu 179913 60.10% 60.15% # Class of executed instruction -system.cpu.op_class::IntMult 466 0.16% 60.31% # Class of executed instruction -system.cpu.op_class::IntDiv 40 0.01% 60.32% # Class of executed instruction -system.cpu.op_class::FloatAdd 120 0.04% 60.36% # Class of executed instruction -system.cpu.op_class::FloatCmp 157 0.05% 60.42% # Class of executed instruction -system.cpu.op_class::FloatCvt 60 0.02% 60.44% # Class of executed instruction -system.cpu.op_class::FloatMult 30 0.01% 60.45% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::FloatDiv 11 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::FloatSqrt 5 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::MemRead 69348 23.17% 83.62% # Class of executed instruction -system.cpu.op_class::MemWrite 48400 16.17% 99.79% # Class of executed instruction -system.cpu.op_class::FloatMemRead 495 0.17% 99.95% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 147 0.05% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 299354 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 149676500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 369197 # Transaction distribution -system.membus.trans_dist::ReadResp 369197 # Transaction distribution -system.membus.trans_dist::WriteReq 48546 # Transaction distribution -system.membus.trans_dist::WriteResp 48546 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 598708 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 236778 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 835486 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1197416 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 761126 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1958542 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 417743 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 417743 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 417743 # Request fanout histogram +sim_seconds 0.000255 +sim_ticks 255853000 +final_tick 255853000 +sim_freq 1000000000000 +host_inst_rate 4946 +host_op_rate 4960 +host_tick_rate 2910956 +host_mem_usage 259288 +host_seconds 87.89 +sim_insts 434729 +sim_ops 436032 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 255853000 +system.physmem.bytes_read::cpu.inst 2041616 +system.physmem.bytes_read::cpu.data 725609 +system.physmem.bytes_read::total 2767225 +system.physmem.bytes_inst_read::cpu.inst 2041616 +system.physmem.bytes_inst_read::total 2041616 +system.physmem.bytes_written::cpu.data 458503 +system.physmem.bytes_written::total 458503 +system.physmem.num_reads::cpu.inst 510404 +system.physmem.num_reads::cpu.data 110145 +system.physmem.num_reads::total 620549 +system.physmem.num_writes::cpu.data 67023 +system.physmem.num_writes::total 67023 +system.physmem.bw_read::cpu.inst 7979644561 +system.physmem.bw_read::cpu.data 2836038662 +system.physmem.bw_read::total 10815683224 +system.physmem.bw_inst_read::cpu.inst 7979644561 +system.physmem.bw_inst_read::total 7979644561 +system.physmem.bw_write::cpu.data 1792056376 +system.physmem.bw_write::total 1792056376 +system.physmem.bw_total::cpu.inst 7979644561 +system.physmem.bw_total::cpu.data 4628095038 +system.physmem.bw_total::total 12607739600 +system.pwrStateResidencyTicks::UNDEFINED 255853000 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 220 +system.cpu.pwrStateResidencyTicks::ON 255853000 +system.cpu.numCycles 511707 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 434729 +system.cpu.committedOps 436032 +system.cpu.num_int_alu_accesses 433908 +system.cpu.num_fp_alu_accesses 1229 +system.cpu.num_vec_alu_accesses 0 +system.cpu.num_func_calls 23870 +system.cpu.num_conditional_control_insts 71049 +system.cpu.num_int_insts 433908 +system.cpu.num_fp_insts 1229 +system.cpu.num_vec_insts 0 +system.cpu.num_int_register_reads 549660 +system.cpu.num_int_register_writes 288600 +system.cpu.num_fp_register_reads 988 +system.cpu.num_fp_register_writes 800 +system.cpu.num_vec_register_reads 0 +system.cpu.num_vec_register_writes 0 +system.cpu.num_mem_refs 177168 +system.cpu.num_load_insts 110145 +system.cpu.num_store_insts 67023 +system.cpu.num_idle_cycles -0 +system.cpu.num_busy_cycles 511707 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction -0 +system.cpu.Branches 94919 +system.cpu.op_class::No_OpClass 224 0.05% 0.05% +system.cpu.op_class::IntAlu 256681 58.83% 58.88% +system.cpu.op_class::IntMult 710 0.16% 59.05% +system.cpu.op_class::IntDiv 992 0.22% 59.27% +system.cpu.op_class::FloatAdd 133 0.03% 59.30% +system.cpu.op_class::FloatCmp 170 0.03% 59.34% +system.cpu.op_class::FloatCvt 128 0.02% 59.37% +system.cpu.op_class::FloatMult 30 0.00% 59.38% +system.cpu.op_class::FloatMultAcc 0 0.00% 59.38% +system.cpu.op_class::FloatDiv 11 0.00% 59.38% +system.cpu.op_class::FloatMisc 0 0.00% 59.38% +system.cpu.op_class::FloatSqrt 5 0.00% 59.38% +system.cpu.op_class::SimdAdd 0 0.00% 59.38% +system.cpu.op_class::SimdAddAcc 0 0.00% 59.38% +system.cpu.op_class::SimdAlu 0 0.00% 59.38% +system.cpu.op_class::SimdCmp 0 0.00% 59.38% +system.cpu.op_class::SimdCvt 0 0.00% 59.38% +system.cpu.op_class::SimdMisc 0 0.00% 59.38% +system.cpu.op_class::SimdMult 0 0.00% 59.38% +system.cpu.op_class::SimdMultAcc 0 0.00% 59.38% +system.cpu.op_class::SimdShift 0 0.00% 59.38% +system.cpu.op_class::SimdShiftAcc 0 0.00% 59.38% +system.cpu.op_class::SimdSqrt 0 0.00% 59.38% +system.cpu.op_class::SimdFloatAdd 0 0.00% 59.38% +system.cpu.op_class::SimdFloatAlu 0 0.00% 59.38% +system.cpu.op_class::SimdFloatCmp 0 0.00% 59.38% +system.cpu.op_class::SimdFloatCvt 0 0.00% 59.38% +system.cpu.op_class::SimdFloatDiv 0 0.00% 59.38% +system.cpu.op_class::SimdFloatMisc 0 0.00% 59.38% +system.cpu.op_class::SimdFloatMult 0 0.00% 59.38% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 59.38% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 59.38% +system.cpu.op_class::MemRead 109574 25.11% 84.50% +system.cpu.op_class::MemWrite 66842 15.32% 99.82% +system.cpu.op_class::FloatMemRead 571 0.13% 99.95% +system.cpu.op_class::FloatMemWrite 181 0.04% 99.99% +system.cpu.op_class::IprAccess 0 0.00% 99.99% +system.cpu.op_class::InstPrefetch 0 0.00% 99.99% +system.cpu.op_class::total 436252 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 255853000 +system.membus.trans_dist::ReadReq 618790 +system.membus.trans_dist::ReadResp 620549 +system.membus.trans_dist::WriteReq 65264 +system.membus.trans_dist::WriteResp 65264 +system.membus.trans_dist::LoadLockedReq 1759 +system.membus.trans_dist::StoreCondReq 1759 +system.membus.trans_dist::StoreCondResp 1759 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1020808 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 354336 +system.membus.pkt_count::total 1375144 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2041616 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1184112 +system.membus.pkt_size::total 3225728 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 687572 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev -0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 687572 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 687572 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.ini index 0a11055d6..13f8c15d6 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.ini +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.ini @@ -85,8 +85,10 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer +wait_for_remote_gdb=false workload=system.cpu.workload dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] @@ -122,7 +124,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=insttest cwd= drivers= @@ -131,14 +133,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -266,6 +269,7 @@ voltage_domain=system.voltage_domain [system.ruby.dir_cntrl0] type=Directory_Controller children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory +addr_ranges=0:268435455:5:0:0:0 buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 @@ -288,16 +292,14 @@ responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory ruby_system=system.ruby system=system to_memory_controller_latency=1 -transitions_per_cycle=4 +transitions_per_cycle=32 version=0 memory=system.mem_ctrls.port [system.ruby.dir_cntrl0.directory] type=RubyDirectoryMemory +addr_ranges=0:268435455:5:0:0:0 eventq_index=0 -numa_high_bit=5 -size=268435456 -version=0 [system.ruby.dir_cntrl0.dmaRequestToDir] type=MessageBuffer @@ -349,6 +351,7 @@ randomization=false [system.ruby.l1_cntrl0] type=L1Cache_Controller children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer +addr_ranges=0:18446744073709551615:0:0:0:0 buffer_size=0 cacheMemory=system.ruby.l1_cntrl0.cacheMemory cache_response_latency=12 diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.json index e041cd07a..2fd83cc59 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.json +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.json @@ -115,7 +115,6 @@ "path": "system.ruby.l1_cntrl0.requestFromCache", "type": "MessageBuffer" }, - "cxx_class": "L1Cache_Controller", "forwardToCache": { "ordered": true, "name": "forwardToCache", @@ -168,8 +167,9 @@ "support_data_reqs": true, "is_cpu_sequencer": true }, - "type": "L1Cache_Controller", + "cxx_class": "L1Cache_Controller", "issue_latency": 2, + "type": "L1Cache_Controller", "recycle_latency": 10, "clk_domain": "system.cpu.clk_domain", "version": 0, @@ -241,6 +241,9 @@ }, "ruby_system": "system.ruby", "name": "l1_cntrl0", + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], "p_state_clk_gate_bins": 20, "mandatoryQueue": { "ordered": false, @@ -1447,12 +1450,15 @@ "path": "system.ruby.dir_cntrl0.responseFromDir", "type": "MessageBuffer" }, - "transitions_per_cycle": 4, + "transitions_per_cycle": 32, "memory": { "peer": "system.mem_ctrls.port", "role": "MASTER" }, "power_model": null, + "addr_ranges": [ + "0:268435455:5:0:0:0" + ], "buffer_size": 0, "ruby_system": "system.ruby", "requestToDir": { @@ -1487,13 +1493,13 @@ "p_state_clk_gate_bins": 20, "directory": { "name": "directory", - "version": 0, + "addr_ranges": [ + "0:268435455:5:0:0:0" + ], "eventq_index": 0, "cxx_class": "DirectoryMemory", "path": "system.ruby.dir_cntrl0.directory", - "type": "RubyDirectoryMemory", - "numa_high_bit": 5, - "size": 268435456 + "type": "RubyDirectoryMemory" }, "path": "system.ruby.dir_cntrl0" } @@ -1548,6 +1554,7 @@ }, "p_state_clk_gate_bins": 20, "p_state_clk_gate_min": 1, + "syscallRetryLatency": 10000, "interrupts": [ { "eventq_index": 0, @@ -1572,21 +1579,22 @@ "uid": 100, "pid": 100, "kvmInSE": false, - "cxx_class": "LiveProcess", - "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest", + "cxx_class": "Process", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest", "drivers": [], "system": "system", "gid": 100, "eventq_index": 0, "env": [], - "input": "cin", - "ppid": 99, - "type": "LiveProcess", + "maxStackSize": 67108864, + "ppid": 0, + "type": "Process", "cwd": "", + "pgid": 100, "simpoint": 0, "euid": 100, + "input": "cin", "path": "system.cpu.workload", - "max_stack_size": 67108864, "name": "workload", "cmd": [ "insttest" @@ -1598,6 +1606,7 @@ } ], "name": "cpu", + "wait_for_remote_gdb": false, "dtb": { "name": "dtb", "eventq_index": 0, diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simerr index 63b14556f..27ce09844 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simerr +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simerr @@ -4,8 +4,12 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) -warn: Unknown operating system; assuming Linux. warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! +warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings. + Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest' +info: Increasing stack size by one page. diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simout index 6698d57dd..ffe951ca5 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simout +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simout @@ -3,14 +3,12 @@ Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv6 gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 30 2016 14:33:35 -gem5 started Nov 30 2016 16:18:32 -gem5 executing on zizzer, pid 34074 -command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby +gem5 compiled Jul 13 2017 17:09:45 +gem5 started Jul 13 2017 17:09:50 +gem5 executing on boldrock, pid 1344 +command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. fld: PASS fsd: PASS fmadd.d: PASS @@ -165,4 +163,62 @@ fcvt.w.d, truncate negative: PASS fcvt.w.d, 0.0: PASS fcvt.w.d, -0.0: PASS fcvt.w.d, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) -Exiting @ tick 6393532 because target called exit() +fcvt.w.d, underflow: PASS +fcvt.w.d, infinity: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +fcvt.w.d, -infinity: PASS +fcvt.w.d, quiet NaN: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +fcvt.w.d, quiet -NaN: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +fcvt.w.d, signaling NaN: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +fcvt.wu.d, truncate positive: PASS +fcvt.wu.d, truncate negative: PASS +fcvt.wu.d, 0.0: PASS +fcvt.wu.d, -0.0: PASS +fcvt.wu.d, overflow: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.d, underflow: PASS +fcvt.wu.d, infinity: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.d, -infinity: PASS +fcvt.wu.d, quiet NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.d, quiet -NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.d, signaling NaN: PASS +fcvt.d.w, 0: PASS +fcvt.d.w, negative: PASS +fcvt.d.w, truncate: PASS +fcvt.d.wu, 0: PASS +fcvt.d.wu: PASS +fcvt.d.wu, truncate: PASS +fcvt.l.d, truncate positive: PASS +fcvt.l.d, truncate negative: PASS +fcvt.l.d, 0.0: PASS +fcvt.l.d, -0.0: PASS +fcvt.l.d, 32-bit overflow: PASS +fcvt.l.d, overflow: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.l.d, underflow: PASS +fcvt.l.d, infinity: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.l.d, -infinity: PASS +fcvt.l.d, quiet NaN: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.l.d, quiet -NaN: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.l.d, signaling NaN: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.lu.d, truncate positive: PASS +fcvt.lu.d, truncate negative: PASS +fcvt.lu.d, 0.0: PASS +fcvt.lu.d, -0.0: PASS +fcvt.lu.d, 32-bit overflow: PASS +fcvt.lu.d, overflow: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.lu.d, underflow: PASS +fcvt.lu.d, infinity: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.lu.d, -infinity: PASS +fcvt.lu.d, quiet NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 9223372036854775808) +fcvt.lu.d, quiet -NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 9223372036854775808) +fcvt.lu.d, signaling NaN: PASS +fmv.x.d, positive: PASS +fmv.x.d, negative: PASS +fmv.x.d, 0.0: PASS +fmv.x.d, -0.0: PASS +fcvt.d.l, 0: PASS +fcvt.d.l, negative: PASS +fcvt.d.l, 32-bit truncate: PASS +fcvt.d.lu, 0: PASS +fcvt.d.lu: PASS +fcvt.d.lu, 32-bit truncate: PASS +fmv.d.x: PASS +Exiting @ tick 8234747 because exiting with last active thread context diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/stats.txt index 218c95842..71f7cb149 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/stats.txt @@ -1,618 +1,658 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.006394 # Number of seconds simulated -sim_ticks 6393532 # Number of ticks simulated -final_tick 6393532 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 80438 # Simulator instruction rate (inst/s) -host_op_rate 80438 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1718903 # Simulator tick rate (ticks/s) -host_mem_usage 429644 # Number of bytes of host memory used -host_seconds 3.72 # Real time elapsed on the host -sim_insts 299191 # Number of instructions simulated -sim_ops 299191 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 6256640 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 6256640 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 6256384 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 6256384 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 97760 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 97760 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 97756 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 97756 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 978588986 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 978588986 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 978548946 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 978548946 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1957137933 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1957137933 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 97760 # Number of read requests accepted -system.mem_ctrls.writeReqs 97756 # Number of write requests accepted -system.mem_ctrls.readBursts 97760 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 97756 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 3295040 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 2961600 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 3443712 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 6256640 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 6256384 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 46275 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 43917 # Number of DRAM write bursts merged with an existing one -system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 352 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 1012 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 26 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 3288 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 5256 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 9431 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 7439 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 1368 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 225 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 1039 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 2533 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 14031 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 3005 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 1537 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 25 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 918 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 359 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 1066 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 34 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 3555 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 5446 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 9633 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 8466 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 1431 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 225 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 1069 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 2579 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 14351 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 3053 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 1590 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 28 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 923 # Per bank write bursts -system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 6393460 # Total gap between requests -system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 97760 # Read request sizes (log2) -system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 97756 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 51485 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 306 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 334 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 2779 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 3333 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 3383 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 3473 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 3559 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 3516 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 3321 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 3315 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 3314 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 3314 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 3314 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 3313 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 3313 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 3313 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 3312 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 3312 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 20661 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 326.074440 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 208.715959 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 320.266569 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 5014 24.27% 24.27% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 6296 30.47% 54.74% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 3457 16.73% 71.47% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 1315 6.36% 77.84% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 736 3.56% 81.40% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 594 2.87% 84.27% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 389 1.88% 86.16% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 293 1.42% 87.58% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 2567 12.42% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 20661 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 3312 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 15.540459 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 15.485552 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 1.332467 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 139 4.20% 4.20% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 1517 45.80% 50.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 1421 42.90% 92.90% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 229 6.91% 99.82% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-21 5 0.15% 99.97% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::36-37 1 0.03% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 3312 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 3312 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.246377 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.229566 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.773105 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 2986 90.16% 90.16% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 14 0.42% 90.58% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 147 4.44% 95.02% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 153 4.62% 99.64% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 11 0.33% 99.97% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::21 1 0.03% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 3312 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 1034437 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 2012652 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 257425 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 20.09 # Average queueing delay per DRAM burst -system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 39.09 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 515.37 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 538.62 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 978.59 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 978.55 # Average system write bandwidth in MiByte/s -system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 8.23 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.03 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 4.21 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.90 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 36136 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 48490 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 70.19 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 90.06 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 32.70 # Average gap between requests -system.mem_ctrls.pageHitRate 80.35 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 95226180 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 51522576 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 321836928 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 250476480 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 501546240.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 829542432 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 11702016 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 1925180016 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 78745728 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 34138560 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 4099917156 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 641.260129 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 4543849 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 6758 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 212226 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 116933 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 205067 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 1630662 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 4221886 # Time in different power states -system.mem_ctrls_1.actEnergy 52336200 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 28311528 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 266327712 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 198927936 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 482492400.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 818266464 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 13925376 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 1847919480 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 72638976 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 80402640 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 3861548712 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 603.977381 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 4562502 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 13661 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 204136 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 321205 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 189164 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 1612911 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 4052455 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states -system.cpu.clk_domain.clock 1 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 162 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 6393532 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 6393532 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 299191 # Number of instructions committed -system.cpu.committedOps 299191 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 299008 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 1025 # Number of float alu accesses -system.cpu.num_func_calls 21816 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 44561 # number of instructions that are conditional controls -system.cpu.num_int_insts 299008 # number of integer instructions -system.cpu.num_fp_insts 1025 # number of float instructions -system.cpu.num_int_register_reads 394163 # number of times the integer registers were read -system.cpu.num_int_register_writes 205779 # number of times the integer registers were written -system.cpu.num_fp_register_reads 851 # number of times the floating registers were read -system.cpu.num_fp_register_writes 688 # number of times the floating registers were written -system.cpu.num_mem_refs 118390 # number of memory refs -system.cpu.num_load_insts 69843 # Number of load instructions -system.cpu.num_store_insts 48547 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 6393532 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 66377 # Number of branches fetched -system.cpu.op_class::No_OpClass 162 0.05% 0.05% # Class of executed instruction -system.cpu.op_class::IntAlu 179913 60.10% 60.15% # Class of executed instruction -system.cpu.op_class::IntMult 466 0.16% 60.31% # Class of executed instruction -system.cpu.op_class::IntDiv 40 0.01% 60.32% # Class of executed instruction -system.cpu.op_class::FloatAdd 120 0.04% 60.36% # Class of executed instruction -system.cpu.op_class::FloatCmp 157 0.05% 60.42% # Class of executed instruction -system.cpu.op_class::FloatCvt 60 0.02% 60.44% # Class of executed instruction -system.cpu.op_class::FloatMult 30 0.01% 60.45% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::FloatDiv 11 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::FloatSqrt 5 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::MemRead 69348 23.17% 83.62% # Class of executed instruction -system.cpu.op_class::MemWrite 48400 16.17% 99.79% # Class of executed instruction -system.cpu.op_class::FloatMemRead 495 0.17% 99.95% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 147 0.05% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 299354 # Class of executed instruction -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states -system.ruby.delayHist::bucket_size 1 # delay histogram for all message -system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 195516 # delay histogram for all message -system.ruby.delayHist | 195516 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 195516 # delay histogram for all message +sim_seconds 0.008234 +sim_ticks 8234747 +final_tick 8234747 +sim_freq 1000000000 +host_inst_rate 3359 +host_op_rate 3369 +host_tick_rate 63636 +host_mem_usage 439776 +host_seconds 129.40 +sim_insts 434729 +sim_ops 436032 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1 +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 8234747 +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 7528256 +system.mem_ctrls.bytes_read::total 7528256 +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 7528000 +system.mem_ctrls.bytes_written::total 7528000 +system.mem_ctrls.num_reads::ruby.dir_cntrl0 117629 +system.mem_ctrls.num_reads::total 117629 +system.mem_ctrls.num_writes::ruby.dir_cntrl0 117625 +system.mem_ctrls.num_writes::total 117625 +system.mem_ctrls.bw_read::ruby.dir_cntrl0 914206107 +system.mem_ctrls.bw_read::total 914206107 +system.mem_ctrls.bw_write::ruby.dir_cntrl0 914175019 +system.mem_ctrls.bw_write::total 914175019 +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1828381126 +system.mem_ctrls.bw_total::total 1828381126 +system.mem_ctrls.readReqs 117629 +system.mem_ctrls.writeReqs 117625 +system.mem_ctrls.readBursts 117629 +system.mem_ctrls.writeBursts 117625 +system.mem_ctrls.bytesReadDRAM 4130304 +system.mem_ctrls.bytesReadWrQ 3397952 +system.mem_ctrls.bytesWritten 4366848 +system.mem_ctrls.bytesReadSys 7528256 +system.mem_ctrls.bytesWrittenSys 7528000 +system.mem_ctrls.servicedByWrQ 53093 +system.mem_ctrls.mergedWrBursts 49364 +system.mem_ctrls.neitherReadNorWriteReqs 0 +system.mem_ctrls.perBankRdBursts::0 10167 +system.mem_ctrls.perBankRdBursts::1 8186 +system.mem_ctrls.perBankRdBursts::2 6889 +system.mem_ctrls.perBankRdBursts::3 10537 +system.mem_ctrls.perBankRdBursts::4 4633 +system.mem_ctrls.perBankRdBursts::5 1895 +system.mem_ctrls.perBankRdBursts::6 3152 +system.mem_ctrls.perBankRdBursts::7 8737 +system.mem_ctrls.perBankRdBursts::8 56 +system.mem_ctrls.perBankRdBursts::9 166 +system.mem_ctrls.perBankRdBursts::10 14 +system.mem_ctrls.perBankRdBursts::11 251 +system.mem_ctrls.perBankRdBursts::12 1768 +system.mem_ctrls.perBankRdBursts::13 891 +system.mem_ctrls.perBankRdBursts::14 2177 +system.mem_ctrls.perBankRdBursts::15 5017 +system.mem_ctrls.perBankWrBursts::0 10442 +system.mem_ctrls.perBankWrBursts::1 8547 +system.mem_ctrls.perBankWrBursts::2 7140 +system.mem_ctrls.perBankWrBursts::3 12327 +system.mem_ctrls.perBankWrBursts::4 4765 +system.mem_ctrls.perBankWrBursts::5 1918 +system.mem_ctrls.perBankWrBursts::6 3176 +system.mem_ctrls.perBankWrBursts::7 9129 +system.mem_ctrls.perBankWrBursts::8 57 +system.mem_ctrls.perBankWrBursts::9 173 +system.mem_ctrls.perBankWrBursts::10 13 +system.mem_ctrls.perBankWrBursts::11 257 +system.mem_ctrls.perBankWrBursts::12 1785 +system.mem_ctrls.perBankWrBursts::13 912 +system.mem_ctrls.perBankWrBursts::14 2275 +system.mem_ctrls.perBankWrBursts::15 5316 +system.mem_ctrls.numRdRetry 0 +system.mem_ctrls.numWrRetry 0 +system.mem_ctrls.totGap 8234661 +system.mem_ctrls.readPktSize::0 0 +system.mem_ctrls.readPktSize::1 0 +system.mem_ctrls.readPktSize::2 0 +system.mem_ctrls.readPktSize::3 0 +system.mem_ctrls.readPktSize::4 0 +system.mem_ctrls.readPktSize::5 0 +system.mem_ctrls.readPktSize::6 117629 +system.mem_ctrls.writePktSize::0 0 +system.mem_ctrls.writePktSize::1 0 +system.mem_ctrls.writePktSize::2 0 +system.mem_ctrls.writePktSize::3 0 +system.mem_ctrls.writePktSize::4 0 +system.mem_ctrls.writePktSize::5 0 +system.mem_ctrls.writePktSize::6 117625 +system.mem_ctrls.rdQLenPdf::0 64536 +system.mem_ctrls.rdQLenPdf::1 0 +system.mem_ctrls.rdQLenPdf::2 0 +system.mem_ctrls.rdQLenPdf::3 0 +system.mem_ctrls.rdQLenPdf::4 0 +system.mem_ctrls.rdQLenPdf::5 0 +system.mem_ctrls.rdQLenPdf::6 0 +system.mem_ctrls.rdQLenPdf::7 0 +system.mem_ctrls.rdQLenPdf::8 0 +system.mem_ctrls.rdQLenPdf::9 0 +system.mem_ctrls.rdQLenPdf::10 0 +system.mem_ctrls.rdQLenPdf::11 0 +system.mem_ctrls.rdQLenPdf::12 0 +system.mem_ctrls.rdQLenPdf::13 0 +system.mem_ctrls.rdQLenPdf::14 0 +system.mem_ctrls.rdQLenPdf::15 0 +system.mem_ctrls.rdQLenPdf::16 0 +system.mem_ctrls.rdQLenPdf::17 0 +system.mem_ctrls.rdQLenPdf::18 0 +system.mem_ctrls.rdQLenPdf::19 0 +system.mem_ctrls.rdQLenPdf::20 0 +system.mem_ctrls.rdQLenPdf::21 0 +system.mem_ctrls.rdQLenPdf::22 0 +system.mem_ctrls.rdQLenPdf::23 0 +system.mem_ctrls.rdQLenPdf::24 0 +system.mem_ctrls.rdQLenPdf::25 0 +system.mem_ctrls.rdQLenPdf::26 0 +system.mem_ctrls.rdQLenPdf::27 0 +system.mem_ctrls.rdQLenPdf::28 0 +system.mem_ctrls.rdQLenPdf::29 0 +system.mem_ctrls.rdQLenPdf::30 0 +system.mem_ctrls.rdQLenPdf::31 0 +system.mem_ctrls.wrQLenPdf::0 1 +system.mem_ctrls.wrQLenPdf::1 1 +system.mem_ctrls.wrQLenPdf::2 1 +system.mem_ctrls.wrQLenPdf::3 1 +system.mem_ctrls.wrQLenPdf::4 1 +system.mem_ctrls.wrQLenPdf::5 1 +system.mem_ctrls.wrQLenPdf::6 1 +system.mem_ctrls.wrQLenPdf::7 1 +system.mem_ctrls.wrQLenPdf::8 1 +system.mem_ctrls.wrQLenPdf::9 1 +system.mem_ctrls.wrQLenPdf::10 1 +system.mem_ctrls.wrQLenPdf::11 1 +system.mem_ctrls.wrQLenPdf::12 1 +system.mem_ctrls.wrQLenPdf::13 1 +system.mem_ctrls.wrQLenPdf::14 1 +system.mem_ctrls.wrQLenPdf::15 482 +system.mem_ctrls.wrQLenPdf::16 585 +system.mem_ctrls.wrQLenPdf::17 3673 +system.mem_ctrls.wrQLenPdf::18 4294 +system.mem_ctrls.wrQLenPdf::19 4263 +system.mem_ctrls.wrQLenPdf::20 4407 +system.mem_ctrls.wrQLenPdf::21 4411 +system.mem_ctrls.wrQLenPdf::22 4319 +system.mem_ctrls.wrQLenPdf::23 4187 +system.mem_ctrls.wrQLenPdf::24 4183 +system.mem_ctrls.wrQLenPdf::25 4181 +system.mem_ctrls.wrQLenPdf::26 4182 +system.mem_ctrls.wrQLenPdf::27 4182 +system.mem_ctrls.wrQLenPdf::28 4181 +system.mem_ctrls.wrQLenPdf::29 4180 +system.mem_ctrls.wrQLenPdf::30 4179 +system.mem_ctrls.wrQLenPdf::31 4179 +system.mem_ctrls.wrQLenPdf::32 4178 +system.mem_ctrls.wrQLenPdf::33 0 +system.mem_ctrls.wrQLenPdf::34 0 +system.mem_ctrls.wrQLenPdf::35 0 +system.mem_ctrls.wrQLenPdf::36 0 +system.mem_ctrls.wrQLenPdf::37 0 +system.mem_ctrls.wrQLenPdf::38 0 +system.mem_ctrls.wrQLenPdf::39 0 +system.mem_ctrls.wrQLenPdf::40 0 +system.mem_ctrls.wrQLenPdf::41 0 +system.mem_ctrls.wrQLenPdf::42 0 +system.mem_ctrls.wrQLenPdf::43 0 +system.mem_ctrls.wrQLenPdf::44 0 +system.mem_ctrls.wrQLenPdf::45 0 +system.mem_ctrls.wrQLenPdf::46 0 +system.mem_ctrls.wrQLenPdf::47 0 +system.mem_ctrls.wrQLenPdf::48 0 +system.mem_ctrls.wrQLenPdf::49 0 +system.mem_ctrls.wrQLenPdf::50 0 +system.mem_ctrls.wrQLenPdf::51 0 +system.mem_ctrls.wrQLenPdf::52 0 +system.mem_ctrls.wrQLenPdf::53 0 +system.mem_ctrls.wrQLenPdf::54 0 +system.mem_ctrls.wrQLenPdf::55 0 +system.mem_ctrls.wrQLenPdf::56 0 +system.mem_ctrls.wrQLenPdf::57 0 +system.mem_ctrls.wrQLenPdf::58 0 +system.mem_ctrls.wrQLenPdf::59 0 +system.mem_ctrls.wrQLenPdf::60 0 +system.mem_ctrls.wrQLenPdf::61 0 +system.mem_ctrls.wrQLenPdf::62 0 +system.mem_ctrls.wrQLenPdf::63 0 +system.mem_ctrls.bytesPerActivate::samples 30658 +system.mem_ctrls.bytesPerActivate::mean 277.151020 +system.mem_ctrls.bytesPerActivate::gmean 189.288939 +system.mem_ctrls.bytesPerActivate::stdev 256.392048 +system.mem_ctrls.bytesPerActivate::0-127 8448 27.55% 27.55% +system.mem_ctrls.bytesPerActivate::128-255 9134 29.79% 57.34% +system.mem_ctrls.bytesPerActivate::256-383 4780 15.59% 72.94% +system.mem_ctrls.bytesPerActivate::384-511 3116 10.16% 83.10% +system.mem_ctrls.bytesPerActivate::512-639 1662 5.42% 88.52% +system.mem_ctrls.bytesPerActivate::640-767 996 3.24% 91.77% +system.mem_ctrls.bytesPerActivate::768-895 671 2.18% 93.96% +system.mem_ctrls.bytesPerActivate::896-1023 436 1.42% 95.38% +system.mem_ctrls.bytesPerActivate::1024-1151 1415 4.61% 99.99% +system.mem_ctrls.bytesPerActivate::total 30658 +system.mem_ctrls.rdPerTurnAround::samples 4178 +system.mem_ctrls.rdPerTurnAround::mean 15.443274 +system.mem_ctrls.rdPerTurnAround::gmean 15.386120 +system.mem_ctrls.rdPerTurnAround::stdev 1.345245 +system.mem_ctrls.rdPerTurnAround::12-13 259 6.19% 6.19% +system.mem_ctrls.rdPerTurnAround::14-15 1988 47.58% 53.78% +system.mem_ctrls.rdPerTurnAround::16-17 1671 39.99% 93.77% +system.mem_ctrls.rdPerTurnAround::18-19 242 5.79% 99.56% +system.mem_ctrls.rdPerTurnAround::20-21 17 0.40% 99.97% +system.mem_ctrls.rdPerTurnAround::32-33 1 0.02% 99.99% +system.mem_ctrls.rdPerTurnAround::total 4178 +system.mem_ctrls.wrPerTurnAround::samples 4178 +system.mem_ctrls.wrPerTurnAround::mean 16.331258 +system.mem_ctrls.wrPerTurnAround::gmean 16.311113 +system.mem_ctrls.wrPerTurnAround::stdev 0.843164 +system.mem_ctrls.wrPerTurnAround::16 3564 85.30% 85.30% +system.mem_ctrls.wrPerTurnAround::17 86 2.05% 87.36% +system.mem_ctrls.wrPerTurnAround::18 296 7.08% 94.44% +system.mem_ctrls.wrPerTurnAround::19 222 5.31% 99.76% +system.mem_ctrls.wrPerTurnAround::20 10 0.23% 99.99% +system.mem_ctrls.wrPerTurnAround::total 4178 +system.mem_ctrls.totQLat 1341576 +system.mem_ctrls.totMemAccLat 2567760 +system.mem_ctrls.totBusLat 322680 +system.mem_ctrls.avgQLat 20.78 +system.mem_ctrls.avgBusLat 5.00 +system.mem_ctrls.avgMemAccLat 39.78 +system.mem_ctrls.avgRdBW 501.57 +system.mem_ctrls.avgWrBW 530.29 +system.mem_ctrls.avgRdBWSys 914.20 +system.mem_ctrls.avgWrBWSys 914.17 +system.mem_ctrls.peakBW 12800.00 +system.mem_ctrls.busUtil 8.06 +system.mem_ctrls.busUtilRead 3.91 +system.mem_ctrls.busUtilWrite 4.14 +system.mem_ctrls.avgRdQLen 0.99 +system.mem_ctrls.avgWrQLen 25.97 +system.mem_ctrls.readRowHits 41328 +system.mem_ctrls.writeRowHits 60778 +system.mem_ctrls.readRowHitRate 64.03 +system.mem_ctrls.writeRowHitRate 89.03 +system.mem_ctrls.avgGap 35.00 +system.mem_ctrls.pageHitRate 76.88 +system.mem_ctrls_0.actEnergy 171045840 +system.mem_ctrls_0.preEnergy 92562120 +system.mem_ctrls_0.readEnergy 619135104 +system.mem_ctrls_0.writeEnergy 479772288 +system.mem_ctrls_0.refreshEnergy 650289120 +system.mem_ctrls_0.actBackEnergy 1172781840 +system.mem_ctrls_0.preBackEnergy 14185728 +system.mem_ctrls_0.actPowerDownEnergy 2505028704 +system.mem_ctrls_0.prePowerDownEnergy 38266752 +system.mem_ctrls_0.selfRefreshEnergy 10627920 +system.mem_ctrls_0.totalEnergy 5753695416 +system.mem_ctrls_0.averagePower 698.709434 +system.mem_ctrls_0.totalIdleTime 5625604 +system.mem_ctrls_0.memoryStateTime::IDLE 5830 +system.mem_ctrls_0.memoryStateTime::REF 275110 +system.mem_ctrls_0.memoryStateTime::SREF 32778 +system.mem_ctrls_0.memoryStateTime::PRE_PDN 99653 +system.mem_ctrls_0.memoryStateTime::ACT 2327892 +system.mem_ctrls_0.memoryStateTime::ACT_PDN 5493484 +system.mem_ctrls_1.actEnergy 47880840 +system.mem_ctrls_1.preEnergy 25900392 +system.mem_ctrls_1.readEnergy 118124160 +system.mem_ctrls_1.writeEnergy 90101376 +system.mem_ctrls_1.refreshEnergy 644757360 +system.mem_ctrls_1.actBackEnergy 878042136 +system.mem_ctrls_1.preBackEnergy 16141056 +system.mem_ctrls_1.actPowerDownEnergy 2454151872 +system.mem_ctrls_1.prePowerDownEnergy 293561472 +system.mem_ctrls_1.selfRefreshEnergy 33436536 +system.mem_ctrls_1.totalEnergy 4602109416 +system.mem_ctrls_1.averagePower 558.864700 +system.mem_ctrls_1.totalIdleTime 6267116 +system.mem_ctrls_1.memoryStateTime::IDLE 11825 +system.mem_ctrls_1.memoryStateTime::REF 272794 +system.mem_ctrls_1.memoryStateTime::SREF 120758 +system.mem_ctrls_1.memoryStateTime::PRE_PDN 764483 +system.mem_ctrls_1.memoryStateTime::ACT 1682975 +system.mem_ctrls_1.memoryStateTime::ACT_PDN 5381912 +system.pwrStateResidencyTicks::UNDEFINED 8234747 +system.cpu.clk_domain.clock 1 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 220 +system.cpu.pwrStateResidencyTicks::ON 8234747 +system.cpu.numCycles 8234747 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 434729 +system.cpu.committedOps 436032 +system.cpu.num_int_alu_accesses 433908 +system.cpu.num_fp_alu_accesses 1229 +system.cpu.num_vec_alu_accesses 0 +system.cpu.num_func_calls 23870 +system.cpu.num_conditional_control_insts 71049 +system.cpu.num_int_insts 433908 +system.cpu.num_fp_insts 1229 +system.cpu.num_vec_insts 0 +system.cpu.num_int_register_reads 549660 +system.cpu.num_int_register_writes 288600 +system.cpu.num_fp_register_reads 988 +system.cpu.num_fp_register_writes 800 +system.cpu.num_vec_register_reads 0 +system.cpu.num_vec_register_writes 0 +system.cpu.num_mem_refs 177168 +system.cpu.num_load_insts 110145 +system.cpu.num_store_insts 67023 +system.cpu.num_idle_cycles -0 +system.cpu.num_busy_cycles 8234747 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction -0 +system.cpu.Branches 94919 +system.cpu.op_class::No_OpClass 224 0.05% 0.05% +system.cpu.op_class::IntAlu 256681 58.83% 58.88% +system.cpu.op_class::IntMult 710 0.16% 59.05% +system.cpu.op_class::IntDiv 992 0.22% 59.27% +system.cpu.op_class::FloatAdd 133 0.03% 59.30% +system.cpu.op_class::FloatCmp 170 0.03% 59.34% +system.cpu.op_class::FloatCvt 128 0.02% 59.37% +system.cpu.op_class::FloatMult 30 0.00% 59.38% +system.cpu.op_class::FloatMultAcc 0 0.00% 59.38% +system.cpu.op_class::FloatDiv 11 0.00% 59.38% +system.cpu.op_class::FloatMisc 0 0.00% 59.38% +system.cpu.op_class::FloatSqrt 5 0.00% 59.38% +system.cpu.op_class::SimdAdd 0 0.00% 59.38% +system.cpu.op_class::SimdAddAcc 0 0.00% 59.38% +system.cpu.op_class::SimdAlu 0 0.00% 59.38% +system.cpu.op_class::SimdCmp 0 0.00% 59.38% +system.cpu.op_class::SimdCvt 0 0.00% 59.38% +system.cpu.op_class::SimdMisc 0 0.00% 59.38% +system.cpu.op_class::SimdMult 0 0.00% 59.38% +system.cpu.op_class::SimdMultAcc 0 0.00% 59.38% +system.cpu.op_class::SimdShift 0 0.00% 59.38% +system.cpu.op_class::SimdShiftAcc 0 0.00% 59.38% +system.cpu.op_class::SimdSqrt 0 0.00% 59.38% +system.cpu.op_class::SimdFloatAdd 0 0.00% 59.38% +system.cpu.op_class::SimdFloatAlu 0 0.00% 59.38% +system.cpu.op_class::SimdFloatCmp 0 0.00% 59.38% +system.cpu.op_class::SimdFloatCvt 0 0.00% 59.38% +system.cpu.op_class::SimdFloatDiv 0 0.00% 59.38% +system.cpu.op_class::SimdFloatMisc 0 0.00% 59.38% +system.cpu.op_class::SimdFloatMult 0 0.00% 59.38% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 59.38% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 59.38% +system.cpu.op_class::MemRead 109574 25.11% 84.50% +system.cpu.op_class::MemWrite 66842 15.32% 99.82% +system.cpu.op_class::FloatMemRead 571 0.13% 99.95% +system.cpu.op_class::FloatMemWrite 181 0.04% 99.99% +system.cpu.op_class::IprAccess 0 0.00% 99.99% +system.cpu.op_class::InstPrefetch 0 0.00% 99.99% +system.cpu.op_class::total 436252 +system.ruby.clk_domain.clock 1 +system.ruby.pwrStateResidencyTicks::UNDEFINED 8234747 +system.ruby.delayHist::bucket_size 1 +system.ruby.delayHist::max_bucket 9 +system.ruby.delayHist::samples 235254 +system.ruby.delayHist | 235254 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayHist::total 235254 system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 417744 +system.ruby.outstanding_req_hist_seqr::samples 687573 system.ruby.outstanding_req_hist_seqr::mean 1 system.ruby.outstanding_req_hist_seqr::gmean 1 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 417744 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 417744 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 687573 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 687573 system.ruby.latency_hist_seqr::bucket_size 64 system.ruby.latency_hist_seqr::max_bucket 639 -system.ruby.latency_hist_seqr::samples 417743 -system.ruby.latency_hist_seqr::mean 14.304941 -system.ruby.latency_hist_seqr::gmean 2.506373 -system.ruby.latency_hist_seqr::stdev 29.993401 -system.ruby.latency_hist_seqr | 367877 88.06% 88.06% | 46330 11.09% 99.15% | 2431 0.58% 99.74% | 380 0.09% 99.83% | 382 0.09% 99.92% | 309 0.07% 99.99% | 15 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 16 0.00% 100.00% -system.ruby.latency_hist_seqr::total 417743 +system.ruby.latency_hist_seqr::samples 687572 +system.ruby.latency_hist_seqr::mean 10.976559 +system.ruby.latency_hist_seqr::gmean 1.966066 +system.ruby.latency_hist_seqr::stdev 26.793113 +system.ruby.latency_hist_seqr | 624767 90.86% 90.86% | 58473 8.50% 99.36% | 3023 0.43% 99.80% | 487 0.07% 99.88% | 421 0.06% 99.94% | 338 0.04% 99.99% | 32 0.00% 99.99% | 14 0.00% 99.99% | 4 0.00% 99.99% | 13 0.00% 99.99% +system.ruby.latency_hist_seqr::total 687572 system.ruby.hit_latency_hist_seqr::bucket_size 1 system.ruby.hit_latency_hist_seqr::max_bucket 9 -system.ruby.hit_latency_hist_seqr::samples 319983 +system.ruby.hit_latency_hist_seqr::samples 569943 system.ruby.hit_latency_hist_seqr::mean 1 system.ruby.hit_latency_hist_seqr::gmean 1 -system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 319983 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 319983 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 569943 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 569943 system.ruby.miss_latency_hist_seqr::bucket_size 64 system.ruby.miss_latency_hist_seqr::max_bucket 639 -system.ruby.miss_latency_hist_seqr::samples 97760 -system.ruby.miss_latency_hist_seqr::mean 57.853989 -system.ruby.miss_latency_hist_seqr::gmean 50.720255 -system.ruby.miss_latency_hist_seqr::stdev 36.989317 -system.ruby.miss_latency_hist_seqr | 47894 48.99% 48.99% | 46330 47.39% 96.38% | 2431 2.49% 98.87% | 380 0.39% 99.26% | 382 0.39% 99.65% | 309 0.32% 99.97% | 15 0.02% 99.98% | 3 0.00% 99.98% | 0 0.00% 99.98% | 16 0.02% 100.00% -system.ruby.miss_latency_hist_seqr::total 97760 -system.ruby.Directory.incomplete_times_seqr 97759 -system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.015290 # Average number of messages in buffer -system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.999944 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.030580 # Average number of messages in buffer -system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.755056 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.015290 # Average number of messages in buffer -system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999989 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.030580 # Average number of messages in buffer -system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999989 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.cacheMemory.demand_hits 319983 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 97760 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 417743 # Number of cache demand accesses -system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.015290 # Average number of messages in buffer -system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.999599 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.065339 # Average number of messages in buffer -system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 1.000000 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.061161 # Average number of messages in buffer -system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999999 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.015290 # Average number of messages in buffer -system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.999918 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.015290 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers03.avg_stall_time 5.999657 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.015290 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers04.avg_stall_time 5.999931 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.091740 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers07.avg_stall_time 6.755068 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 7.645070 -system.ruby.network.routers0.msg_count.Control::2 97760 -system.ruby.network.routers0.msg_count.Data::2 97756 -system.ruby.network.routers0.msg_count.Response_Data::4 97760 -system.ruby.network.routers0.msg_count.Writeback_Control::3 97756 -system.ruby.network.routers0.msg_bytes.Control::2 782080 -system.ruby.network.routers0.msg_bytes.Data::2 7038432 -system.ruby.network.routers0.msg_bytes.Response_Data::4 7038720 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 782048 -system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.030580 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers02.avg_stall_time 10.755059 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.015290 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers06.avg_stall_time 1.999887 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.015290 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers07.avg_stall_time 1.999978 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 7.645070 -system.ruby.network.routers1.msg_count.Control::2 97760 -system.ruby.network.routers1.msg_count.Data::2 97756 -system.ruby.network.routers1.msg_count.Response_Data::4 97760 -system.ruby.network.routers1.msg_count.Writeback_Control::3 97756 -system.ruby.network.routers1.msg_bytes.Control::2 782080 -system.ruby.network.routers1.msg_bytes.Data::2 7038432 -system.ruby.network.routers1.msg_bytes.Response_Data::4 7038720 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 782048 -system.ruby.network.int_link_buffers02.avg_buf_msgs 0.030580 # Average number of messages in buffer -system.ruby.network.int_link_buffers02.avg_stall_time 7.755066 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers08.avg_buf_msgs 0.015290 # Average number of messages in buffer -system.ruby.network.int_link_buffers08.avg_stall_time 2.999830 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers09.avg_buf_msgs 0.015290 # Average number of messages in buffer -system.ruby.network.int_link_buffers09.avg_stall_time 2.999967 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers13.avg_buf_msgs 0.015290 # Average number of messages in buffer -system.ruby.network.int_link_buffers13.avg_stall_time 4.999715 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers14.avg_buf_msgs 0.015290 # Average number of messages in buffer -system.ruby.network.int_link_buffers14.avg_stall_time 4.999943 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers17.avg_buf_msgs 0.030580 # Average number of messages in buffer -system.ruby.network.int_link_buffers17.avg_stall_time 9.755062 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.015290 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers03.avg_stall_time 3.999773 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.015290 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers04.avg_stall_time 3.999955 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.030580 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers07.avg_stall_time 8.755064 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 7.645070 -system.ruby.network.routers2.msg_count.Control::2 97760 -system.ruby.network.routers2.msg_count.Data::2 97756 -system.ruby.network.routers2.msg_count.Response_Data::4 97760 -system.ruby.network.routers2.msg_count.Writeback_Control::3 97756 -system.ruby.network.routers2.msg_bytes.Control::2 782080 -system.ruby.network.routers2.msg_bytes.Data::2 7038432 -system.ruby.network.routers2.msg_bytes.Response_Data::4 7038720 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 782048 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Control 293280 -system.ruby.network.msg_count.Data 293268 -system.ruby.network.msg_count.Response_Data 293280 -system.ruby.network.msg_count.Writeback_Control 293268 -system.ruby.network.msg_byte.Control 2346240 -system.ruby.network.msg_byte.Data 21115296 -system.ruby.network.msg_byte.Response_Data 21116160 -system.ruby.network.msg_byte.Writeback_Control 2346144 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 7.645195 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 97760 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 97756 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 7038720 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 782048 -system.ruby.network.routers0.throttle1.link_utilization 7.644945 -system.ruby.network.routers0.throttle1.msg_count.Control::2 97760 -system.ruby.network.routers0.throttle1.msg_count.Data::2 97756 -system.ruby.network.routers0.throttle1.msg_bytes.Control::2 782080 -system.ruby.network.routers0.throttle1.msg_bytes.Data::2 7038432 -system.ruby.network.routers1.throttle0.link_utilization 7.644945 -system.ruby.network.routers1.throttle0.msg_count.Control::2 97760 -system.ruby.network.routers1.throttle0.msg_count.Data::2 97756 -system.ruby.network.routers1.throttle0.msg_bytes.Control::2 782080 -system.ruby.network.routers1.throttle0.msg_bytes.Data::2 7038432 -system.ruby.network.routers1.throttle1.link_utilization 7.645195 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 97760 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 97756 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 7038720 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 782048 -system.ruby.network.routers2.throttle0.link_utilization 7.645195 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 97760 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 97756 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 7038720 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 782048 -system.ruby.network.routers2.throttle1.link_utilization 7.644945 -system.ruby.network.routers2.throttle1.msg_count.Control::2 97760 -system.ruby.network.routers2.throttle1.msg_count.Data::2 97756 -system.ruby.network.routers2.throttle1.msg_bytes.Control::2 782080 -system.ruby.network.routers2.throttle1.msg_bytes.Data::2 7038432 -system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 97760 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 97760 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 97760 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 97756 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 97756 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 97756 # delay histogram for vnet_2 +system.ruby.miss_latency_hist_seqr::samples 117629 +system.ruby.miss_latency_hist_seqr::mean 59.315576 +system.ruby.miss_latency_hist_seqr::gmean 52.018516 +system.ruby.miss_latency_hist_seqr::stdev 37.111044 +system.ruby.miss_latency_hist_seqr | 54824 46.60% 46.60% | 58473 49.70% 96.31% | 3023 2.56% 98.88% | 487 0.41% 99.30% | 421 0.35% 99.65% | 338 0.28% 99.94% | 32 0.02% 99.97% | 14 0.01% 99.98% | 4 0.00% 99.98% | 13 0.01% 99.99% +system.ruby.miss_latency_hist_seqr::total 117629 +system.ruby.Directory.incomplete_times_seqr 117628 +system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.014283 +system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.999964 +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.028568 +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.771273 +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.014284 +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999991 +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.028568 +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999991 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 8234747 +system.ruby.l1_cntrl0.cacheMemory.demand_hits 569943 +system.ruby.l1_cntrl0.cacheMemory.demand_misses 117629 +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 687572 +system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.014283 +system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.999743 +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.083496 +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999999 +system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.057136 +system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999999 +system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.014284 +system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.999936 +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 8234747 +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 8234747 +system.ruby.memctrl_clk_domain.clock 3 +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.014283 +system.ruby.network.routers0.port_buffers03.avg_stall_time 5.999780 +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.014284 +system.ruby.network.routers0.port_buffers04.avg_stall_time 5.999946 +system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.085704 +system.ruby.network.routers0.port_buffers07.avg_stall_time 6.771282 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 8234747 +system.ruby.network.routers0.percent_links_utilized 7.142113 +system.ruby.network.routers0.msg_count.Control::2 117629 +system.ruby.network.routers0.msg_count.Data::2 117625 +system.ruby.network.routers0.msg_count.Response_Data::4 117629 +system.ruby.network.routers0.msg_count.Writeback_Control::3 117625 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0.028568 +system.ruby.network.int_link_buffers17.avg_stall_time 9.771277 +system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.014283 +system.ruby.network.routers2.port_buffers03.avg_stall_time 3.999854 +system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.014284 +system.ruby.network.routers2.port_buffers04.avg_stall_time 3.999965 +system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.028568 +system.ruby.network.routers2.port_buffers07.avg_stall_time 8.771279 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 8234747 +system.ruby.network.routers2.percent_links_utilized 7.142113 +system.ruby.network.routers2.msg_count.Control::2 117629 +system.ruby.network.routers2.msg_count.Data::2 117625 +system.ruby.network.routers2.msg_count.Response_Data::4 117629 +system.ruby.network.routers2.msg_count.Writeback_Control::3 117625 +system.ruby.network.routers2.msg_bytes.Control::2 941032 +system.ruby.network.routers2.msg_bytes.Data::2 8469000 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-system.ruby.LD.latency_hist_seqr | 55897 80.03% 80.03% | 12888 18.45% 98.49% | 741 1.06% 99.55% | 131 0.19% 99.73% | 105 0.15% 99.88% | 76 0.11% 99.99% | 4 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% -system.ruby.LD.latency_hist_seqr::total 69843 +system.ruby.LD.latency_hist_seqr::samples 108386 +system.ruby.LD.latency_hist_seqr::mean 27.548825 +system.ruby.LD.latency_hist_seqr::gmean 6.786879 +system.ruby.LD.latency_hist_seqr::stdev 36.533101 +system.ruby.LD.latency_hist_seqr | 85531 78.91% 78.91% | 21323 19.67% 98.58% | 1014 0.93% 99.52% | 217 0.20% 99.72% | 165 0.15% 99.87% | 114 0.10% 99.97% | 9 0.00% 99.98% | 4 0.00% 99.99% | 4 0.00% 99.99% | 5 0.00% 99.99% +system.ruby.LD.latency_hist_seqr::total 108386 system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 -system.ruby.LD.hit_latency_hist_seqr::samples 33083 +system.ruby.LD.hit_latency_hist_seqr::samples 54696 system.ruby.LD.hit_latency_hist_seqr::mean 1 system.ruby.LD.hit_latency_hist_seqr::gmean 1 -system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 33083 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 33083 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 54696 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 54696 system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 -system.ruby.LD.miss_latency_hist_seqr::samples 36760 -system.ruby.LD.miss_latency_hist_seqr::mean 52.911425 -system.ruby.LD.miss_latency_hist_seqr::gmean 46.109058 -system.ruby.LD.miss_latency_hist_seqr::stdev 34.651513 -system.ruby.LD.miss_latency_hist_seqr | 22814 62.06% 62.06% | 12888 35.06% 97.12% | 741 2.02% 99.14% | 131 0.36% 99.49% | 105 0.29% 99.78% | 76 0.21% 99.99% | 4 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 36760 +system.ruby.LD.miss_latency_hist_seqr::samples 53690 +system.ruby.LD.miss_latency_hist_seqr::mean 54.595101 +system.ruby.LD.miss_latency_hist_seqr::gmean 47.744503 +system.ruby.LD.miss_latency_hist_seqr::stdev 35.281629 +system.ruby.LD.miss_latency_hist_seqr | 30835 57.43% 57.43% | 21323 39.71% 97.14% | 1014 1.88% 99.03% | 217 0.40% 99.43% | 165 0.30% 99.74% | 114 0.21% 99.95% | 9 0.01% 99.97% | 4 0.00% 99.98% | 4 0.00% 99.99% | 5 0.00% 99.99% +system.ruby.LD.miss_latency_hist_seqr::total 53690 system.ruby.ST.latency_hist_seqr::bucket_size 64 system.ruby.ST.latency_hist_seqr::max_bucket 639 -system.ruby.ST.latency_hist_seqr::samples 48546 -system.ruby.ST.latency_hist_seqr::mean 14.735838 -system.ruby.ST.latency_hist_seqr::gmean 3.058930 -system.ruby.ST.latency_hist_seqr::stdev 27.657147 -system.ruby.ST.latency_hist_seqr | 44298 91.25% 91.25% | 3958 8.15% 99.40% | 180 0.37% 99.77% | 35 0.07% 99.85% | 42 0.09% 99.93% | 23 0.05% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 10 0.02% 100.00% -system.ruby.ST.latency_hist_seqr::total 48546 +system.ruby.ST.latency_hist_seqr::samples 65264 +system.ruby.ST.latency_hist_seqr::mean 14.266318 +system.ruby.ST.latency_hist_seqr::gmean 2.785713 +system.ruby.ST.latency_hist_seqr::stdev 27.810593 +system.ruby.ST.latency_hist_seqr | 59018 90.42% 90.42% | 5726 8.77% 99.20% | 421 0.64% 99.84% | 27 0.04% 99.88% | 36 0.05% 99.94% | 25 0.03% 99.98% | 4 0.00% 99.98% | 2 0.00% 99.99% | 0 0.00% 99.99% | 5 0.00% 99.99% +system.ruby.ST.latency_hist_seqr::total 65264 system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 -system.ruby.ST.hit_latency_hist_seqr::samples 33996 +system.ruby.ST.hit_latency_hist_seqr::samples 47606 system.ruby.ST.hit_latency_hist_seqr::mean 1 system.ruby.ST.hit_latency_hist_seqr::gmean 1 -system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 33996 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist_seqr::total 33996 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 47606 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 47606 system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 -system.ruby.ST.miss_latency_hist_seqr::samples 14550 -system.ruby.ST.miss_latency_hist_seqr::mean 46.829553 -system.ruby.ST.miss_latency_hist_seqr::gmean 41.696554 -system.ruby.ST.miss_latency_hist_seqr::stdev 32.883513 -system.ruby.ST.miss_latency_hist_seqr | 10302 70.80% 70.80% | 3958 27.20% 98.01% | 180 1.24% 99.24% | 35 0.24% 99.48% | 42 0.29% 99.77% | 23 0.16% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 10 0.07% 100.00% -system.ruby.ST.miss_latency_hist_seqr::total 14550 +system.ruby.ST.miss_latency_hist_seqr::samples 17658 +system.ruby.ST.miss_latency_hist_seqr::mean 50.032336 +system.ruby.ST.miss_latency_hist_seqr::gmean 44.104829 +system.ruby.ST.miss_latency_hist_seqr::stdev 33.240377 +system.ruby.ST.miss_latency_hist_seqr | 11412 64.62% 64.62% | 5726 32.42% 97.05% | 421 2.38% 99.43% | 27 0.15% 99.59% | 36 0.20% 99.79% | 25 0.14% 99.93% | 4 0.02% 99.96% | 2 0.01% 99.97% | 0 0.00% 99.97% | 5 0.02% 99.99% +system.ruby.ST.miss_latency_hist_seqr::total 17658 system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.latency_hist_seqr::samples 299354 -system.ruby.IFETCH.latency_hist_seqr::mean 10.964664 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.878483 -system.ruby.IFETCH.latency_hist_seqr::stdev 27.751002 -system.ruby.IFETCH.latency_hist_seqr | 267682 89.42% 89.42% | 29484 9.85% 99.27% | 1510 0.50% 99.77% | 214 0.07% 99.84% | 235 0.08% 99.92% | 210 0.07% 99.99% | 11 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 5 0.00% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 299354 +system.ruby.IFETCH.latency_hist_seqr::samples 510404 +system.ruby.IFETCH.latency_hist_seqr::mean 7.102352 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.451746 +system.ruby.IFETCH.latency_hist_seqr::stdev 22.563215 +system.ruby.IFETCH.latency_hist_seqr | 476703 93.39% 93.39% | 31422 6.15% 99.55% | 1588 0.31% 99.86% | 243 0.04% 99.91% | 220 0.04% 99.95% | 198 0.03% 99.99% | 19 0.00% 99.99% | 8 0.00% 99.99% | 0 0.00% 99.99% | 3 0.00% 99.99% +system.ruby.IFETCH.latency_hist_seqr::total 510404 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 252904 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 464162 system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 -system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 252904 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 252904 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 464162 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 464162 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.miss_latency_hist_seqr::samples 46450 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 65.218773 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 58.155656 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 38.458091 -system.ruby.IFETCH.miss_latency_hist_seqr | 14778 31.81% 31.81% | 29484 63.47% 95.29% | 1510 3.25% 98.54% | 214 0.46% 99.00% | 235 0.51% 99.51% | 210 0.45% 99.96% | 11 0.02% 99.98% | 3 0.01% 99.99% | 0 0.00% 99.99% | 5 0.01% 100.00% -system.ruby.IFETCH.miss_latency_hist_seqr::total 46450 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 46242 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 68.355758 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 61.220522 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 38.646033 +system.ruby.IFETCH.miss_latency_hist_seqr | 12541 27.12% 27.12% | 31422 67.95% 95.07% | 1588 3.43% 98.50% | 243 0.52% 99.03% | 220 0.47% 99.50% | 198 0.42% 99.93% | 19 0.04% 99.97% | 8 0.01% 99.99% | 0 0.00% 99.99% | 3 0.00% 99.99% +system.ruby.IFETCH.miss_latency_hist_seqr::total 46242 +system.ruby.Load_Linked.latency_hist_seqr::bucket_size 64 +system.ruby.Load_Linked.latency_hist_seqr::max_bucket 639 +system.ruby.Load_Linked.latency_hist_seqr::samples 1759 +system.ruby.Load_Linked.latency_hist_seqr::mean 1.911881 +system.ruby.Load_Linked.latency_hist_seqr::gmean 1.082444 +system.ruby.Load_Linked.latency_hist_seqr::stdev 9.344784 +system.ruby.Load_Linked.latency_hist_seqr | 1756 99.82% 99.82% | 2 0.11% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 1 0.05% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% +system.ruby.Load_Linked.latency_hist_seqr::total 1759 +system.ruby.Load_Linked.hit_latency_hist_seqr::bucket_size 1 +system.ruby.Load_Linked.hit_latency_hist_seqr::max_bucket 9 +system.ruby.Load_Linked.hit_latency_hist_seqr::samples 1720 +system.ruby.Load_Linked.hit_latency_hist_seqr::mean 1 +system.ruby.Load_Linked.hit_latency_hist_seqr::gmean 1 +system.ruby.Load_Linked.hit_latency_hist_seqr | 0 0.00% 0.00% | 1720 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Load_Linked.hit_latency_hist_seqr::total 1720 +system.ruby.Load_Linked.miss_latency_hist_seqr::bucket_size 64 +system.ruby.Load_Linked.miss_latency_hist_seqr::max_bucket 639 +system.ruby.Load_Linked.miss_latency_hist_seqr::samples 39 +system.ruby.Load_Linked.miss_latency_hist_seqr::mean 42.128205 +system.ruby.Load_Linked.miss_latency_hist_seqr::gmean 35.627366 +system.ruby.Load_Linked.miss_latency_hist_seqr::stdev 48.398118 +system.ruby.Load_Linked.miss_latency_hist_seqr | 36 92.30% 92.30% | 2 5.12% 97.43% | 0 0.00% 97.43% | 0 0.00% 97.43% | 0 0.00% 97.43% | 1 2.56% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% +system.ruby.Load_Linked.miss_latency_hist_seqr::total 39 +system.ruby.Store_Conditional.latency_hist_seqr::bucket_size 1 +system.ruby.Store_Conditional.latency_hist_seqr::max_bucket 9 +system.ruby.Store_Conditional.latency_hist_seqr::samples 1759 +system.ruby.Store_Conditional.latency_hist_seqr::mean 1 +system.ruby.Store_Conditional.latency_hist_seqr::gmean 1 +system.ruby.Store_Conditional.latency_hist_seqr | 0 0.00% 0.00% | 1759 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Store_Conditional.latency_hist_seqr::total 1759 +system.ruby.Store_Conditional.hit_latency_hist_seqr::bucket_size 1 +system.ruby.Store_Conditional.hit_latency_hist_seqr::max_bucket 9 +system.ruby.Store_Conditional.hit_latency_hist_seqr::samples 1759 +system.ruby.Store_Conditional.hit_latency_hist_seqr::mean 1 +system.ruby.Store_Conditional.hit_latency_hist_seqr::gmean 1 +system.ruby.Store_Conditional.hit_latency_hist_seqr | 0 0.00% 0.00% | 1759 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Store_Conditional.hit_latency_hist_seqr::total 1759 system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 -system.ruby.Directory.miss_mach_latency_hist_seqr::samples 97760 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 57.853989 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 50.720255 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 36.989317 -system.ruby.Directory.miss_mach_latency_hist_seqr | 47894 48.99% 48.99% | 46330 47.39% 96.38% | 2431 2.49% 98.87% | 380 0.39% 99.26% | 382 0.39% 99.65% | 309 0.32% 99.97% | 15 0.02% 99.98% | 3 0.00% 99.98% | 0 0.00% 99.98% | 16 0.02% 100.00% -system.ruby.Directory.miss_mach_latency_hist_seqr::total 97760 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 117629 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 59.315576 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 52.018516 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 37.111044 +system.ruby.Directory.miss_mach_latency_hist_seqr | 54824 46.60% 46.60% | 58473 49.70% 96.31% | 3023 2.56% 98.88% | 487 0.41% 99.30% | 421 0.35% 99.65% | 338 0.28% 99.94% | 32 0.02% 99.97% | 14 0.01% 99.98% | 4 0.00% 99.98% | 13 0.01% 99.99% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 117629 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 @@ -635,57 +675,65 @@ system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucke system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 74.999999 system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 36760 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 52.911425 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 46.109058 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 34.651513 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 22814 62.06% 62.06% | 12888 35.06% 97.12% | 741 2.02% 99.14% | 131 0.36% 99.49% | 105 0.29% 99.78% | 76 0.21% 99.99% | 4 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 36760 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 53690 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 54.595101 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 47.744503 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 35.281629 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 30835 57.43% 57.43% | 21323 39.71% 97.14% | 1014 1.88% 99.03% | 217 0.40% 99.43% | 165 0.30% 99.74% | 114 0.21% 99.95% | 9 0.01% 99.97% | 4 0.00% 99.98% | 4 0.00% 99.99% | 5 0.00% 99.99% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 53690 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 14550 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 46.829553 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 41.696554 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 32.883513 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 10302 70.80% 70.80% | 3958 27.20% 98.01% | 180 1.24% 99.24% | 35 0.24% 99.48% | 42 0.29% 99.77% | 23 0.16% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 10 0.07% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 14550 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 17658 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 50.032336 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 44.104829 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 33.240377 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 11412 64.62% 64.62% | 5726 32.42% 97.05% | 421 2.38% 99.43% | 27 0.15% 99.59% | 36 0.20% 99.79% | 25 0.14% 99.93% | 4 0.02% 99.96% | 2 0.01% 99.97% | 0 0.00% 99.97% | 5 0.02% 99.99% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 17658 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 46450 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 65.218773 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 58.155656 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 38.458091 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 14778 31.81% 31.81% | 29484 63.47% 95.29% | 1510 3.25% 98.54% | 214 0.46% 99.00% | 235 0.51% 99.51% | 210 0.45% 99.96% | 11 0.02% 99.98% | 3 0.01% 99.99% | 0 0.00% 99.99% | 5 0.01% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 46450 -system.ruby.Directory_Controller.GETX 97760 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 97756 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 97760 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 97756 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 97760 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 97756 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 97760 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 97756 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 69843 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 299354 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 48546 0.00% 0.00% -system.ruby.L1Cache_Controller.Data 97760 0.00% 0.00% -system.ruby.L1Cache_Controller.Replacement 97756 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack 97756 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 36760 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Ifetch 46450 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Store 14550 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Load 33083 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 252904 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Store 33996 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Replacement 97756 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack 97756 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data 83210 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Data 14550 0.00% 0.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 46242 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 68.355758 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 61.220522 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 38.646033 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 12541 27.12% 27.12% | 31422 67.95% 95.07% | 1588 3.43% 98.50% | 243 0.52% 99.03% | 220 0.47% 99.50% | 198 0.42% 99.93% | 19 0.04% 99.97% | 8 0.01% 99.99% | 0 0.00% 99.99% | 3 0.00% 99.99% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 46242 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::samples 39 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::mean 42.128205 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::gmean 35.627366 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::stdev 48.398118 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr | 36 92.30% 92.30% | 2 5.12% 97.43% | 0 0.00% 97.43% | 0 0.00% 97.43% | 0 0.00% 97.43% | 1 2.56% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::total 39 +system.ruby.Directory_Controller.GETX 117629 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 117625 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 117629 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 117625 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 117629 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 117625 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 117629 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 117625 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 108386 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 510404 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 68782 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 117629 0.00% 0.00% +system.ruby.L1Cache_Controller.Replacement 117625 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 117625 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 53690 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 46242 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 17697 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 54696 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 464162 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Store 51085 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Replacement 117625 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 117625 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 99932 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data 17697 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/config.ini index be13c3ba9..1f2242b23 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/config.ini @@ -85,8 +85,10 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer +wait_for_remote_gdb=false workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side @@ -287,7 +289,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=insttest cwd= drivers= @@ -296,14 +298,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/config.json index 382338e98..633548a7c 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/config.json +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/config.json @@ -292,6 +292,7 @@ }, "p_state_clk_gate_bins": 20, "p_state_clk_gate_min": 1000, + "syscallRetryLatency": 10000, "interrupts": [ { "eventq_index": 0, @@ -376,21 +377,22 @@ "uid": 100, "pid": 100, "kvmInSE": false, - "cxx_class": "LiveProcess", - "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest", + "cxx_class": "Process", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest", "drivers": [], "system": "system", "gid": 100, "eventq_index": 0, "env": [], - "input": "cin", - "ppid": 99, - "type": "LiveProcess", + "maxStackSize": 67108864, + "ppid": 0, + "type": "Process", "cwd": "", + "pgid": 100, "simpoint": 0, "euid": 100, + "input": "cin", "path": "system.cpu.workload", - "max_stack_size": 67108864, "name": "workload", "cmd": [ "insttest" @@ -402,6 +404,7 @@ } ], "name": "cpu", + "wait_for_remote_gdb": false, "dtb": { "name": "dtb", "eventq_index": 0, diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/simerr index fd133b12b..1b7fba635 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/simerr +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/simerr @@ -1,3 +1,5 @@ -warn: Unknown operating system; assuming Linux. warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings. + Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest' +info: Increasing stack size by one page. diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/simout index 709d5c6f6..0cf571c48 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/simout +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/simout @@ -3,14 +3,12 @@ Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv6 gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 30 2016 14:33:35 -gem5 started Nov 30 2016 16:18:31 -gem5 executing on zizzer, pid 34073 -command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/simple-timing +gem5 compiled Jul 13 2017 17:09:45 +gem5 started Jul 13 2017 17:11:34 +gem5 executing on boldrock, pid 1863 +command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. fld: PASS fsd: PASS fmadd.d: PASS @@ -165,4 +163,62 @@ fcvt.w.d, truncate negative: PASS fcvt.w.d, 0.0: PASS fcvt.w.d, -0.0: PASS fcvt.w.d, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) -Exiting @ tick 497165500 because target called exit() +fcvt.w.d, underflow: PASS +fcvt.w.d, infinity: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +fcvt.w.d, -infinity: PASS +fcvt.w.d, quiet NaN: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +fcvt.w.d, quiet -NaN: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +fcvt.w.d, signaling NaN: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +fcvt.wu.d, truncate positive: PASS +fcvt.wu.d, truncate negative: PASS +fcvt.wu.d, 0.0: PASS +fcvt.wu.d, -0.0: PASS +fcvt.wu.d, overflow: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.d, underflow: PASS +fcvt.wu.d, infinity: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.d, -infinity: PASS +fcvt.wu.d, quiet NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.d, quiet -NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.d, signaling NaN: PASS +fcvt.d.w, 0: PASS +fcvt.d.w, negative: PASS +fcvt.d.w, truncate: PASS +fcvt.d.wu, 0: PASS +fcvt.d.wu: PASS +fcvt.d.wu, truncate: PASS +fcvt.l.d, truncate positive: PASS +fcvt.l.d, truncate negative: PASS +fcvt.l.d, 0.0: PASS +fcvt.l.d, -0.0: PASS +fcvt.l.d, 32-bit overflow: PASS +fcvt.l.d, overflow: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.l.d, underflow: PASS +fcvt.l.d, infinity: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.l.d, -infinity: PASS +fcvt.l.d, quiet NaN: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.l.d, quiet -NaN: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.l.d, signaling NaN: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.lu.d, truncate positive: PASS +fcvt.lu.d, truncate negative: PASS +fcvt.lu.d, 0.0: PASS +fcvt.lu.d, -0.0: PASS +fcvt.lu.d, 32-bit overflow: PASS +fcvt.lu.d, overflow: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.lu.d, underflow: PASS +fcvt.lu.d, infinity: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.lu.d, -infinity: PASS +fcvt.lu.d, quiet NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 9223372036854775808) +fcvt.lu.d, quiet -NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 9223372036854775808) +fcvt.lu.d, signaling NaN: PASS +fmv.x.d, positive: PASS +fmv.x.d, negative: PASS +fmv.x.d, 0.0: PASS +fmv.x.d, -0.0: PASS +fcvt.d.l, 0: PASS +fcvt.d.l, negative: PASS +fcvt.d.l, 32-bit truncate: PASS +fcvt.d.lu, 0: PASS +fcvt.d.lu: PASS +fcvt.d.lu, 32-bit truncate: PASS +fmv.d.x: PASS +Exiting @ tick 787032500 because exiting with last active thread context diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/stats.txt index e0a5b9af7..46c49ad51 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/stats.txt @@ -1,515 +1,556 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000497 # Number of seconds simulated -sim_ticks 497165500 # Number of ticks simulated -final_tick 497165500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 27513 # Simulator instruction rate (inst/s) -host_op_rate 27513 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45717681 # Simulator tick rate (ticks/s) -host_mem_usage 243824 # Number of bytes of host memory used -host_seconds 10.87 # Real time elapsed on the host -sim_insts 299191 # Number of instructions simulated -sim_ops 299191 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 61760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 20224 # Number of bytes read from this memory -system.physmem.bytes_read::total 81984 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61760 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 965 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 316 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1281 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 124224227 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 40678607 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 164902834 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 124224227 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 124224227 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 124224227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 40678607 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 164902834 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 162 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 497165500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 994331 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 299191 # Number of instructions committed -system.cpu.committedOps 299191 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 299008 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 1025 # Number of float alu accesses -system.cpu.num_func_calls 21816 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 44561 # number of instructions that are conditional controls -system.cpu.num_int_insts 299008 # number of integer instructions -system.cpu.num_fp_insts 1025 # number of float instructions -system.cpu.num_int_register_reads 394163 # number of times the integer registers were read -system.cpu.num_int_register_writes 205779 # number of times the integer registers were written -system.cpu.num_fp_register_reads 851 # number of times the floating registers were read -system.cpu.num_fp_register_writes 688 # number of times the floating registers were written -system.cpu.num_mem_refs 118390 # number of memory refs -system.cpu.num_load_insts 69843 # Number of load instructions -system.cpu.num_store_insts 48547 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 994331 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 66377 # Number of branches fetched -system.cpu.op_class::No_OpClass 162 0.05% 0.05% # Class of executed instruction -system.cpu.op_class::IntAlu 179913 60.10% 60.15% # Class of executed instruction -system.cpu.op_class::IntMult 466 0.16% 60.31% # Class of executed instruction -system.cpu.op_class::IntDiv 40 0.01% 60.32% # Class of executed instruction -system.cpu.op_class::FloatAdd 120 0.04% 60.36% # Class of executed instruction -system.cpu.op_class::FloatCmp 157 0.05% 60.42% # Class of executed instruction -system.cpu.op_class::FloatCvt 60 0.02% 60.44% # Class of executed instruction -system.cpu.op_class::FloatMult 30 0.01% 60.45% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::FloatDiv 11 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::FloatSqrt 5 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.45% # Class of executed instruction -system.cpu.op_class::MemRead 69348 23.17% 83.62% # Class of executed instruction -system.cpu.op_class::MemWrite 48400 16.17% 99.79% # Class of executed instruction -system.cpu.op_class::FloatMemRead 495 0.17% 99.95% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 147 0.05% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 299354 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 258.453748 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 118073 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 316 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 373.648734 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 258.453748 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.063099 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.063099 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 316 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 296 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.077148 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 237094 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 237094 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 69732 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 69732 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 48341 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 48341 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 118073 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 118073 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 118073 # number of overall hits -system.cpu.dcache.overall_hits::total 118073 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 111 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 111 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 205 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 205 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 316 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 316 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 316 # number of overall misses -system.cpu.dcache.overall_misses::total 316 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6993000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6993000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12915000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12915000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19908000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19908000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19908000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19908000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 69843 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 69843 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 48546 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 48546 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 118389 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 118389 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 118389 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 118389 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001589 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.001589 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004223 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.004223 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002669 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002669 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002669 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002669 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 111 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 111 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 205 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 205 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 316 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 316 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 316 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 316 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6882000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6882000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12710000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12710000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19592000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 19592000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19592000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 19592000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001589 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001589 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004223 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004223 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002669 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002669 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002669 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002669 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 26 # number of replacements -system.cpu.icache.tags.tagsinuse 551.353598 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 298390 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 965 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 309.212435 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 551.353598 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.269216 # Average percentage of cache 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-system.cpu.icache.demand_miss_latency::total 60795500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 60795500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 60795500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 299355 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 299355 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 299355 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 299355 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 299355 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 299355 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003224 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.003224 # miss rate for ReadReq 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-system.cpu.icache.overall_mshr_misses::cpu.inst 965 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 965 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59830500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 59830500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59830500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 59830500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59830500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 59830500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.003224 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.003224 # mshr miss rate for ReadReq accesses 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percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.025060 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 1281 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1096 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.039093 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 11737 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 11737 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackClean_hits::writebacks 26 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 26 # number of WritebackClean hits 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-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12402500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 12402500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58383000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 58383000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6715500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 6715500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 58383000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 19118000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 77501000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 58383000 # number of overall miss cycles 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# mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss 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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.390320 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1307 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 26 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1076 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 26 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 205 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 205 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 965 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 111 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1956 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 632 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2588 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 20224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 83648 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1281 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1281 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1281 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 679500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1447500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 474000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 1281 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1076 # Transaction distribution -system.membus.trans_dist::ReadExReq 205 # Transaction distribution -system.membus.trans_dist::ReadExResp 205 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1076 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2562 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2562 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 81984 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 81984 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1281 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1281 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1281 # Request fanout histogram -system.membus.reqLayer0.occupancy 1281500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 6405000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.3 # Layer utilization (%) +sim_seconds 0.000787 +sim_ticks 787032500 +final_tick 787032500 +sim_freq 1000000000000 +host_inst_rate 4249 +host_op_rate 4261 +host_tick_rate 7692847 +host_mem_usage 270044 +host_seconds 102.30 +sim_insts 434729 +sim_ops 436032 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 787032500 +system.physmem.bytes_read::cpu.inst 68608 +system.physmem.bytes_read::cpu.data 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99.99% +system.cpu.op_class::IprAccess 0 0.00% 99.99% +system.cpu.op_class::InstPrefetch 0 0.00% 99.99% +system.cpu.op_class::total 436252 +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 787032500 +system.cpu.dcache.tags.replacements 1 +system.cpu.dcache.tags.tagsinuse 438.186834 +system.cpu.dcache.tags.total_refs 176636 +system.cpu.dcache.tags.sampled_refs 532 +system.cpu.dcache.tags.avg_refs 332.022556 +system.cpu.dcache.tags.warmup_cycle 0 +system.cpu.dcache.tags.occ_blocks::cpu.data 438.186834 +system.cpu.dcache.tags.occ_percent::cpu.data 0.106979 +system.cpu.dcache.tags.occ_percent::total 0.106979 +system.cpu.dcache.tags.occ_task_id_blocks::1024 531 +system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 +system.cpu.dcache.tags.age_task_id_blocks_1024::1 10 +system.cpu.dcache.tags.age_task_id_blocks_1024::2 507 +system.cpu.dcache.tags.occ_task_id_percent::1024 0.129638 +system.cpu.dcache.tags.tag_accesses 354868 +system.cpu.dcache.tags.data_accesses 354868 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1604500 +system.membus.reqLayer0.utilization 0.2 +system.membus.respLayer1.occupancy 8020000 +system.membus.respLayer1.utilization 1.0 ---------- End Simulation Statistics ---------- |