diff options
Diffstat (limited to 'tests/quick/se/02.insttest/ref/riscv/linux-rv64f')
25 files changed, 3874 insertions, 3168 deletions
diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.ini index 4631a10f3..6d93468f6 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.ini @@ -116,9 +116,11 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system threadPolicy=RoundRobin tracer=system.cpu.tracer +wait_for_remote_gdb=false workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side @@ -745,7 +747,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=insttest cwd= drivers= @@ -754,14 +756,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64f/insttest gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.json index 0a349ce2a..dcaf56bab 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.json +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.json @@ -297,6 +297,7 @@ "max_loads_all_threads": 0, "executeMemoryIssueLimit": 1, "decodeCycleInput": true, + "syscallRetryLatency": 10000, "max_loads_any_thread": 0, "executeLSQTransfersQueueSize": 2, "p_state_clk_gate_max": 1000000000000, @@ -1058,21 +1059,22 @@ "uid": 100, "pid": 100, "kvmInSE": false, - "cxx_class": "LiveProcess", - "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest", + "cxx_class": "Process", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64f/insttest", "drivers": [], "system": "system", "gid": 100, "eventq_index": 0, "env": [], - "input": "cin", - "ppid": 99, - "type": "LiveProcess", + "maxStackSize": 67108864, + "ppid": 0, + "type": "Process", "cwd": "", + "pgid": 100, "simpoint": 0, "euid": 100, + "input": "cin", "path": "system.cpu.workload", - "max_stack_size": 67108864, "name": "workload", "cmd": [ "insttest" @@ -1084,6 +1086,7 @@ } ], "name": "cpu", + "wait_for_remote_gdb": false, "dtb": { "name": "dtb", "eventq_index": 0, diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simerr index 85a6a33ad..6c18cc52d 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simerr +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simerr @@ -1,4 +1,6 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Unknown operating system; assuming Linux. warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings. + Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest' +info: Increasing stack size by one page. diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simout index 695544b14..889a8796d 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simout +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simout @@ -3,14 +3,12 @@ Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv6 gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 30 2016 14:33:35 -gem5 started Nov 30 2016 16:18:32 -gem5 executing on zizzer, pid 34076 -command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/minor-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/minor-timing +gem5 compiled Jul 13 2017 17:09:45 +gem5 started Jul 13 2017 17:11:58 +gem5 executing on boldrock, pid 1989 +command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/minor-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/minor-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. clear fsflags: PASS flw: PASS fsw: PASS @@ -118,4 +116,105 @@ fcvt.w.s, truncate negative: PASS fcvt.w.s, 0.0: PASS fcvt.w.s, -0.0: PASS fcvt.w.s, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) -Exiting @ tick 270200000 because target called exit() +fcvt.w.s, underflow: PASS +fcvt.w.s, infinity: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +fcvt.w.s, -infinity: PASS +fcvt.w.s, quiet NaN: PASS +fcvt.w.s, quiet -NaN: PASS +fcvt.w.s, signaling NaN: PASS +fcvt.wu.s, truncate positive: PASS +fcvt.wu.s, truncate negative: PASS +fcvt.wu.s, 0.0: PASS +fcvt.wu.s, -0.0: PASS +fcvt.wu.s, overflow: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.s, underflow: PASS +fcvt.wu.s, infinity: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.s, -infinity: PASS +fcvt.wu.s, quiet NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.s, quiet -NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.s, signaling NaN: PASS +fmv.x.s, positive: PASS +fmv.x.s, negative: PASS +fmv.x.s, 0.0: PASS +fmv.x.s, -0.0: PASS +feq.s, equal: PASS +feq.s, not equal: PASS +feq.s, 0 == -0: PASS +feq.s, quiet NaN first: PASS +feq.s, quiet NaN second: PASS +feq.s, quiet NaN both: PASS +feq.s, signaling NaN first: PASS +feq.s, signaling NaN second: PASS +feq.s, signaling NaN both: PASS +flt.s, equal: PASS +flt.s, less: PASS +flt.s, greater: PASS +flt.s, quiet NaN first: PASS +flt.s, quiet NaN second: PASS +flt.s, quiet NaN both: PASS +flt.s, signaling NaN first: PASS +flt.s, signaling NaN second: PASS +flt.s, signaling NaN both: PASS +fle.s, equal: PASS +fle.s, less: PASS +fle.s, greater: PASS +fle.s, 0 == -0: PASS +fle.s, quiet NaN first: PASS +fle.s, quiet NaN second: PASS +fle.s, quiet NaN both: PASS +fle.s, signaling NaN first: PASS +fle.s, signaling NaN second: PASS +fle.s, signaling NaN both: PASS +fclass.s, -infinity: PASS +fclass.s, -normal: PASS +fclass.s, -subnormal: PASS +fclass.s, -0.0: PASS +fclass.s, 0.0: PASS +fclass.s, subnormal: PASS +fclass.s, normal: PASS +fclass.s, infinity: PASS +fclass.s, signaling NaN: PASS +fclass.s, quiet NaN: PASS +fcvt.s.w, 0: PASS +fcvt.s.w, negative: PASS +fcvt.s.w, truncate: PASS +fcvt.s.wu, 0: PASS +fcvt.s.wu: PASS +fcvt.s.wu, truncate: PASS +fmv.s.x: PASS +fmv.s.x, truncate: PASS +fsrm: PASS +fsflags: PASS +fscsr: PASS +restore initial round mode: PASS +fcvt.l.s, truncate positive: PASS +fcvt.l.s, truncate negative: PASS +fcvt.l.s, 0.0: PASS +fcvt.l.s, -0.0: PASS +fcvt.l.s, 32-bit overflow: PASS +fcvt.l.s, overflow: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.l.s, underflow: PASS +fcvt.l.s, infinity: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.l.s, -infinity: PASS +fcvt.l.s, quiet NaN: PASS +fcvt.l.s, quiet -NaN: PASS +fcvt.l.s, signaling NaN: PASS +fcvt.lu.s, truncate positive: PASS +fcvt.lu.s, truncate negative: PASS +fcvt.lu.s, 0.0: PASS +fcvt.lu.s, -0.0: PASS +fcvt.lu.s, 32-bit overflow: PASS +fcvt.lu.s, overflow: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.lu.s, underflow: PASS +fcvt.lu.s, infinity: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.lu.s, -infinity: PASS +fcvt.lu.s, quiet NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 9223372036854775808) +fcvt.lu.s, quiet -NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 9223372036854775808) +fcvt.lu.s, signaling NaN: PASS +fcvt.s.l, 0: PASS +fcvt.s.l, negative: PASS +fcvt.s.l, 32-bit truncate: PASS +fcvt.s.lu, 0: PASS +fcvt.s.lu: PASS +fcvt.s.lu, 32-bit truncate: PASS +Exiting @ tick 414261500 because exiting with last active thread context diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/stats.txt index 1a17bfe87..b057a68bf 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/stats.txt @@ -1,765 +1,796 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000270 # Number of seconds simulated -sim_ticks 269998000 # Number of ticks simulated -final_tick 269998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 216821 # Simulator instruction rate (inst/s) -host_op_rate 216819 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 258712153 # Simulator tick rate (ticks/s) -host_mem_usage 263004 # Number of bytes of host memory used -host_seconds 1.04 # Real time elapsed on the host -sim_insts 226275 # Number of instructions simulated -sim_ops 226275 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 67072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 19264 # Number of bytes read from this memory -system.physmem.bytes_read::total 86336 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 67072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 67072 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 1048 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 301 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1349 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 248416655 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 71348677 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 319765332 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 248416655 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 248416655 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 248416655 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 71348677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 319765332 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1349 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 1349 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 86336 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 86336 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 173 # Per bank write bursts -system.physmem.perBankRdBursts::1 19 # Per bank write bursts -system.physmem.perBankRdBursts::2 18 # Per bank write bursts -system.physmem.perBankRdBursts::3 76 # Per bank write bursts -system.physmem.perBankRdBursts::4 196 # Per bank write bursts -system.physmem.perBankRdBursts::5 259 # Per bank write bursts -system.physmem.perBankRdBursts::6 19 # Per bank write bursts -system.physmem.perBankRdBursts::7 4 # Per bank write bursts -system.physmem.perBankRdBursts::8 26 # Per bank write bursts -system.physmem.perBankRdBursts::9 99 # Per bank write bursts -system.physmem.perBankRdBursts::10 157 # Per bank write bursts -system.physmem.perBankRdBursts::11 158 # Per bank write bursts -system.physmem.perBankRdBursts::12 48 # Per bank write bursts -system.physmem.perBankRdBursts::13 47 # Per bank write bursts -system.physmem.perBankRdBursts::14 17 # Per bank write bursts -system.physmem.perBankRdBursts::15 33 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 269757000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1349 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 239 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 351.330544 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 237.806193 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 293.628623 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54 22.59% 22.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 57 23.85% 46.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 29 12.13% 58.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35 14.64% 73.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 20 8.37% 81.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 17 7.11% 88.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 1.67% 90.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 1.26% 91.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20 8.37% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 239 # Bytes accessed per row activation -system.physmem.totQLat 15217250 # Total ticks spent queuing -system.physmem.totMemAccLat 40511000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6745000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11280.39 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30030.39 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 319.77 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 319.77 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.50 # Data bus utilization in percentage -system.physmem.busUtilRead 2.50 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 1101 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.62 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 199968.12 # Average gap between requests -system.physmem.pageHitRate 81.62 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 899640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 462990 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 5454960 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 20897760.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 13384170 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 450240 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 94080210 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 12732960 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 148362930 # Total energy per rank (pJ) -system.physmem_0.averagePower 549.494877 # Core power per rank (mW) -system.physmem_0.totalIdleTime 238782750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 210000 # Time in different power states -system.physmem_0.memoryStateTime::REF 8840000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 33151500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 21477500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 206319000 # Time in different power states -system.physmem_1.actEnergy 871080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 444015 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4176900 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 21512400.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11660490 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 3532800 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 84455190 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 18941760 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 718140.000000 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 146312775 # Total energy per rank (pJ) -system.physmem_1.averagePower 541.901675 # Core power per rank (mW) -system.physmem_1.totalIdleTime 235034750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 8236250 # Time in different power states -system.physmem_1.memoryStateTime::REF 9106000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 690750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 49337750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 17416750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 185210500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 61459 # Number of BP lookups -system.cpu.branchPred.condPredicted 39303 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4350 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 48024 # Number of BTB lookups -system.cpu.branchPred.BTBHits 29463 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.350575 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 10253 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 6091 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 4162 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 2365 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 115 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 269998000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 539996 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 226275 # Number of instructions committed -system.cpu.committedOps 226275 # Number of ops (including micro ops) committed -system.cpu.discardedOps 10605 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 2.386459 # CPI: cycles per instruction -system.cpu.ipc 0.419031 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 117 0.05% 0.05% # Class of committed instruction -system.cpu.op_class_0::IntAlu 136540 60.34% 60.39% # Class of committed instruction -system.cpu.op_class_0::IntMult 325 0.14% 60.54% # Class of committed instruction -system.cpu.op_class_0::IntDiv 40 0.02% 60.56% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 104 0.05% 60.60% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 119 0.05% 60.65% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 43 0.02% 60.67% # Class of committed instruction -system.cpu.op_class_0::FloatMult 30 0.01% 60.69% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 60.69% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 11 0.00% 60.69% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 60.69% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 5 0.00% 60.69% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 60.69% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.69% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 60.69% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 60.69% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 60.69% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 60.69% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 60.69% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.69% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 60.69% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.69% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 60.69% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.69% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.69% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.69% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.69% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.69% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.69% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.69% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.69% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.69% # Class of committed instruction -system.cpu.op_class_0::MemRead 51297 22.67% 83.36% # Class of committed instruction -system.cpu.op_class_0::MemWrite 37094 16.39% 99.76% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 414 0.18% 99.94% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 136 0.06% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 226275 # Class of committed instruction -system.cpu.tickCycles 339832 # Number of cycles that the object actually ticked -system.cpu.idleCycles 200164 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 242.012615 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 90016 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 302 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 298.066225 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 242.012615 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.059085 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.059085 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 302 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.073730 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 181332 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 181332 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 53183 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 53183 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 36833 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 36833 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 90016 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 90016 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 90016 # number of overall hits -system.cpu.dcache.overall_hits::total 90016 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 103 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 103 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 396 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 396 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 499 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 499 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 499 # number of overall misses -system.cpu.dcache.overall_misses::total 499 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9627000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9627000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31678500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31678500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41305500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41305500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41305500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41305500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 53286 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 53286 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 37229 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 37229 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 90515 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 90515 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 90515 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 90515 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001933 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.001933 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010637 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010637 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.005513 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.005513 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.005513 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.005513 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 93466.019417 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 93466.019417 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79996.212121 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 79996.212121 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 82776.553106 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 82776.553106 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 82776.553106 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 82776.553106 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 191 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 191 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 197 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 197 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 197 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 197 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 97 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 97 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 205 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 205 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 302 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 302 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9014000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9014000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16356000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 16356000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25370000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 25370000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25370000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 25370000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001820 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001820 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005506 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005506 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003336 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003336 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003336 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003336 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 92927.835052 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 92927.835052 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79785.365854 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79785.365854 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84006.622517 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 84006.622517 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84006.622517 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 84006.622517 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 69 # number of replacements -system.cpu.icache.tags.tagsinuse 555.459146 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 101640 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1051 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 96.707897 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 555.459146 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.271220 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.271220 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 982 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 189 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 724 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.479492 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 206433 # Number of tag accesses -system.cpu.icache.tags.data_accesses 206433 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 101640 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 101640 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 101640 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 101640 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 101640 # number of overall hits -system.cpu.icache.overall_hits::total 101640 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1051 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1051 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1051 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1051 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1051 # number of overall misses -system.cpu.icache.overall_misses::total 1051 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 87010500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 87010500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 87010500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 87010500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 87010500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 87010500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 102691 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 102691 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 102691 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 102691 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 102691 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 102691 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.010235 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.010235 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.010235 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.010235 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.010235 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.010235 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 82788.296860 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 82788.296860 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 82788.296860 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 82788.296860 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 82788.296860 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 82788.296860 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 69 # number of writebacks -system.cpu.icache.writebacks::total 69 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1051 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1051 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1051 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1051 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1051 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1051 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 85959500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 85959500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 85959500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 85959500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 85959500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 85959500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.010235 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.010235 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.010235 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.010235 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.010235 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.010235 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81788.296860 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81788.296860 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81788.296860 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 81788.296860 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81788.296860 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 81788.296860 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 826.940635 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 73 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1349 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.054114 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 585.573058 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 241.367577 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017870 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.007366 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.025236 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 1349 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1060 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.041168 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12725 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12725 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackClean_hits::writebacks 69 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 69 # number of WritebackClean hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 4 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits -system.cpu.l2cache.overall_hits::total 4 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 205 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 205 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1048 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1048 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 96 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 96 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1048 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 301 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1349 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1048 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 301 # number of overall misses -system.cpu.l2cache.overall_misses::total 1349 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16048500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 16048500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 84351500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 84351500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8856000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 8856000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 84351500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 24904500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 109256000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 84351500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 24904500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 109256000 # number of overall miss cycles -system.cpu.l2cache.WritebackClean_accesses::writebacks 69 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 69 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 205 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 205 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1051 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1051 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 97 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 97 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1051 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 302 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1353 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1051 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 302 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1353 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.997146 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.997146 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.989691 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.989691 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.997146 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.996689 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997044 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997146 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.996689 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997044 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78285.365854 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78285.365854 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80488.072519 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80488.072519 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92250 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92250 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80488.072519 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82739.202658 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 80990.363232 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80488.072519 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82739.202658 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 80990.363232 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 205 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 205 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1048 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1048 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 96 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 96 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1048 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 301 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1349 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1048 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 301 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1349 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13998500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13998500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 73871500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 73871500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7896000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7896000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 73871500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21894500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 95766000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 73871500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21894500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 95766000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997146 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.997146 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.989691 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.989691 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.997146 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.996689 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997044 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997146 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996689 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997044 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68285.365854 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68285.365854 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70488.072519 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70488.072519 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82250 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82250 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70488.072519 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72739.202658 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70990.363232 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70488.072519 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72739.202658 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70990.363232 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1422 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 70 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1148 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 69 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 205 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 205 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1051 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 97 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2171 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 604 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2775 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 71680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 19328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 91008 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1353 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000739 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.027186 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1352 99.93% 99.93% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1 0.07% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1353 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 780000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1576500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 453000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 1349 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1144 # Transaction distribution -system.membus.trans_dist::ReadExReq 205 # Transaction distribution -system.membus.trans_dist::ReadExResp 205 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1144 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2698 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2698 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 86336 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 86336 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1349 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1349 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1349 # Request fanout histogram -system.membus.reqLayer0.occupancy 1553000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 7152500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.6 # Layer utilization (%) +sim_seconds 0.000414 +sim_ticks 414261500 +final_tick 414261500 +sim_freq 1000000000000 +host_inst_rate 4344 +host_op_rate 4357 +host_tick_rate 4323449 +host_mem_usage 272860 +host_seconds 95.81 +sim_insts 416240 +sim_ops 417493 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 414261500 +system.physmem.bytes_read::cpu.inst 85248 +system.physmem.bytes_read::cpu.data 34368 +system.physmem.bytes_read::total 119616 +system.physmem.bytes_inst_read::cpu.inst 85248 +system.physmem.bytes_inst_read::total 85248 +system.physmem.num_reads::cpu.inst 1332 +system.physmem.num_reads::cpu.data 537 +system.physmem.num_reads::total 1869 +system.physmem.bw_read::cpu.inst 205783062 +system.physmem.bw_read::cpu.data 82962090 +system.physmem.bw_read::total 288745152 +system.physmem.bw_inst_read::cpu.inst 205783062 +system.physmem.bw_inst_read::total 205783062 +system.physmem.bw_total::cpu.inst 205783062 +system.physmem.bw_total::cpu.data 82962090 +system.physmem.bw_total::total 288745152 +system.physmem.readReqs 1869 +system.physmem.writeReqs 0 +system.physmem.readBursts 1869 +system.physmem.writeBursts 0 +system.physmem.bytesReadDRAM 119616 +system.physmem.bytesReadWrQ 0 +system.physmem.bytesWritten 0 +system.physmem.bytesReadSys 119616 +system.physmem.bytesWrittenSys 0 +system.physmem.servicedByWrQ 0 +system.physmem.mergedWrBursts 0 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 238 +system.physmem.perBankRdBursts::1 263 +system.physmem.perBankRdBursts::2 168 +system.physmem.perBankRdBursts::3 170 +system.physmem.perBankRdBursts::4 149 +system.physmem.perBankRdBursts::5 98 +system.physmem.perBankRdBursts::6 118 +system.physmem.perBankRdBursts::7 65 +system.physmem.perBankRdBursts::8 62 +system.physmem.perBankRdBursts::9 64 +system.physmem.perBankRdBursts::10 21 +system.physmem.perBankRdBursts::11 43 +system.physmem.perBankRdBursts::12 80 +system.physmem.perBankRdBursts::13 100 +system.physmem.perBankRdBursts::14 109 +system.physmem.perBankRdBursts::15 121 +system.physmem.perBankWrBursts::0 0 +system.physmem.perBankWrBursts::1 0 +system.physmem.perBankWrBursts::2 0 +system.physmem.perBankWrBursts::3 0 +system.physmem.perBankWrBursts::4 0 +system.physmem.perBankWrBursts::5 0 +system.physmem.perBankWrBursts::6 0 +system.physmem.perBankWrBursts::7 0 +system.physmem.perBankWrBursts::8 0 +system.physmem.perBankWrBursts::9 0 +system.physmem.perBankWrBursts::10 0 +system.physmem.perBankWrBursts::11 0 +system.physmem.perBankWrBursts::12 0 +system.physmem.perBankWrBursts::13 0 +system.physmem.perBankWrBursts::14 0 +system.physmem.perBankWrBursts::15 0 +system.physmem.numRdRetry 0 +system.physmem.numWrRetry 0 +system.physmem.totGap 414165000 +system.physmem.readPktSize::0 0 +system.physmem.readPktSize::1 0 +system.physmem.readPktSize::2 0 +system.physmem.readPktSize::3 0 +system.physmem.readPktSize::4 0 +system.physmem.readPktSize::5 0 +system.physmem.readPktSize::6 1869 +system.physmem.writePktSize::0 0 +system.physmem.writePktSize::1 0 +system.physmem.writePktSize::2 0 +system.physmem.writePktSize::3 0 +system.physmem.writePktSize::4 0 +system.physmem.writePktSize::5 0 +system.physmem.writePktSize::6 0 +system.physmem.rdQLenPdf::0 1655 +system.physmem.rdQLenPdf::1 200 +system.physmem.rdQLenPdf::2 14 +system.physmem.rdQLenPdf::3 0 +system.physmem.rdQLenPdf::4 0 +system.physmem.rdQLenPdf::5 0 +system.physmem.rdQLenPdf::6 0 +system.physmem.rdQLenPdf::7 0 +system.physmem.rdQLenPdf::8 0 +system.physmem.rdQLenPdf::9 0 +system.physmem.rdQLenPdf::10 0 +system.physmem.rdQLenPdf::11 0 +system.physmem.rdQLenPdf::12 0 +system.physmem.rdQLenPdf::13 0 +system.physmem.rdQLenPdf::14 0 +system.physmem.rdQLenPdf::15 0 +system.physmem.rdQLenPdf::16 0 +system.physmem.rdQLenPdf::17 0 +system.physmem.rdQLenPdf::18 0 +system.physmem.rdQLenPdf::19 0 +system.physmem.rdQLenPdf::20 0 +system.physmem.rdQLenPdf::21 0 +system.physmem.rdQLenPdf::22 0 +system.physmem.rdQLenPdf::23 0 +system.physmem.rdQLenPdf::24 0 +system.physmem.rdQLenPdf::25 0 +system.physmem.rdQLenPdf::26 0 +system.physmem.rdQLenPdf::27 0 +system.physmem.rdQLenPdf::28 0 +system.physmem.rdQLenPdf::29 0 +system.physmem.rdQLenPdf::30 0 +system.physmem.rdQLenPdf::31 0 +system.physmem.wrQLenPdf::0 0 +system.physmem.wrQLenPdf::1 0 +system.physmem.wrQLenPdf::2 0 +system.physmem.wrQLenPdf::3 0 +system.physmem.wrQLenPdf::4 0 +system.physmem.wrQLenPdf::5 0 +system.physmem.wrQLenPdf::6 0 +system.physmem.wrQLenPdf::7 0 +system.physmem.wrQLenPdf::8 0 +system.physmem.wrQLenPdf::9 0 +system.physmem.wrQLenPdf::10 0 +system.physmem.wrQLenPdf::11 0 +system.physmem.wrQLenPdf::12 0 +system.physmem.wrQLenPdf::13 0 +system.physmem.wrQLenPdf::14 0 +system.physmem.wrQLenPdf::15 0 +system.physmem.wrQLenPdf::16 0 +system.physmem.wrQLenPdf::17 0 +system.physmem.wrQLenPdf::18 0 +system.physmem.wrQLenPdf::19 0 +system.physmem.wrQLenPdf::20 0 +system.physmem.wrQLenPdf::21 0 +system.physmem.wrQLenPdf::22 0 +system.physmem.wrQLenPdf::23 0 +system.physmem.wrQLenPdf::24 0 +system.physmem.wrQLenPdf::25 0 +system.physmem.wrQLenPdf::26 0 +system.physmem.wrQLenPdf::27 0 +system.physmem.wrQLenPdf::28 0 +system.physmem.wrQLenPdf::29 0 +system.physmem.wrQLenPdf::30 0 +system.physmem.wrQLenPdf::31 0 +system.physmem.wrQLenPdf::32 0 +system.physmem.wrQLenPdf::33 0 +system.physmem.wrQLenPdf::34 0 +system.physmem.wrQLenPdf::35 0 +system.physmem.wrQLenPdf::36 0 +system.physmem.wrQLenPdf::37 0 +system.physmem.wrQLenPdf::38 0 +system.physmem.wrQLenPdf::39 0 +system.physmem.wrQLenPdf::40 0 +system.physmem.wrQLenPdf::41 0 +system.physmem.wrQLenPdf::42 0 +system.physmem.wrQLenPdf::43 0 +system.physmem.wrQLenPdf::44 0 +system.physmem.wrQLenPdf::45 0 +system.physmem.wrQLenPdf::46 0 +system.physmem.wrQLenPdf::47 0 +system.physmem.wrQLenPdf::48 0 +system.physmem.wrQLenPdf::49 0 +system.physmem.wrQLenPdf::50 0 +system.physmem.wrQLenPdf::51 0 +system.physmem.wrQLenPdf::52 0 +system.physmem.wrQLenPdf::53 0 +system.physmem.wrQLenPdf::54 0 +system.physmem.wrQLenPdf::55 0 +system.physmem.wrQLenPdf::56 0 +system.physmem.wrQLenPdf::57 0 +system.physmem.wrQLenPdf::58 0 +system.physmem.wrQLenPdf::59 0 +system.physmem.wrQLenPdf::60 0 +system.physmem.wrQLenPdf::61 0 +system.physmem.wrQLenPdf::62 0 +system.physmem.wrQLenPdf::63 0 +system.physmem.bytesPerActivate::samples 398 +system.physmem.bytesPerActivate::mean 295.557788 +system.physmem.bytesPerActivate::gmean 206.933383 +system.physmem.bytesPerActivate::stdev 254.300651 +system.physmem.bytesPerActivate::0-127 93 23.36% 23.36% +system.physmem.bytesPerActivate::128-255 118 29.64% 53.01% +system.physmem.bytesPerActivate::256-383 64 16.08% 69.09% +system.physmem.bytesPerActivate::384-511 48 12.06% 81.15% +system.physmem.bytesPerActivate::512-639 28 7.03% 88.19% +system.physmem.bytesPerActivate::640-767 16 4.02% 92.21% +system.physmem.bytesPerActivate::768-895 8 2.01% 94.22% +system.physmem.bytesPerActivate::896-1023 7 1.75% 95.97% +system.physmem.bytesPerActivate::1024-1151 16 4.02% 99.99% +system.physmem.bytesPerActivate::total 398 +system.physmem.totQLat 24652500 +system.physmem.totMemAccLat 59696250 +system.physmem.totBusLat 9345000 +system.physmem.avgQLat 13190.20 +system.physmem.avgBusLat 5000.00 +system.physmem.avgMemAccLat 31940.20 +system.physmem.avgRdBW 288.74 +system.physmem.avgWrBW 0.00 +system.physmem.avgRdBWSys 288.74 +system.physmem.avgWrBWSys 0.00 +system.physmem.peakBW 12800.00 +system.physmem.busUtil 2.25 +system.physmem.busUtilRead 2.25 +system.physmem.busUtilWrite 0.00 +system.physmem.avgRdQLen 1.06 +system.physmem.avgWrQLen 0.00 +system.physmem.readRowHits 1463 +system.physmem.writeRowHits 0 +system.physmem.readRowHitRate 78.27 +system.physmem.writeRowHitRate nan +system.physmem.avgGap 221597.11 +system.physmem.pageHitRate 78.27 +system.physmem_0.actEnergy 1992060 +system.physmem_0.preEnergy 1051215 +system.physmem_0.readEnergy 9060660 +system.physmem_0.writeEnergy 0 +system.physmem_0.refreshEnergy 32575920 +system.physmem_0.actBackEnergy 22658070 +system.physmem_0.preBackEnergy 684000 +system.physmem_0.actPowerDownEnergy 159927750 +system.physmem_0.prePowerDownEnergy 4636320 +system.physmem_0.selfRefreshEnergy 0 +system.physmem_0.totalEnergy 232585995 +system.physmem_0.averagePower 561.445931 +system.physmem_0.totalIdleTime 362517500 +system.physmem_0.memoryStateTime::IDLE 318000 +system.physmem_0.memoryStateTime::REF 13780000 +system.physmem_0.memoryStateTime::SREF 0 +system.physmem_0.memoryStateTime::PRE_PDN 12066000 +system.physmem_0.memoryStateTime::ACT 37356750 +system.physmem_0.memoryStateTime::ACT_PDN 350740750 +system.physmem_1.actEnergy 906780 +system.physmem_1.preEnergy 459195 +system.physmem_1.readEnergy 4284000 +system.physmem_1.writeEnergy 0 +system.physmem_1.refreshEnergy 15366000 +system.physmem_1.actBackEnergy 12000210 +system.physmem_1.preBackEnergy 728640 +system.physmem_1.actPowerDownEnergy 52156140 +system.physmem_1.prePowerDownEnergy 13950720 +system.physmem_1.selfRefreshEnergy 58138620 +system.physmem_1.totalEnergy 157990305 +system.physmem_1.averagePower 381.377278 +system.physmem_1.totalIdleTime 386011000 +system.physmem_1.memoryStateTime::IDLE 1203000 +system.physmem_1.memoryStateTime::REF 6518000 +system.physmem_1.memoryStateTime::SREF 235342000 +system.physmem_1.memoryStateTime::PRE_PDN 36329000 +system.physmem_1.memoryStateTime::ACT 20483500 +system.physmem_1.memoryStateTime::ACT_PDN 114386000 +system.pwrStateResidencyTicks::UNDEFINED 414261500 +system.cpu.branchPred.lookups 113788 +system.cpu.branchPred.condPredicted 80533 +system.cpu.branchPred.condIncorrect 8262 +system.cpu.branchPred.BTBLookups 70464 +system.cpu.branchPred.BTBHits 37407 +system.cpu.branchPred.BTBCorrect 0 +system.cpu.branchPred.BTBHitPct 53.086682 +system.cpu.branchPred.usedRAS 0 +system.cpu.branchPred.RASInCorrect 0 +system.cpu.branchPred.indirectLookups 22847 +system.cpu.branchPred.indirectHits 13810 +system.cpu.branchPred.indirectMisses 9037 +system.cpu.branchPredindirectMispredicted 4771 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 216 +system.cpu.pwrStateResidencyTicks::ON 414261500 +system.cpu.numCycles 828523 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 416240 +system.cpu.committedOps 417493 +system.cpu.discardedOps 21677 +system.cpu.numFetchSuspends 0 +system.cpu.cpi 1.990493 +system.cpu.ipc 0.502387 +system.cpu.op_class_0::No_OpClass 236 0.05% 0.05% +system.cpu.op_class_0::IntAlu 245871 58.89% 58.94% +system.cpu.op_class_0::IntMult 674 0.16% 59.11% +system.cpu.op_class_0::IntDiv 644 0.15% 59.26% +system.cpu.op_class_0::FloatAdd 128 0.03% 59.29% +system.cpu.op_class_0::FloatCmp 161 0.03% 59.33% +system.cpu.op_class_0::FloatCvt 109 0.02% 59.35% +system.cpu.op_class_0::FloatMult 30 0.00% 59.36% +system.cpu.op_class_0::FloatMultAcc 0 0.00% 59.36% +system.cpu.op_class_0::FloatDiv 11 0.00% 59.36% +system.cpu.op_class_0::FloatMisc 0 0.00% 59.36% +system.cpu.op_class_0::FloatSqrt 5 0.00% 59.37% +system.cpu.op_class_0::SimdAdd 0 0.00% 59.37% +system.cpu.op_class_0::SimdAddAcc 0 0.00% 59.37% +system.cpu.op_class_0::SimdAlu 0 0.00% 59.37% +system.cpu.op_class_0::SimdCmp 0 0.00% 59.37% +system.cpu.op_class_0::SimdCvt 0 0.00% 59.37% +system.cpu.op_class_0::SimdMisc 0 0.00% 59.37% +system.cpu.op_class_0::SimdMult 0 0.00% 59.37% +system.cpu.op_class_0::SimdMultAcc 0 0.00% 59.37% +system.cpu.op_class_0::SimdShift 0 0.00% 59.37% +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 59.37% +system.cpu.op_class_0::SimdSqrt 0 0.00% 59.37% +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 59.37% +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 59.37% +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 59.37% +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 59.37% +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 59.37% +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 59.37% +system.cpu.op_class_0::SimdFloatMult 0 0.00% 59.37% +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 59.37% +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 59.37% +system.cpu.op_class_0::MemRead 104951 25.13% 84.50% +system.cpu.op_class_0::MemWrite 63954 15.31% 99.82% +system.cpu.op_class_0::FloatMemRead 547 0.13% 99.95% +system.cpu.op_class_0::FloatMemWrite 172 0.04% 99.99% +system.cpu.op_class_0::IprAccess 0 0.00% 99.99% +system.cpu.op_class_0::InstPrefetch 0 0.00% 99.99% +system.cpu.op_class_0::total 417493 +system.cpu.tickCycles 557012 +system.cpu.idleCycles 271511 +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 414261500 +system.cpu.dcache.tags.replacements 2 +system.cpu.dcache.tags.tagsinuse 414.110238 +system.cpu.dcache.tags.total_refs 172703 +system.cpu.dcache.tags.sampled_refs 538 +system.cpu.dcache.tags.avg_refs 321.009293 +system.cpu.dcache.tags.warmup_cycle 0 +system.cpu.dcache.tags.occ_blocks::cpu.data 414.110238 +system.cpu.dcache.tags.occ_percent::cpu.data 0.101101 +system.cpu.dcache.tags.occ_percent::total 0.101101 +system.cpu.dcache.tags.occ_task_id_blocks::1024 536 +system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 +system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 +system.cpu.dcache.tags.age_task_id_blocks_1024::2 497 +system.cpu.dcache.tags.occ_task_id_percent::1024 0.130859 +system.cpu.dcache.tags.tag_accesses 347344 +system.cpu.dcache.tags.data_accesses 347344 +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 414261500 +system.cpu.dcache.ReadReq_hits::cpu.data 107273 +system.cpu.dcache.ReadReq_hits::total 107273 +system.cpu.dcache.WriteReq_hits::cpu.data 62050 +system.cpu.dcache.WriteReq_hits::total 62050 +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1689 +system.cpu.dcache.LoadLockedReq_hits::total 1689 +system.cpu.dcache.StoreCondReq_hits::cpu.data 1691 +system.cpu.dcache.StoreCondReq_hits::total 1691 +system.cpu.dcache.demand_hits::cpu.data 169323 +system.cpu.dcache.demand_hits::total 169323 +system.cpu.dcache.overall_hits::cpu.data 169323 +system.cpu.dcache.overall_hits::total 169323 +system.cpu.dcache.ReadReq_misses::cpu.data 313 +system.cpu.dcache.ReadReq_misses::total 313 +system.cpu.dcache.WriteReq_misses::cpu.data 385 +system.cpu.dcache.WriteReq_misses::total 385 +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 +system.cpu.dcache.LoadLockedReq_misses::total 2 +system.cpu.dcache.demand_misses::cpu.data 698 +system.cpu.dcache.demand_misses::total 698 +system.cpu.dcache.overall_misses::cpu.data 698 +system.cpu.dcache.overall_misses::total 698 +system.cpu.dcache.ReadReq_miss_latency::cpu.data 27269500 +system.cpu.dcache.ReadReq_miss_latency::total 27269500 +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31180500 +system.cpu.dcache.WriteReq_miss_latency::total 31180500 +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 198500 +system.cpu.dcache.LoadLockedReq_miss_latency::total 198500 +system.cpu.dcache.demand_miss_latency::cpu.data 58450000 +system.cpu.dcache.demand_miss_latency::total 58450000 +system.cpu.dcache.overall_miss_latency::cpu.data 58450000 +system.cpu.dcache.overall_miss_latency::total 58450000 +system.cpu.dcache.ReadReq_accesses::cpu.data 107586 +system.cpu.dcache.ReadReq_accesses::total 107586 +system.cpu.dcache.WriteReq_accesses::cpu.data 62435 +system.cpu.dcache.WriteReq_accesses::total 62435 +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1691 +system.cpu.dcache.LoadLockedReq_accesses::total 1691 +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1691 +system.cpu.dcache.StoreCondReq_accesses::total 1691 +system.cpu.dcache.demand_accesses::cpu.data 170021 +system.cpu.dcache.demand_accesses::total 170021 +system.cpu.dcache.overall_accesses::cpu.data 170021 +system.cpu.dcache.overall_accesses::total 170021 +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002909 +system.cpu.dcache.ReadReq_miss_rate::total 0.002909 +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006166 +system.cpu.dcache.WriteReq_miss_rate::total 0.006166 +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001182 +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001182 +system.cpu.dcache.demand_miss_rate::cpu.data 0.004105 +system.cpu.dcache.demand_miss_rate::total 0.004105 +system.cpu.dcache.overall_miss_rate::cpu.data 0.004105 +system.cpu.dcache.overall_miss_rate::total 0.004105 +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87123.003194 +system.cpu.dcache.ReadReq_avg_miss_latency::total 87123.003194 +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80988.311688 +system.cpu.dcache.WriteReq_avg_miss_latency::total 80988.311688 +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 99250 +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 99250 +system.cpu.dcache.demand_avg_miss_latency::cpu.data 83739.255014 +system.cpu.dcache.demand_avg_miss_latency::total 83739.255014 +system.cpu.dcache.overall_avg_miss_latency::cpu.data 83739.255014 +system.cpu.dcache.overall_avg_miss_latency::total 83739.255014 +system.cpu.dcache.blocked_cycles::no_mshrs 0 +system.cpu.dcache.blocked_cycles::no_targets 0 +system.cpu.dcache.blocked::no_mshrs 0 +system.cpu.dcache.blocked::no_targets 0 +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan +system.cpu.dcache.avg_blocked_cycles::no_targets nan +system.cpu.dcache.writebacks::writebacks 2 +system.cpu.dcache.writebacks::total 2 +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3 +system.cpu.dcache.ReadReq_mshr_hits::total 3 +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 159 +system.cpu.dcache.WriteReq_mshr_hits::total 159 +system.cpu.dcache.demand_mshr_hits::cpu.data 162 +system.cpu.dcache.demand_mshr_hits::total 162 +system.cpu.dcache.overall_mshr_hits::cpu.data 162 +system.cpu.dcache.overall_mshr_hits::total 162 +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 310 +system.cpu.dcache.ReadReq_mshr_misses::total 310 +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 226 +system.cpu.dcache.WriteReq_mshr_misses::total 226 +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 2 +system.cpu.dcache.LoadLockedReq_mshr_misses::total 2 +system.cpu.dcache.demand_mshr_misses::cpu.data 536 +system.cpu.dcache.demand_mshr_misses::total 536 +system.cpu.dcache.overall_mshr_misses::cpu.data 536 +system.cpu.dcache.overall_mshr_misses::total 536 +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26720000 +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26720000 +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18848500 +system.cpu.dcache.WriteReq_mshr_miss_latency::total 18848500 +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 196500 +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196500 +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45568500 +system.cpu.dcache.demand_mshr_miss_latency::total 45568500 +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45568500 +system.cpu.dcache.overall_mshr_miss_latency::total 45568500 +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002881 +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002881 +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003619 +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003619 +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.001182 +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.001182 +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003152 +system.cpu.dcache.demand_mshr_miss_rate::total 0.003152 +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003152 +system.cpu.dcache.overall_mshr_miss_rate::total 0.003152 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86193.548387 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86193.548387 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83400.442477 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83400.442477 +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 98250 +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 98250 +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 85015.858208 +system.cpu.dcache.demand_avg_mshr_miss_latency::total 85015.858208 +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 85015.858208 +system.cpu.dcache.overall_avg_mshr_miss_latency::total 85015.858208 +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 414261500 +system.cpu.icache.tags.replacements 118 +system.cpu.icache.tags.tagsinuse 820.164908 +system.cpu.icache.tags.total_refs 153400 +system.cpu.icache.tags.sampled_refs 1339 +system.cpu.icache.tags.avg_refs 114.563106 +system.cpu.icache.tags.warmup_cycle 0 +system.cpu.icache.tags.occ_blocks::cpu.inst 820.164908 +system.cpu.icache.tags.occ_percent::cpu.inst 0.400471 +system.cpu.icache.tags.occ_percent::total 0.400471 +system.cpu.icache.tags.occ_task_id_blocks::1024 1221 +system.cpu.icache.tags.age_task_id_blocks_1024::0 51 +system.cpu.icache.tags.age_task_id_blocks_1024::1 123 +system.cpu.icache.tags.age_task_id_blocks_1024::2 1047 +system.cpu.icache.tags.occ_task_id_percent::1024 0.596191 +system.cpu.icache.tags.tag_accesses 310819 +system.cpu.icache.tags.data_accesses 310819 +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 414261500 +system.cpu.icache.ReadReq_hits::cpu.inst 153400 +system.cpu.icache.ReadReq_hits::total 153400 +system.cpu.icache.demand_hits::cpu.inst 153400 +system.cpu.icache.demand_hits::total 153400 +system.cpu.icache.overall_hits::cpu.inst 153400 +system.cpu.icache.overall_hits::total 153400 +system.cpu.icache.ReadReq_misses::cpu.inst 1340 +system.cpu.icache.ReadReq_misses::total 1340 +system.cpu.icache.demand_misses::cpu.inst 1340 +system.cpu.icache.demand_misses::total 1340 +system.cpu.icache.overall_misses::cpu.inst 1340 +system.cpu.icache.overall_misses::total 1340 +system.cpu.icache.ReadReq_miss_latency::cpu.inst 113521500 +system.cpu.icache.ReadReq_miss_latency::total 113521500 +system.cpu.icache.demand_miss_latency::cpu.inst 113521500 +system.cpu.icache.demand_miss_latency::total 113521500 +system.cpu.icache.overall_miss_latency::cpu.inst 113521500 +system.cpu.icache.overall_miss_latency::total 113521500 +system.cpu.icache.ReadReq_accesses::cpu.inst 154740 +system.cpu.icache.ReadReq_accesses::total 154740 +system.cpu.icache.demand_accesses::cpu.inst 154740 +system.cpu.icache.demand_accesses::total 154740 +system.cpu.icache.overall_accesses::cpu.inst 154740 +system.cpu.icache.overall_accesses::total 154740 +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008659 +system.cpu.icache.ReadReq_miss_rate::total 0.008659 +system.cpu.icache.demand_miss_rate::cpu.inst 0.008659 +system.cpu.icache.demand_miss_rate::total 0.008659 +system.cpu.icache.overall_miss_rate::cpu.inst 0.008659 +system.cpu.icache.overall_miss_rate::total 0.008659 +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 84717.537313 +system.cpu.icache.ReadReq_avg_miss_latency::total 84717.537313 +system.cpu.icache.demand_avg_miss_latency::cpu.inst 84717.537313 +system.cpu.icache.demand_avg_miss_latency::total 84717.537313 +system.cpu.icache.overall_avg_miss_latency::cpu.inst 84717.537313 +system.cpu.icache.overall_avg_miss_latency::total 84717.537313 +system.cpu.icache.blocked_cycles::no_mshrs 0 +system.cpu.icache.blocked_cycles::no_targets 0 +system.cpu.icache.blocked::no_mshrs 0 +system.cpu.icache.blocked::no_targets 0 +system.cpu.icache.avg_blocked_cycles::no_mshrs nan +system.cpu.icache.avg_blocked_cycles::no_targets nan +system.cpu.icache.writebacks::writebacks 118 +system.cpu.icache.writebacks::total 118 +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1340 +system.cpu.icache.ReadReq_mshr_misses::total 1340 +system.cpu.icache.demand_mshr_misses::cpu.inst 1340 +system.cpu.icache.demand_mshr_misses::total 1340 +system.cpu.icache.overall_mshr_misses::cpu.inst 1340 +system.cpu.icache.overall_mshr_misses::total 1340 +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 112182500 +system.cpu.icache.ReadReq_mshr_miss_latency::total 112182500 +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 112182500 +system.cpu.icache.demand_mshr_miss_latency::total 112182500 +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 112182500 +system.cpu.icache.overall_mshr_miss_latency::total 112182500 +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008659 +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008659 +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008659 +system.cpu.icache.demand_mshr_miss_rate::total 0.008659 +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008659 +system.cpu.icache.overall_mshr_miss_rate::total 0.008659 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83718.283582 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83718.283582 +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83718.283582 +system.cpu.icache.demand_avg_mshr_miss_latency::total 83718.283582 +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83718.283582 +system.cpu.icache.overall_avg_mshr_miss_latency::total 83718.283582 +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 414261500 +system.cpu.l2cache.tags.replacements 0 +system.cpu.l2cache.tags.tagsinuse 1287.297048 +system.cpu.l2cache.tags.total_refs 128 +system.cpu.l2cache.tags.sampled_refs 1869 +system.cpu.l2cache.tags.avg_refs 0.068485 +system.cpu.l2cache.tags.warmup_cycle 0 +system.cpu.l2cache.tags.occ_blocks::cpu.inst 873.530918 +system.cpu.l2cache.tags.occ_blocks::cpu.data 413.766129 +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.026658 +system.cpu.l2cache.tags.occ_percent::cpu.data 0.012627 +system.cpu.l2cache.tags.occ_percent::total 0.039285 +system.cpu.l2cache.tags.occ_task_id_blocks::1024 1869 +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 147 +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1657 +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.057037 +system.cpu.l2cache.tags.tag_accesses 17853 +system.cpu.l2cache.tags.data_accesses 17853 +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 414261500 +system.cpu.l2cache.WritebackDirty_hits::writebacks 2 +system.cpu.l2cache.WritebackDirty_hits::total 2 +system.cpu.l2cache.WritebackClean_hits::writebacks 118 +system.cpu.l2cache.WritebackClean_hits::total 118 +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 7 +system.cpu.l2cache.ReadCleanReq_hits::total 7 +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 +system.cpu.l2cache.ReadSharedReq_hits::total 1 +system.cpu.l2cache.demand_hits::cpu.inst 7 +system.cpu.l2cache.demand_hits::cpu.data 1 +system.cpu.l2cache.demand_hits::total 8 +system.cpu.l2cache.overall_hits::cpu.inst 7 +system.cpu.l2cache.overall_hits::cpu.data 1 +system.cpu.l2cache.overall_hits::total 8 +system.cpu.l2cache.ReadExReq_misses::cpu.data 226 +system.cpu.l2cache.ReadExReq_misses::total 226 +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1333 +system.cpu.l2cache.ReadCleanReq_misses::total 1333 +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 311 +system.cpu.l2cache.ReadSharedReq_misses::total 311 +system.cpu.l2cache.demand_misses::cpu.inst 1333 +system.cpu.l2cache.demand_misses::cpu.data 537 +system.cpu.l2cache.demand_misses::total 1870 +system.cpu.l2cache.overall_misses::cpu.inst 1333 +system.cpu.l2cache.overall_misses::cpu.data 537 +system.cpu.l2cache.overall_misses::total 1870 +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 18508000 +system.cpu.l2cache.ReadExReq_miss_latency::total 18508000 +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 110100500 +system.cpu.l2cache.ReadCleanReq_miss_latency::total 110100500 +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 26435000 +system.cpu.l2cache.ReadSharedReq_miss_latency::total 26435000 +system.cpu.l2cache.demand_miss_latency::cpu.inst 110100500 +system.cpu.l2cache.demand_miss_latency::cpu.data 44943000 +system.cpu.l2cache.demand_miss_latency::total 155043500 +system.cpu.l2cache.overall_miss_latency::cpu.inst 110100500 +system.cpu.l2cache.overall_miss_latency::cpu.data 44943000 +system.cpu.l2cache.overall_miss_latency::total 155043500 +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2 +system.cpu.l2cache.WritebackDirty_accesses::total 2 +system.cpu.l2cache.WritebackClean_accesses::writebacks 118 +system.cpu.l2cache.WritebackClean_accesses::total 118 +system.cpu.l2cache.ReadExReq_accesses::cpu.data 226 +system.cpu.l2cache.ReadExReq_accesses::total 226 +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1340 +system.cpu.l2cache.ReadCleanReq_accesses::total 1340 +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 312 +system.cpu.l2cache.ReadSharedReq_accesses::total 312 +system.cpu.l2cache.demand_accesses::cpu.inst 1340 +system.cpu.l2cache.demand_accesses::cpu.data 538 +system.cpu.l2cache.demand_accesses::total 1878 +system.cpu.l2cache.overall_accesses::cpu.inst 1340 +system.cpu.l2cache.overall_accesses::cpu.data 538 +system.cpu.l2cache.overall_accesses::total 1878 +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 +system.cpu.l2cache.ReadExReq_miss_rate::total 1 +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.994776 +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.994776 +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.996794 +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.996794 +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994776 +system.cpu.l2cache.demand_miss_rate::cpu.data 0.998141 +system.cpu.l2cache.demand_miss_rate::total 0.995740 +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994776 +system.cpu.l2cache.overall_miss_rate::cpu.data 0.998141 +system.cpu.l2cache.overall_miss_rate::total 0.995740 +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81893.805309 +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81893.805309 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82596.024006 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82596.024006 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85000 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85000 +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82596.024006 +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83692.737430 +system.cpu.l2cache.demand_avg_miss_latency::total 82910.962566 +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82596.024006 +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83692.737430 +system.cpu.l2cache.overall_avg_miss_latency::total 82910.962566 +system.cpu.l2cache.blocked_cycles::no_mshrs 0 +system.cpu.l2cache.blocked_cycles::no_targets 0 +system.cpu.l2cache.blocked::no_mshrs 0 +system.cpu.l2cache.blocked::no_targets 0 +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan +system.cpu.l2cache.avg_blocked_cycles::no_targets nan +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 226 +system.cpu.l2cache.ReadExReq_mshr_misses::total 226 +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1333 +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1333 +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 311 +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 311 +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1333 +system.cpu.l2cache.demand_mshr_misses::cpu.data 537 +system.cpu.l2cache.demand_mshr_misses::total 1870 +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1333 +system.cpu.l2cache.overall_mshr_misses::cpu.data 537 +system.cpu.l2cache.overall_mshr_misses::total 1870 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16248000 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16248000 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 96780500 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 96780500 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 23325000 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 23325000 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 96780500 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 39573000 +system.cpu.l2cache.demand_mshr_miss_latency::total 136353500 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 96780500 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 39573000 +system.cpu.l2cache.overall_mshr_miss_latency::total 136353500 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994776 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994776 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.996794 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.996794 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994776 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.998141 +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995740 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994776 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.998141 +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995740 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71893.805309 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71893.805309 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72603.525881 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72603.525881 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75000 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75000 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72603.525881 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73692.737430 +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72916.310160 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72603.525881 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73692.737430 +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72916.310160 +system.cpu.toL2Bus.snoop_filter.tot_requests 1998 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 121 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 414261500 +system.cpu.toL2Bus.trans_dist::ReadResp 1651 +system.cpu.toL2Bus.trans_dist::WritebackDirty 2 +system.cpu.toL2Bus.trans_dist::WritebackClean 118 +system.cpu.toL2Bus.trans_dist::ReadExReq 226 +system.cpu.toL2Bus.trans_dist::ReadExResp 226 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1340 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 312 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2797 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1078 +system.cpu.toL2Bus.pkt_count::total 3875 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93248 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 34560 +system.cpu.toL2Bus.pkt_size::total 127808 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 1878 +system.cpu.toL2Bus.snoop_fanout::mean 0.000532 +system.cpu.toL2Bus.snoop_fanout::stdev 0.023075 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 1877 99.94% 99.94% +system.cpu.toL2Bus.snoop_fanout::1 1 0.05% 99.99% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 99.99% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 99.99% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 1878 +system.cpu.toL2Bus.reqLayer0.occupancy 1119000 +system.cpu.toL2Bus.reqLayer0.utilization 0.2 +system.cpu.toL2Bus.respLayer0.occupancy 2008500 +system.cpu.toL2Bus.respLayer0.utilization 0.4 +system.cpu.toL2Bus.respLayer1.occupancy 807000 +system.cpu.toL2Bus.respLayer1.utilization 0.1 +system.membus.snoop_filter.tot_requests 1869 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 414261500 +system.membus.trans_dist::ReadResp 1643 +system.membus.trans_dist::ReadExReq 226 +system.membus.trans_dist::ReadExResp 226 +system.membus.trans_dist::ReadSharedReq 1643 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3738 +system.membus.pkt_count::total 3738 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 119616 +system.membus.pkt_size::total 119616 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 1869 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev -0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 1869 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 1869 +system.membus.reqLayer0.occupancy 2188500 +system.membus.reqLayer0.utilization 0.5 +system.membus.respLayer1.occupancy 9936000 +system.membus.respLayer1.utilization 2.3 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.ini index 22d4ff3c2..aad6a62ac 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.ini @@ -65,7 +65,7 @@ SSITSize=1024 activity=0 backComSize=5 branchPred=system.cpu.branchPred -cachePorts=200 +cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 @@ -111,6 +111,7 @@ numIQEntries=64 numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 +numPhysVecRegs=256 numROBEntries=192 numRobs=1 numThreads=1 @@ -139,9 +140,11 @@ socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer trapLatency=13 +wait_for_remote_gdb=false wbWidth=8 workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side @@ -715,7 +718,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=insttest cwd= drivers= @@ -724,14 +727,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64f/insttest gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.json index 2675fc23a..8be1a983d 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.json +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.json @@ -311,21 +311,22 @@ "uid": 100, "pid": 100, "kvmInSE": false, - "cxx_class": "LiveProcess", - "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest", + "cxx_class": "Process", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64f/insttest", "drivers": [], "system": "system", "gid": 100, "eventq_index": 0, "env": [], - "input": "cin", - "ppid": 99, - "type": "LiveProcess", + "maxStackSize": 67108864, + "ppid": 0, + "type": "Process", "cwd": "", + "pgid": 100, "simpoint": 0, "euid": 100, + "input": "cin", "path": "system.cpu.workload", - "max_stack_size": 67108864, "name": "workload", "cmd": [ "insttest" @@ -350,6 +351,7 @@ "decodeToFetchDelay": 1, "renameWidth": 8, "numThreads": 1, + "syscallRetryLatency": 10000, "squashWidth": 8, "function_trace": false, "backComSize": 5, @@ -968,6 +970,8 @@ "switched_out": false, "smtLSQPolicy": "Partitioned", "fetchBufferSize": 64, + "wait_for_remote_gdb": false, + "cacheStorePorts": 200, "simpoint_start_insts": [], "max_insts_any_thread": 0, "smtROBThreshold": 100, @@ -1077,7 +1081,6 @@ "issueWidth": 8, "LSQCheckLoads": true, "commitToRenameDelay": 1, - "cachePorts": 200, "system": "system", "checker": null, "numPhysFloatRegs": 256, @@ -1085,6 +1088,7 @@ "default_p_state": "UNDEFINED", "type": "DerivO3CPU", "wbWidth": 8, + "numPhysVecRegs": 256, "interrupts": [ { "eventq_index": 0, diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simerr index 85a6a33ad..6c18cc52d 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simerr +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simerr @@ -1,4 +1,6 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Unknown operating system; assuming Linux. warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings. + Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest' +info: Increasing stack size by one page. diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simout index 44893f204..b0c999de1 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simout +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simout @@ -3,14 +3,12 @@ Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv6 gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 30 2016 14:33:35 -gem5 started Nov 30 2016 16:18:32 -gem5 executing on zizzer, pid 34077 -command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/o3-timing +gem5 compiled Jul 13 2017 17:09:45 +gem5 started Jul 13 2017 17:09:50 +gem5 executing on boldrock, pid 1347 +command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/o3-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. clear fsflags: PASS flw: PASS fsw: PASS @@ -118,4 +116,105 @@ fcvt.w.s, truncate negative: PASS fcvt.w.s, 0.0: PASS fcvt.w.s, -0.0: PASS fcvt.w.s, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) -Exiting @ tick 113397000 because target called exit() +fcvt.w.s, underflow: PASS +fcvt.w.s, infinity: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +fcvt.w.s, -infinity: PASS +fcvt.w.s, quiet NaN: PASS +fcvt.w.s, quiet -NaN: PASS +fcvt.w.s, signaling NaN: PASS +fcvt.wu.s, truncate positive: PASS +fcvt.wu.s, truncate negative: PASS +fcvt.wu.s, 0.0: PASS +fcvt.wu.s, -0.0: PASS +fcvt.wu.s, overflow: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.s, underflow: PASS +fcvt.wu.s, infinity: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.s, -infinity: PASS +fcvt.wu.s, quiet NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.s, quiet -NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.s, signaling NaN: PASS +fmv.x.s, positive: PASS +fmv.x.s, negative: PASS +fmv.x.s, 0.0: PASS +fmv.x.s, -0.0: PASS +feq.s, equal: PASS +feq.s, not equal: PASS +feq.s, 0 == -0: PASS +feq.s, quiet NaN first: PASS +feq.s, quiet NaN second: PASS +feq.s, quiet NaN both: PASS +feq.s, signaling NaN first: PASS +feq.s, signaling NaN second: PASS +feq.s, signaling NaN both: PASS +flt.s, equal: PASS +flt.s, less: PASS +flt.s, greater: PASS +flt.s, quiet NaN first: PASS +flt.s, quiet NaN second: PASS +flt.s, quiet NaN both: PASS +flt.s, signaling NaN first: PASS +flt.s, signaling NaN second: PASS +flt.s, signaling NaN both: PASS +fle.s, equal: PASS +fle.s, less: PASS +fle.s, greater: PASS +fle.s, 0 == -0: PASS +fle.s, quiet NaN first: PASS +fle.s, quiet NaN second: PASS +fle.s, quiet NaN both: PASS +fle.s, signaling NaN first: PASS +fle.s, signaling NaN second: PASS +fle.s, signaling NaN both: PASS +fclass.s, -infinity: PASS +fclass.s, -normal: PASS +fclass.s, -subnormal: PASS +fclass.s, -0.0: PASS +fclass.s, 0.0: PASS +fclass.s, subnormal: PASS +fclass.s, normal: PASS +fclass.s, infinity: PASS +fclass.s, signaling NaN: PASS +fclass.s, quiet NaN: PASS +fcvt.s.w, 0: PASS +fcvt.s.w, negative: PASS +fcvt.s.w, truncate: PASS +fcvt.s.wu, 0: PASS +fcvt.s.wu: PASS +fcvt.s.wu, truncate: PASS +fmv.s.x: PASS +fmv.s.x, truncate: PASS +fsrm: PASS +fsflags: PASS +fscsr: PASS +restore initial round mode: PASS +fcvt.l.s, truncate positive: PASS +fcvt.l.s, truncate negative: PASS +fcvt.l.s, 0.0: PASS +fcvt.l.s, -0.0: PASS +fcvt.l.s, 32-bit overflow: PASS +fcvt.l.s, overflow: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.l.s, underflow: PASS +fcvt.l.s, infinity: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.l.s, -infinity: PASS +fcvt.l.s, quiet NaN: PASS +fcvt.l.s, quiet -NaN: PASS +fcvt.l.s, signaling NaN: PASS +fcvt.lu.s, truncate positive: PASS +fcvt.lu.s, truncate negative: PASS +fcvt.lu.s, 0.0: PASS +fcvt.lu.s, -0.0: PASS +fcvt.lu.s, 32-bit overflow: PASS +fcvt.lu.s, overflow: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.lu.s, underflow: PASS +fcvt.lu.s, infinity: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.lu.s, -infinity: PASS +fcvt.lu.s, quiet NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 9223372036854775808) +fcvt.lu.s, quiet -NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 9223372036854775808) +fcvt.lu.s, signaling NaN: PASS +fcvt.s.l, 0: PASS +fcvt.s.l, negative: PASS +fcvt.s.l, 32-bit truncate: PASS +fcvt.s.lu, 0: PASS +fcvt.s.lu: PASS +fcvt.s.lu, 32-bit truncate: PASS +Exiting @ tick 334241000 because exiting with last active thread context diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/stats.txt index d17cb8543..4fb2b4c52 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/stats.txt @@ -1,1020 +1,1059 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000113 # Number of seconds simulated -sim_ticks 113383000 # Number of ticks simulated -final_tick 113383000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 167766 # Simulator instruction rate (inst/s) -host_op_rate 167765 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 84106882 # Simulator tick rate (ticks/s) -host_mem_usage 263760 # Number of bytes of host memory used -host_seconds 1.35 # Real time elapsed on the host -sim_insts 226159 # Number of instructions simulated -sim_ops 226159 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 65920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 19264 # Number of bytes read from this memory -system.physmem.bytes_read::total 85184 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 65920 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 65920 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 1030 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 301 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1331 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 581392272 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 169902014 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 751294286 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 581392272 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 581392272 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 581392272 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 169902014 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 751294286 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1331 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 1331 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 85184 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 85184 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 174 # Per bank write bursts -system.physmem.perBankRdBursts::1 18 # Per bank write bursts -system.physmem.perBankRdBursts::2 15 # Per bank write bursts -system.physmem.perBankRdBursts::3 82 # Per bank write bursts -system.physmem.perBankRdBursts::4 194 # Per bank write bursts -system.physmem.perBankRdBursts::5 254 # Per bank write bursts -system.physmem.perBankRdBursts::6 22 # Per bank write bursts -system.physmem.perBankRdBursts::7 4 # Per bank write bursts -system.physmem.perBankRdBursts::8 25 # Per bank write bursts -system.physmem.perBankRdBursts::9 103 # Per bank write bursts -system.physmem.perBankRdBursts::10 150 # Per bank write bursts -system.physmem.perBankRdBursts::11 145 # Per bank write bursts -system.physmem.perBankRdBursts::12 50 # Per bank write bursts -system.physmem.perBankRdBursts::13 52 # Per bank write bursts -system.physmem.perBankRdBursts::14 14 # Per bank write bursts -system.physmem.perBankRdBursts::15 29 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 113277000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1331 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 810 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 368 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 44 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 212 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 390.641509 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 252.461189 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 341.274727 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 49 23.11% 23.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43 20.28% 43.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 38 17.92% 61.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 18 8.49% 69.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13 6.13% 75.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 8 3.77% 79.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6 2.83% 82.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5 2.36% 84.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 32 15.09% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 212 # Bytes accessed per row activation -system.physmem.totQLat 17606250 # Total ticks spent queuing -system.physmem.totMemAccLat 42562500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6655000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13227.84 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31977.84 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 751.29 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 751.29 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 5.87 # Data bus utilization in percentage -system.physmem.busUtilRead 5.87 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.58 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 1107 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.17 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 85106.69 # Average gap between requests -system.physmem.pageHitRate 83.17 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 771120 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 390885 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 5447820 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 9821100 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 199200 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 40147950 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 1260960 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 66643995 # Total energy per rank (pJ) -system.physmem_0.averagePower 587.773777 # Core power per rank (mW) -system.physmem_0.totalIdleTime 90897000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 89500 # Time in different power states -system.physmem_0.memoryStateTime::REF 3640000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 3282750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 18328750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 88042000 # Time in different power states -system.physmem_1.actEnergy 828240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 413655 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4055520 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 7853460 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 220320 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 41175660 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 2031360 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 65183175 # Total energy per rank (pJ) -system.physmem_1.averagePower 574.889920 # Core power per rank (mW) -system.physmem_1.totalIdleTime 95520250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 174500 # Time in different power states -system.physmem_1.memoryStateTime::REF 3640000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 5288750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 13978500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 90301250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 78097 # Number of BP lookups -system.cpu.branchPred.condPredicted 47857 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4973 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 59652 # Number of BTB lookups -system.cpu.branchPred.BTBHits 36130 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 60.567961 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 14779 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 6634 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 8145 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 2576 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 115 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 113383000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 226767 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 73708 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 336580 # Number of instructions fetch has processed -system.cpu.fetch.Branches 78097 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42764 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 87814 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 10240 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 400 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 177 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 60514 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2320 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 167219 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.012810 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.818543 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 90347 54.03% 54.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 11793 7.05% 61.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 13895 8.31% 69.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 11689 6.99% 76.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 5745 3.44% 79.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6911 4.13% 83.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2836 1.70% 85.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4645 2.78% 88.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 19358 11.58% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 167219 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.344393 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.484255 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 72610 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 18818 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 70228 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1268 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4295 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 35338 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 921 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 310147 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2548 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4295 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 75141 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8221 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 3161 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 68810 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 7591 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 298778 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 161 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 69 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 743 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 6500 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 207984 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 389381 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 387034 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2347 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 155141 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 52843 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 133 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 133 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 3092 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 62122 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 43306 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1169 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 342 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 273422 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 166 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 261550 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 571 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 47419 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 26031 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 167219 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.564117 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.884378 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 67857 40.58% 40.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 36223 21.66% 62.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 23953 14.32% 76.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10828 6.48% 83.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10307 6.16% 89.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8097 4.84% 94.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7553 4.52% 98.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1302 0.78% 99.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1099 0.66% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 167219 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 716 10.62% 10.62% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 10.62% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 10.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 10.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.62% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2981 44.22% 54.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2955 43.84% 98.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 88 1.31% 99.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 1 0.01% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 117 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 159688 61.05% 61.10% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 326 0.12% 61.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 44 0.02% 61.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 170 0.06% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 120 0.05% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 58 0.02% 61.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 30 0.01% 61.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 12 0.00% 61.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 5 0.00% 61.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 59226 22.64% 84.04% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 40848 15.62% 99.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 727 0.28% 99.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 179 0.07% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 261550 # Type of FU issued -system.cpu.iq.rate 1.153387 # Inst issue rate -system.cpu.iq.fu_busy_cnt 6741 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.025773 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 694940 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 318115 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 249943 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2691 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2944 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1007 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266784 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1390 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5624 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 10411 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 34 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 41 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6077 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 9 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 117 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4295 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4907 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 918 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 273579 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 3363 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 62122 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 43306 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 157 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 908 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1293 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3450 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 4743 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 254044 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 58349 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7506 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 98069 # number of memory reference insts executed -system.cpu.iew.exec_branches 57083 # Number of branches executed -system.cpu.iew.exec_stores 39720 # Number of stores executed -system.cpu.iew.exec_rate 1.120286 # Inst execution rate -system.cpu.iew.wb_sent 252158 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 250950 # cumulative count of insts written-back -system.cpu.iew.wb_producers 95653 # num instructions producing a value -system.cpu.iew.wb_consumers 131997 # num instructions consuming a value -system.cpu.iew.wb_rate 1.106643 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.724660 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 47451 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 117 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 4148 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158171 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.429839 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.156696 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 83501 52.79% 52.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 25809 16.32% 69.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14383 9.09% 78.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 10997 6.95% 85.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5860 3.70% 88.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 5977 3.78% 92.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3309 2.09% 94.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1266 0.80% 95.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7069 4.47% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158171 # Number of insts commited each cycle -system.cpu.commit.committedInsts 226159 # Number of instructions committed -system.cpu.commit.committedOps 226159 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 88940 # Number of memory references committed -system.cpu.commit.loads 51711 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 50405 # Number of branches committed -system.cpu.commit.fp_insts 862 # Number of committed floating point instructions. -system.cpu.commit.int_insts 225991 # Number of committed integer instructions. -system.cpu.commit.function_calls 16616 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 2 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 136540 60.37% 60.37% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 325 0.14% 60.52% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 40 0.02% 60.54% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 104 0.05% 60.58% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 119 0.05% 60.63% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 43 0.02% 60.65% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 30 0.01% 60.67% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 60.67% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 11 0.00% 60.67% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 60.67% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 5 0.00% 60.67% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 60.67% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 60.67% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 60.67% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 60.67% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 60.67% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 60.67% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 60.67% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 60.67% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 60.67% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 60.67% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 60.67% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 60.67% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 60.67% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 60.67% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 60.67% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 60.67% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 60.67% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 60.67% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 60.67% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 60.67% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 51297 22.68% 83.36% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 37093 16.40% 99.76% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 414 0.18% 99.94% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 136 0.06% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 226159 # Class of committed instruction -system.cpu.commit.bw_lim_events 7069 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 423217 # The number of ROB reads -system.cpu.rob.rob_writes 556357 # The number of ROB writes -system.cpu.timesIdled 459 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 59548 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 226159 # Number of Instructions Simulated -system.cpu.committedOps 226159 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.002688 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.002688 # CPI: Total CPI of All Threads -system.cpu.ipc 0.997319 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.997319 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 329254 # number of integer regfile reads -system.cpu.int_regfile_writes 174794 # number of integer regfile writes -system.cpu.fp_regfile_reads 878 # number of floating regfile reads -system.cpu.fp_regfile_writes 754 # number of floating regfile writes -system.cpu.misc_regfile_reads 446 # number of misc regfile reads -system.cpu.misc_regfile_writes 313 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 244.658569 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 87565 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 301 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 290.913621 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 244.658569 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.059731 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.059731 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 301 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 194 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.073486 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179301 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179301 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 51833 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 51833 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 35732 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 35732 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 87565 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 87565 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 87565 # number of overall hits -system.cpu.dcache.overall_hits::total 87565 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 438 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 438 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1497 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1497 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1935 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1935 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1935 # number of overall misses -system.cpu.dcache.overall_misses::total 1935 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 36015000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36015000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 97868425 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 97868425 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 133883425 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 133883425 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 133883425 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 133883425 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 52271 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 52271 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 37229 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 37229 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 89500 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 89500 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 89500 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 89500 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008379 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.008379 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.040211 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.040211 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.021620 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.021620 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.021620 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.021620 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 82226.027397 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 82226.027397 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65376.369405 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65376.369405 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 69190.400517 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69190.400517 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 69190.400517 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69190.400517 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6103 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 79 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 77.253165 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 341 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 341 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1293 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1293 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1634 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1634 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1634 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1634 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 97 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 97 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 204 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 204 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 301 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 301 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 301 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8546500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8546500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17206500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 17206500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25753000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 25753000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25753000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 25753000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001856 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001856 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005480 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005480 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003363 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003363 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003363 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003363 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 88108.247423 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 88108.247423 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 84345.588235 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84345.588235 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 85558.139535 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 85558.139535 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 85558.139535 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 85558.139535 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 70 # number of replacements -system.cpu.icache.tags.tagsinuse 535.835535 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 59155 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1035 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 57.154589 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 535.835535 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.261638 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.261638 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 965 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 738 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.471191 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 122053 # Number of tag accesses -system.cpu.icache.tags.data_accesses 122053 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 59155 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 59155 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 59155 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 59155 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 59155 # number of overall hits -system.cpu.icache.overall_hits::total 59155 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1354 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1354 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1354 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1354 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1354 # number of overall misses -system.cpu.icache.overall_misses::total 1354 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 109143498 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 109143498 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 109143498 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 109143498 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 109143498 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 109143498 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 60509 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 60509 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 60509 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 60509 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 60509 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 60509 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.022377 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.022377 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.022377 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.022377 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.022377 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.022377 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80608.196455 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 80608.196455 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 80608.196455 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 80608.196455 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 80608.196455 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 80608.196455 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2475 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 34 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 72.794118 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 70 # number of writebacks -system.cpu.icache.writebacks::total 70 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 319 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 319 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 319 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 319 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 319 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 319 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1035 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1035 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1035 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1035 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1035 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1035 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 86827498 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 86827498 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 86827498 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 86827498 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 86827498 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 86827498 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.017105 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.017105 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.017105 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.017105 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.017105 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.017105 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83891.302415 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83891.302415 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83891.302415 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 83891.302415 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83891.302415 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 83891.302415 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 808.901136 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 72 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1331 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.054095 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 564.214692 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 244.686444 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017218 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.007467 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.024686 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 1331 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 880 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 338 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.040619 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12555 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12555 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackClean_hits::writebacks 70 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 70 # number of WritebackClean hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits -system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 204 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 204 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1030 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1030 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 97 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 97 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1030 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 301 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1331 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1030 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 301 # number of overall misses -system.cpu.l2cache.overall_misses::total 1331 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16900000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 16900000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 85245000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 85245000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8401000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 8401000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 85245000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 25301000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 110546000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 85245000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 25301000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 110546000 # number of overall miss cycles -system.cpu.l2cache.WritebackClean_accesses::writebacks 70 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 70 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 204 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 204 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1032 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1032 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 97 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 97 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1032 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 301 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1333 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1032 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 301 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1333 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.998062 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.998062 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.998062 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.998500 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998062 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.998500 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82843.137255 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82843.137255 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82762.135922 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82762.135922 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86608.247423 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86608.247423 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82762.135922 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84056.478405 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 83054.845980 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82762.135922 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84056.478405 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 83054.845980 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 204 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 204 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1030 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1030 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 97 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 97 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1030 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 301 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1331 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1030 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 301 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1331 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14860000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14860000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 74945000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 74945000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7431000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7431000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 74945000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22291000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 97236000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 74945000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22291000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 97236000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.998062 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.998062 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998062 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.998500 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998062 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.998500 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72843.137255 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72843.137255 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72762.135922 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72762.135922 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76608.247423 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76608.247423 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72762.135922 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74056.478405 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73054.845980 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72762.135922 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74056.478405 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73054.845980 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1406 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1132 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 70 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 204 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 204 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1035 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 97 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2137 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 602 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2739 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 70528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 19264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 89792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 3 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 192 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1336 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002246 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.047351 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1333 99.78% 99.78% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3 0.22% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1336 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 773000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1552500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 451500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 1331 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1127 # Transaction distribution -system.membus.trans_dist::ReadExReq 204 # Transaction distribution -system.membus.trans_dist::ReadExResp 204 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1127 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2662 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2662 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 85184 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 85184 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1331 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1331 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1331 # Request fanout histogram -system.membus.reqLayer0.occupancy 1624000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 7014000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.2 # Layer utilization (%) +sim_seconds 0.000334 +sim_ticks 334241000 +final_tick 334241000 +sim_freq 1000000000000 +host_inst_rate 3258 +host_op_rate 3268 +host_tick_rate 2618086 +host_mem_usage 272352 +host_seconds 127.66 +sim_insts 416024 +sim_ops 417277 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 334241000 +system.physmem.bytes_read::cpu.inst 79616 +system.physmem.bytes_read::cpu.data 34432 +system.physmem.bytes_read::total 114048 +system.physmem.bytes_inst_read::cpu.inst 79616 +system.physmem.bytes_inst_read::total 79616 +system.physmem.num_reads::cpu.inst 1244 +system.physmem.num_reads::cpu.data 538 +system.physmem.num_reads::total 1782 +system.physmem.bw_read::cpu.inst 238199383 +system.physmem.bw_read::cpu.data 103015488 +system.physmem.bw_read::total 341214871 +system.physmem.bw_inst_read::cpu.inst 238199383 +system.physmem.bw_inst_read::total 238199383 +system.physmem.bw_total::cpu.inst 238199383 +system.physmem.bw_total::cpu.data 103015488 +system.physmem.bw_total::total 341214871 +system.physmem.readReqs 1782 +system.physmem.writeReqs 0 +system.physmem.readBursts 1782 +system.physmem.writeBursts 0 +system.physmem.bytesReadDRAM 114048 +system.physmem.bytesReadWrQ 0 +system.physmem.bytesWritten 0 +system.physmem.bytesReadSys 114048 +system.physmem.bytesWrittenSys 0 +system.physmem.servicedByWrQ 0 +system.physmem.mergedWrBursts 0 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 238 +system.physmem.perBankRdBursts::1 261 +system.physmem.perBankRdBursts::2 164 +system.physmem.perBankRdBursts::3 171 +system.physmem.perBankRdBursts::4 146 +system.physmem.perBankRdBursts::5 102 +system.physmem.perBankRdBursts::6 103 +system.physmem.perBankRdBursts::7 59 +system.physmem.perBankRdBursts::8 59 +system.physmem.perBankRdBursts::9 52 +system.physmem.perBankRdBursts::10 21 +system.physmem.perBankRdBursts::11 42 +system.physmem.perBankRdBursts::12 76 +system.physmem.perBankRdBursts::13 78 +system.physmem.perBankRdBursts::14 92 +system.physmem.perBankRdBursts::15 118 +system.physmem.perBankWrBursts::0 0 +system.physmem.perBankWrBursts::1 0 +system.physmem.perBankWrBursts::2 0 +system.physmem.perBankWrBursts::3 0 +system.physmem.perBankWrBursts::4 0 +system.physmem.perBankWrBursts::5 0 +system.physmem.perBankWrBursts::6 0 +system.physmem.perBankWrBursts::7 0 +system.physmem.perBankWrBursts::8 0 +system.physmem.perBankWrBursts::9 0 +system.physmem.perBankWrBursts::10 0 +system.physmem.perBankWrBursts::11 0 +system.physmem.perBankWrBursts::12 0 +system.physmem.perBankWrBursts::13 0 +system.physmem.perBankWrBursts::14 0 +system.physmem.perBankWrBursts::15 0 +system.physmem.numRdRetry 0 +system.physmem.numWrRetry 0 +system.physmem.totGap 334109500 +system.physmem.readPktSize::0 0 +system.physmem.readPktSize::1 0 +system.physmem.readPktSize::2 0 +system.physmem.readPktSize::3 0 +system.physmem.readPktSize::4 0 +system.physmem.readPktSize::5 0 +system.physmem.readPktSize::6 1782 +system.physmem.writePktSize::0 0 +system.physmem.writePktSize::1 0 +system.physmem.writePktSize::2 0 +system.physmem.writePktSize::3 0 +system.physmem.writePktSize::4 0 +system.physmem.writePktSize::5 0 +system.physmem.writePktSize::6 0 +system.physmem.rdQLenPdf::0 1136 +system.physmem.rdQLenPdf::1 450 +system.physmem.rdQLenPdf::2 141 +system.physmem.rdQLenPdf::3 42 +system.physmem.rdQLenPdf::4 11 +system.physmem.rdQLenPdf::5 2 +system.physmem.rdQLenPdf::6 0 +system.physmem.rdQLenPdf::7 0 +system.physmem.rdQLenPdf::8 0 +system.physmem.rdQLenPdf::9 0 +system.physmem.rdQLenPdf::10 0 +system.physmem.rdQLenPdf::11 0 +system.physmem.rdQLenPdf::12 0 +system.physmem.rdQLenPdf::13 0 +system.physmem.rdQLenPdf::14 0 +system.physmem.rdQLenPdf::15 0 +system.physmem.rdQLenPdf::16 0 +system.physmem.rdQLenPdf::17 0 +system.physmem.rdQLenPdf::18 0 +system.physmem.rdQLenPdf::19 0 +system.physmem.rdQLenPdf::20 0 +system.physmem.rdQLenPdf::21 0 +system.physmem.rdQLenPdf::22 0 +system.physmem.rdQLenPdf::23 0 +system.physmem.rdQLenPdf::24 0 +system.physmem.rdQLenPdf::25 0 +system.physmem.rdQLenPdf::26 0 +system.physmem.rdQLenPdf::27 0 +system.physmem.rdQLenPdf::28 0 +system.physmem.rdQLenPdf::29 0 +system.physmem.rdQLenPdf::30 0 +system.physmem.rdQLenPdf::31 0 +system.physmem.wrQLenPdf::0 0 +system.physmem.wrQLenPdf::1 0 +system.physmem.wrQLenPdf::2 0 +system.physmem.wrQLenPdf::3 0 +system.physmem.wrQLenPdf::4 0 +system.physmem.wrQLenPdf::5 0 +system.physmem.wrQLenPdf::6 0 +system.physmem.wrQLenPdf::7 0 +system.physmem.wrQLenPdf::8 0 +system.physmem.wrQLenPdf::9 0 +system.physmem.wrQLenPdf::10 0 +system.physmem.wrQLenPdf::11 0 +system.physmem.wrQLenPdf::12 0 +system.physmem.wrQLenPdf::13 0 +system.physmem.wrQLenPdf::14 0 +system.physmem.wrQLenPdf::15 0 +system.physmem.wrQLenPdf::16 0 +system.physmem.wrQLenPdf::17 0 +system.physmem.wrQLenPdf::18 0 +system.physmem.wrQLenPdf::19 0 +system.physmem.wrQLenPdf::20 0 +system.physmem.wrQLenPdf::21 0 +system.physmem.wrQLenPdf::22 0 +system.physmem.wrQLenPdf::23 0 +system.physmem.wrQLenPdf::24 0 +system.physmem.wrQLenPdf::25 0 +system.physmem.wrQLenPdf::26 0 +system.physmem.wrQLenPdf::27 0 +system.physmem.wrQLenPdf::28 0 +system.physmem.wrQLenPdf::29 0 +system.physmem.wrQLenPdf::30 0 +system.physmem.wrQLenPdf::31 0 +system.physmem.wrQLenPdf::32 0 +system.physmem.wrQLenPdf::33 0 +system.physmem.wrQLenPdf::34 0 +system.physmem.wrQLenPdf::35 0 +system.physmem.wrQLenPdf::36 0 +system.physmem.wrQLenPdf::37 0 +system.physmem.wrQLenPdf::38 0 +system.physmem.wrQLenPdf::39 0 +system.physmem.wrQLenPdf::40 0 +system.physmem.wrQLenPdf::41 0 +system.physmem.wrQLenPdf::42 0 +system.physmem.wrQLenPdf::43 0 +system.physmem.wrQLenPdf::44 0 +system.physmem.wrQLenPdf::45 0 +system.physmem.wrQLenPdf::46 0 +system.physmem.wrQLenPdf::47 0 +system.physmem.wrQLenPdf::48 0 +system.physmem.wrQLenPdf::49 0 +system.physmem.wrQLenPdf::50 0 +system.physmem.wrQLenPdf::51 0 +system.physmem.wrQLenPdf::52 0 +system.physmem.wrQLenPdf::53 0 +system.physmem.wrQLenPdf::54 0 +system.physmem.wrQLenPdf::55 0 +system.physmem.wrQLenPdf::56 0 +system.physmem.wrQLenPdf::57 0 +system.physmem.wrQLenPdf::58 0 +system.physmem.wrQLenPdf::59 0 +system.physmem.wrQLenPdf::60 0 +system.physmem.wrQLenPdf::61 0 +system.physmem.wrQLenPdf::62 0 +system.physmem.wrQLenPdf::63 0 +system.physmem.bytesPerActivate::samples 400 +system.physmem.bytesPerActivate::mean 278.239999 +system.physmem.bytesPerActivate::gmean 189.218763 +system.physmem.bytesPerActivate::stdev 254.162780 +system.physmem.bytesPerActivate::0-127 113 28.24% 28.24% +system.physmem.bytesPerActivate::128-255 118 29.49% 57.74% +system.physmem.bytesPerActivate::256-383 52 12.99% 70.74% +system.physmem.bytesPerActivate::384-511 42 10.49% 81.24% +system.physmem.bytesPerActivate::512-639 33 8.24% 89.49% +system.physmem.bytesPerActivate::640-767 10 2.49% 91.99% +system.physmem.bytesPerActivate::768-895 7 1.74% 93.74% +system.physmem.bytesPerActivate::896-1023 11 2.74% 96.49% +system.physmem.bytesPerActivate::1024-1151 14 3.49% 99.99% +system.physmem.bytesPerActivate::total 400 +system.physmem.totQLat 28596250 +system.physmem.totMemAccLat 62008750 +system.physmem.totBusLat 8910000 +system.physmem.avgQLat 16047.27 +system.physmem.avgBusLat 5000.00 +system.physmem.avgMemAccLat 34797.27 +system.physmem.avgRdBW 341.21 +system.physmem.avgWrBW 0.00 +system.physmem.avgRdBWSys 341.21 +system.physmem.avgWrBWSys 0.00 +system.physmem.peakBW 12800.00 +system.physmem.busUtil 2.66 +system.physmem.busUtilRead 2.66 +system.physmem.busUtilWrite 0.00 +system.physmem.avgRdQLen 1.38 +system.physmem.avgWrQLen 0.00 +system.physmem.readRowHits 1368 +system.physmem.writeRowHits 0 +system.physmem.readRowHitRate 76.76 +system.physmem.writeRowHitRate nan +system.physmem.avgGap 187491.30 +system.physmem.pageHitRate 76.76 +system.physmem_0.actEnergy 1927800 +system.physmem_0.preEnergy 998085 +system.physmem_0.readEnergy 8882160 +system.physmem_0.writeEnergy 0 +system.physmem_0.refreshEnergy 25814880 +system.physmem_0.actBackEnergy 18293580 +system.physmem_0.preBackEnergy 540000 +system.physmem_0.actPowerDownEnergy 129050280 +system.physmem_0.prePowerDownEnergy 3729600 +system.physmem_0.selfRefreshEnergy 0 +system.physmem_0.totalEnergy 189236385 +system.physmem_0.averagePower 566.167057 +system.physmem_0.totalIdleTime 292641750 +system.physmem_0.memoryStateTime::IDLE 245500 +system.physmem_0.memoryStateTime::REF 10920000 +system.physmem_0.memoryStateTime::SREF 0 +system.physmem_0.memoryStateTime::PRE_PDN 9705500 +system.physmem_0.memoryStateTime::ACT 30338500 +system.physmem_0.memoryStateTime::ACT_PDN 283031500 +system.physmem_1.actEnergy 1028160 +system.physmem_1.preEnergy 519915 +system.physmem_1.readEnergy 3841320 +system.physmem_1.writeEnergy 0 +system.physmem_1.refreshEnergy 11678160 +system.physmem_1.actBackEnergy 8555700 +system.physmem_1.preBackEnergy 555360 +system.physmem_1.actPowerDownEnergy 38406030 +system.physmem_1.prePowerDownEnergy 10018560 +system.physmem_1.selfRefreshEnergy 50549220 +system.physmem_1.totalEnergy 125152425 +system.physmem_1.averagePower 374.437401 +system.physmem_1.totalIdleTime 313185500 +system.physmem_1.memoryStateTime::IDLE 973000 +system.physmem_1.memoryStateTime::REF 4958000 +system.physmem_1.memoryStateTime::SREF 203719000 +system.physmem_1.memoryStateTime::PRE_PDN 26090000 +system.physmem_1.memoryStateTime::ACT 14271500 +system.physmem_1.memoryStateTime::ACT_PDN 84229500 +system.pwrStateResidencyTicks::UNDEFINED 334241000 +system.cpu.branchPred.lookups 127435 +system.cpu.branchPred.condPredicted 89833 +system.cpu.branchPred.condIncorrect 23395 +system.cpu.branchPred.BTBLookups 81108 +system.cpu.branchPred.BTBHits 45160 +system.cpu.branchPred.BTBCorrect 0 +system.cpu.branchPred.BTBHitPct 55.678847 +system.cpu.branchPred.usedRAS 0 +system.cpu.branchPred.RASInCorrect 0 +system.cpu.branchPred.indirectLookups 25902 +system.cpu.branchPred.indirectHits 14811 +system.cpu.branchPred.indirectMisses 11091 +system.cpu.branchPredindirectMispredicted 5072 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 216 +system.cpu.pwrStateResidencyTicks::ON 334241000 +system.cpu.numCycles 668483 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.fetch.icacheStallCycles 128666 +system.cpu.fetch.Insts 570376 +system.cpu.fetch.Branches 127435 +system.cpu.fetch.predictedBranches 59971 +system.cpu.fetch.Cycles 411263 +system.cpu.fetch.SquashCycles 47272 +system.cpu.fetch.MiscStallCycles 19 +system.cpu.fetch.PendingTrapStallCycles 76 +system.cpu.fetch.IcacheWaitRetryStallCycles 83 +system.cpu.fetch.CacheLines 90304 +system.cpu.fetch.IcacheSquashes 2386 +system.cpu.fetch.rateDist::samples 563743 +system.cpu.fetch.rateDist::mean 1.014057 +system.cpu.fetch.rateDist::stdev 0.982669 +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% +system.cpu.fetch.rateDist::0 163182 28.94% 28.94% +system.cpu.fetch.rateDist::1 291750 51.75% 80.69% +system.cpu.fetch.rateDist::2 72803 12.91% 93.61% +system.cpu.fetch.rateDist::3 20031 3.55% 97.16% +system.cpu.fetch.rateDist::4 9935 1.76% 98.92% +system.cpu.fetch.rateDist::5 3180 0.56% 99.49% +system.cpu.fetch.rateDist::6 1981 0.35% 99.84% +system.cpu.fetch.rateDist::7 355 0.06% 99.90% +system.cpu.fetch.rateDist::8 526 0.09% 99.99% +system.cpu.fetch.rateDist::overflows 0 0.00% 99.99% +system.cpu.fetch.rateDist::min_value 0 +system.cpu.fetch.rateDist::max_value 8 +system.cpu.fetch.rateDist::total 563743 +system.cpu.fetch.branchRate 0.190633 +system.cpu.fetch.rate 0.853239 +system.cpu.decode.IdleCycles 145658 +system.cpu.decode.BlockedCycles 50036 +system.cpu.decode.RunCycles 350465 +system.cpu.decode.UnblockCycles 2505 +system.cpu.decode.SquashCycles 15079 +system.cpu.decode.BranchResolved 43531 +system.cpu.decode.BranchMispred 8717 +system.cpu.decode.DecodedInsts 520617 +system.cpu.decode.SquashedInsts 13886 +system.cpu.rename.SquashCycles 15079 +system.cpu.rename.IdleCycles 162879 +system.cpu.rename.BlockCycles 5626 +system.cpu.rename.serializeStallCycles 37161 +system.cpu.rename.RunCycles 335687 +system.cpu.rename.UnblockCycles 7311 +system.cpu.rename.RenamedInsts 502269 +system.cpu.rename.ROBFullEvents 984 +system.cpu.rename.IQFullEvents 138 +system.cpu.rename.LQFullEvents 1822 +system.cpu.rename.SQFullEvents 3460 +system.cpu.rename.RenamedOperands 337685 +system.cpu.rename.RenameLookups 620018 +system.cpu.rename.int_rename_lookups 618230 +system.cpu.rename.fp_rename_lookups 1788 +system.cpu.rename.CommittedMaps 276598 +system.cpu.rename.UndoneMaps 61087 +system.cpu.rename.serializingInsts 1943 +system.cpu.rename.tempSerializingInsts 1943 +system.cpu.rename.skidInsts 3831 +system.cpu.memDep0.insertedLoads 119278 +system.cpu.memDep0.insertedStores 67494 +system.cpu.memDep0.conflictingLoads 532 +system.cpu.memDep0.conflictingStores 153 +system.cpu.iq.iqInstsAdded 466229 +system.cpu.iq.iqNonSpecInstsAdded 3274 +system.cpu.iq.iqInstsIssued 459327 +system.cpu.iq.iqSquashedInstsIssued 175 +system.cpu.iq.iqSquashedInstsExamined 52219 +system.cpu.iq.iqSquashedOperandsExamined 23838 +system.cpu.iq.iqSquashedNonSpecRemoved 88 +system.cpu.iq.issued_per_cycle::samples 563743 +system.cpu.iq.issued_per_cycle::mean 0.814780 +system.cpu.iq.issued_per_cycle::stdev 0.900911 +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% +system.cpu.iq.issued_per_cycle::0 233488 41.41% 41.41% +system.cpu.iq.issued_per_cycle::1 239164 42.42% 83.84% +system.cpu.iq.issued_per_cycle::2 63723 11.30% 95.14% +system.cpu.iq.issued_per_cycle::3 22016 3.90% 99.05% +system.cpu.iq.issued_per_cycle::4 2579 0.45% 99.50% +system.cpu.iq.issued_per_cycle::5 1083 0.19% 99.70% +system.cpu.iq.issued_per_cycle::6 919 0.16% 99.86% +system.cpu.iq.issued_per_cycle::7 744 0.13% 99.99% +system.cpu.iq.issued_per_cycle::8 27 0.00% 99.99% +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 99.99% +system.cpu.iq.issued_per_cycle::min_value 0 +system.cpu.iq.issued_per_cycle::max_value 8 +system.cpu.iq.issued_per_cycle::total 563743 +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% +system.cpu.iq.fu_full::IntAlu 39 2.95% 2.95% +system.cpu.iq.fu_full::IntMult 0 0.00% 2.95% +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.95% +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.95% +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.95% +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.95% +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.95% +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 2.95% +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.95% +system.cpu.iq.fu_full::FloatMisc 0 0.00% 2.95% +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.95% +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.95% +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.95% +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.95% +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.95% +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.95% +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.95% +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.95% +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.95% +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.95% +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.95% +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.95% +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.95% +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.95% +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.95% +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.95% +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.95% +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.95% +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.95% +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.95% +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.95% +system.cpu.iq.fu_full::MemRead 609 46.13% 49.09% +system.cpu.iq.fu_full::MemWrite 669 50.68% 99.77% +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.77% +system.cpu.iq.fu_full::FloatMemWrite 3 0.22% 99.99% +system.cpu.iq.fu_full::IprAccess 0 0.00% 99.99% +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 99.99% +system.cpu.iq.FU_type_0::No_OpClass 236 0.05% 0.05% +system.cpu.iq.FU_type_0::IntAlu 272906 59.41% 59.46% +system.cpu.iq.FU_type_0::IntMult 677 0.14% 59.61% +system.cpu.iq.FU_type_0::IntDiv 645 0.14% 59.75% +system.cpu.iq.FU_type_0::FloatAdd 128 0.02% 59.78% +system.cpu.iq.FU_type_0::FloatCmp 161 0.03% 59.81% +system.cpu.iq.FU_type_0::FloatCvt 109 0.02% 59.84% +system.cpu.iq.FU_type_0::FloatMult 62 0.01% 59.85% +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 59.85% +system.cpu.iq.FU_type_0::FloatDiv 11 0.00% 59.85% +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 59.85% +system.cpu.iq.FU_type_0::FloatSqrt 5 0.00% 59.85% +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.85% +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.85% +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.85% +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.85% +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.85% +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.85% +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.85% +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.85% +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.85% +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.85% +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.85% +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.85% +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.85% +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.85% +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.85% +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.85% +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.85% +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.85% +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.85% +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.85% +system.cpu.iq.FU_type_0::MemRead 117233 25.52% 85.37% +system.cpu.iq.FU_type_0::MemWrite 66368 14.44% 99.82% +system.cpu.iq.FU_type_0::FloatMemRead 614 0.13% 99.96% +system.cpu.iq.FU_type_0::FloatMemWrite 172 0.03% 99.99% +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 99.99% +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 99.99% +system.cpu.iq.FU_type_0::total 459327 +system.cpu.iq.rate 0.687118 +system.cpu.iq.fu_busy_cnt 1320 +system.cpu.iq.fu_busy_rate 0.002873 +system.cpu.iq.int_inst_queue_reads 1481365 +system.cpu.iq.int_inst_queue_writes 520340 +system.cpu.iq.int_inst_queue_wakeup_accesses 440331 +system.cpu.iq.fp_inst_queue_reads 2527 +system.cpu.iq.fp_inst_queue_writes 1401 +system.cpu.iq.fp_inst_queue_wakeup_accesses 1166 +system.cpu.iq.int_alu_accesses 459146 +system.cpu.iq.fp_alu_accesses 1265 +system.cpu.iew.lsq.thread0.forwLoads 234 +system.cpu.iew.lsq.thread0.invAddrLoads 0 +system.cpu.iew.lsq.thread0.squashedLoads 13780 +system.cpu.iew.lsq.thread0.ignoredResponses 17 +system.cpu.iew.lsq.thread0.memOrderViolation 17 +system.cpu.iew.lsq.thread0.squashedStores 3368 +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 +system.cpu.iew.lsq.thread0.blockedLoads 0 +system.cpu.iew.lsq.thread0.rescheduledLoads 370 +system.cpu.iew.lsq.thread0.cacheBlocked 139 +system.cpu.iew.iewIdleCycles 0 +system.cpu.iew.iewSquashCycles 15079 +system.cpu.iew.iewBlockCycles 4278 +system.cpu.iew.iewUnblockCycles 898 +system.cpu.iew.iewDispatchedInsts 469497 +system.cpu.iew.iewDispSquashedInsts 15026 +system.cpu.iew.iewDispLoadInsts 119278 +system.cpu.iew.iewDispStoreInsts 67494 +system.cpu.iew.iewDispNonSpecInsts 3268 +system.cpu.iew.iewIQFullEvents 22 +system.cpu.iew.iewLSQFullEvents 852 +system.cpu.iew.memOrderViolationEvents 17 +system.cpu.iew.predictedTakenIncorrect 9022 +system.cpu.iew.predictedNotTakenIncorrect 7728 +system.cpu.iew.branchMispredicts 16750 +system.cpu.iew.iewExecutedInsts 445015 +system.cpu.iew.iewExecLoadInsts 114273 +system.cpu.iew.iewExecSquashedInsts 14312 +system.cpu.iew.exec_swp 0 +system.cpu.iew.exec_nop 0 +system.cpu.iew.exec_refs 180226 +system.cpu.iew.exec_branches 96621 +system.cpu.iew.exec_stores 65953 +system.cpu.iew.exec_rate 0.665708 +system.cpu.iew.wb_sent 442183 +system.cpu.iew.wb_count 441497 +system.cpu.iew.wb_producers 142269 +system.cpu.iew.wb_consumers 163893 +system.cpu.iew.wb_rate 0.660446 +system.cpu.iew.wb_fanout 0.868060 +system.cpu.commit.commitSquashedInsts 52233 +system.cpu.commit.commitNonSpecStalls 3180 +system.cpu.commit.branchMispredicts 14848 +system.cpu.commit.committed_per_cycle::samples 545846 +system.cpu.commit.committed_per_cycle::mean 0.764459 +system.cpu.commit.committed_per_cycle::stdev 1.249358 +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% +system.cpu.commit.committed_per_cycle::0 310862 56.95% 56.95% +system.cpu.commit.committed_per_cycle::1 149504 27.38% 84.33% +system.cpu.commit.committed_per_cycle::2 34535 6.32% 90.66% +system.cpu.commit.committed_per_cycle::3 30814 5.64% 96.31% +system.cpu.commit.committed_per_cycle::4 9598 1.75% 98.07% +system.cpu.commit.committed_per_cycle::5 3078 0.56% 98.63% +system.cpu.commit.committed_per_cycle::6 2903 0.53% 99.16% +system.cpu.commit.committed_per_cycle::7 1355 0.24% 99.41% +system.cpu.commit.committed_per_cycle::8 3197 0.58% 99.99% +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 99.99% +system.cpu.commit.committed_per_cycle::min_value 0 +system.cpu.commit.committed_per_cycle::max_value 8 +system.cpu.commit.committed_per_cycle::total 545846 +system.cpu.commit.committedInsts 416024 +system.cpu.commit.committedOps 417277 +system.cpu.commit.swp_count 0 +system.cpu.commit.refs 169624 +system.cpu.commit.loads 105498 +system.cpu.commit.membars 4 +system.cpu.commit.branches 90856 +system.cpu.commit.vec_insts 0 +system.cpu.commit.fp_insts 1163 +system.cpu.commit.int_insts 415220 +system.cpu.commit.function_calls 23050 +system.cpu.commit.op_class_0::No_OpClass 20 0.00% 0.00% +system.cpu.commit.op_class_0::IntAlu 245871 58.92% 58.92% +system.cpu.commit.op_class_0::IntMult 674 0.16% 59.08% +system.cpu.commit.op_class_0::IntDiv 644 0.15% 59.24% +system.cpu.commit.op_class_0::FloatAdd 128 0.03% 59.27% +system.cpu.commit.op_class_0::FloatCmp 161 0.03% 59.31% +system.cpu.commit.op_class_0::FloatCvt 109 0.02% 59.33% +system.cpu.commit.op_class_0::FloatMult 30 0.00% 59.34% +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 59.34% +system.cpu.commit.op_class_0::FloatDiv 11 0.00% 59.34% +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 59.34% +system.cpu.commit.op_class_0::FloatSqrt 5 0.00% 59.34% +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 59.34% +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 59.34% +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 59.34% +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 59.34% +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 59.34% +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 59.34% +system.cpu.commit.op_class_0::SimdMult 0 0.00% 59.34% +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 59.34% +system.cpu.commit.op_class_0::SimdShift 0 0.00% 59.34% +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 59.34% +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 59.34% +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 59.34% +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 59.34% +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 59.34% +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 59.34% +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 59.34% +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 59.34% +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 59.34% +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 59.34% +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 59.34% +system.cpu.commit.op_class_0::MemRead 104951 25.15% 84.50% +system.cpu.commit.op_class_0::MemWrite 63954 15.32% 99.82% +system.cpu.commit.op_class_0::FloatMemRead 547 0.13% 99.95% +system.cpu.commit.op_class_0::FloatMemWrite 172 0.04% 99.99% +system.cpu.commit.op_class_0::IprAccess 0 0.00% 99.99% +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 99.99% +system.cpu.commit.op_class_0::total 417277 +system.cpu.commit.bw_lim_events 3197 +system.cpu.rob.rob_reads 1009364 +system.cpu.rob.rob_writes 956943 +system.cpu.timesIdled 823 +system.cpu.idleCycles 104740 +system.cpu.committedInsts 416024 +system.cpu.committedOps 417277 +system.cpu.cpi 1.606837 +system.cpu.cpi_total 1.606837 +system.cpu.ipc 0.622340 +system.cpu.ipc_total 0.622340 +system.cpu.int_regfile_reads 555010 +system.cpu.int_regfile_writes 293365 +system.cpu.fp_regfile_reads 936 +system.cpu.fp_regfile_writes 759 +system.cpu.misc_regfile_reads 575 +system.cpu.misc_regfile_writes 454 +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 334241000 +system.cpu.dcache.tags.replacements 2 +system.cpu.dcache.tags.tagsinuse 431.348065 +system.cpu.dcache.tags.total_refs 175634 +system.cpu.dcache.tags.sampled_refs 539 +system.cpu.dcache.tags.avg_refs 325.851576 +system.cpu.dcache.tags.warmup_cycle 0 +system.cpu.dcache.tags.occ_blocks::cpu.data 431.348065 +system.cpu.dcache.tags.occ_percent::cpu.data 0.105309 +system.cpu.dcache.tags.occ_percent::total 0.105309 +system.cpu.dcache.tags.occ_task_id_blocks::1024 537 +system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 +system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 +system.cpu.dcache.tags.age_task_id_blocks_1024::2 494 +system.cpu.dcache.tags.occ_task_id_percent::1024 0.131103 +system.cpu.dcache.tags.tag_accesses 355461 +system.cpu.dcache.tags.data_accesses 355461 +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 334241000 +system.cpu.dcache.ReadReq_hits::cpu.data 110953 +system.cpu.dcache.ReadReq_hits::total 110953 +system.cpu.dcache.WriteReq_hits::cpu.data 61296 +system.cpu.dcache.WriteReq_hits::total 61296 +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1694 +system.cpu.dcache.LoadLockedReq_hits::total 1694 +system.cpu.dcache.StoreCondReq_hits::cpu.data 1691 +system.cpu.dcache.StoreCondReq_hits::total 1691 +system.cpu.dcache.demand_hits::cpu.data 172249 +system.cpu.dcache.demand_hits::total 172249 +system.cpu.dcache.overall_hits::cpu.data 172249 +system.cpu.dcache.overall_hits::total 172249 +system.cpu.dcache.ReadReq_misses::cpu.data 684 +system.cpu.dcache.ReadReq_misses::total 684 +system.cpu.dcache.WriteReq_misses::cpu.data 1139 +system.cpu.dcache.WriteReq_misses::total 1139 +system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 +system.cpu.dcache.LoadLockedReq_misses::total 4 +system.cpu.dcache.demand_misses::cpu.data 1823 +system.cpu.dcache.demand_misses::total 1823 +system.cpu.dcache.overall_misses::cpu.data 1823 +system.cpu.dcache.overall_misses::total 1823 +system.cpu.dcache.ReadReq_miss_latency::cpu.data 56772000 +system.cpu.dcache.ReadReq_miss_latency::total 56772000 +system.cpu.dcache.WriteReq_miss_latency::cpu.data 80150460 +system.cpu.dcache.WriteReq_miss_latency::total 80150460 +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 341500 +system.cpu.dcache.LoadLockedReq_miss_latency::total 341500 +system.cpu.dcache.demand_miss_latency::cpu.data 136922460 +system.cpu.dcache.demand_miss_latency::total 136922460 +system.cpu.dcache.overall_miss_latency::cpu.data 136922460 +system.cpu.dcache.overall_miss_latency::total 136922460 +system.cpu.dcache.ReadReq_accesses::cpu.data 111637 +system.cpu.dcache.ReadReq_accesses::total 111637 +system.cpu.dcache.WriteReq_accesses::cpu.data 62435 +system.cpu.dcache.WriteReq_accesses::total 62435 +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1698 +system.cpu.dcache.LoadLockedReq_accesses::total 1698 +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1691 +system.cpu.dcache.StoreCondReq_accesses::total 1691 +system.cpu.dcache.demand_accesses::cpu.data 174072 +system.cpu.dcache.demand_accesses::total 174072 +system.cpu.dcache.overall_accesses::cpu.data 174072 +system.cpu.dcache.overall_accesses::total 174072 +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006127 +system.cpu.dcache.ReadReq_miss_rate::total 0.006127 +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018242 +system.cpu.dcache.WriteReq_miss_rate::total 0.018242 +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002355 +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002355 +system.cpu.dcache.demand_miss_rate::cpu.data 0.010472 +system.cpu.dcache.demand_miss_rate::total 0.010472 +system.cpu.dcache.overall_miss_rate::cpu.data 0.010472 +system.cpu.dcache.overall_miss_rate::total 0.010472 +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 83000 +system.cpu.dcache.ReadReq_avg_miss_latency::total 83000 +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70369.148375 +system.cpu.dcache.WriteReq_avg_miss_latency::total 70369.148375 +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85375 +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85375 +system.cpu.dcache.demand_avg_miss_latency::cpu.data 75108.315962 +system.cpu.dcache.demand_avg_miss_latency::total 75108.315962 +system.cpu.dcache.overall_avg_miss_latency::cpu.data 75108.315962 +system.cpu.dcache.overall_avg_miss_latency::total 75108.315962 +system.cpu.dcache.blocked_cycles::no_mshrs 3337 +system.cpu.dcache.blocked_cycles::no_targets 77 +system.cpu.dcache.blocked::no_mshrs 63 +system.cpu.dcache.blocked::no_targets 1 +system.cpu.dcache.avg_blocked_cycles::no_mshrs 52.968253 +system.cpu.dcache.avg_blocked_cycles::no_targets 77 +system.cpu.dcache.writebacks::writebacks 2 +system.cpu.dcache.writebacks::total 2 +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 366 +system.cpu.dcache.ReadReq_mshr_hits::total 366 +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 920 +system.cpu.dcache.WriteReq_mshr_hits::total 920 +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 +system.cpu.dcache.demand_mshr_hits::cpu.data 1286 +system.cpu.dcache.demand_mshr_hits::total 1286 +system.cpu.dcache.overall_mshr_hits::cpu.data 1286 +system.cpu.dcache.overall_mshr_hits::total 1286 +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 318 +system.cpu.dcache.ReadReq_mshr_misses::total 318 +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 219 +system.cpu.dcache.WriteReq_mshr_misses::total 219 +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 2 +system.cpu.dcache.LoadLockedReq_mshr_misses::total 2 +system.cpu.dcache.demand_mshr_misses::cpu.data 537 +system.cpu.dcache.demand_mshr_misses::total 537 +system.cpu.dcache.overall_mshr_misses::cpu.data 537 +system.cpu.dcache.overall_mshr_misses::total 537 +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28870000 +system.cpu.dcache.ReadReq_mshr_miss_latency::total 28870000 +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19445998 +system.cpu.dcache.WriteReq_mshr_miss_latency::total 19445998 +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 183000 +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 183000 +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 48315998 +system.cpu.dcache.demand_mshr_miss_latency::total 48315998 +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48315998 +system.cpu.dcache.overall_mshr_miss_latency::total 48315998 +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002848 +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003507 +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003507 +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.001177 +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.001177 +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003084 +system.cpu.dcache.demand_mshr_miss_rate::total 0.003084 +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003084 +system.cpu.dcache.overall_mshr_miss_rate::total 0.003084 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 90786.163522 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 90786.163522 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 88794.511415 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88794.511415 +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 91500 +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 91500 +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89973.925512 +system.cpu.dcache.demand_avg_mshr_miss_latency::total 89973.925512 +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89973.925512 +system.cpu.dcache.overall_avg_mshr_miss_latency::total 89973.925512 +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 334241000 +system.cpu.icache.tags.replacements 100 +system.cpu.icache.tags.tagsinuse 795.681127 +system.cpu.icache.tags.total_refs 88646 +system.cpu.icache.tags.sampled_refs 1259 +system.cpu.icache.tags.avg_refs 70.409849 +system.cpu.icache.tags.warmup_cycle 0 +system.cpu.icache.tags.occ_blocks::cpu.inst 795.681127 +system.cpu.icache.tags.occ_percent::cpu.inst 0.388516 +system.cpu.icache.tags.occ_percent::total 0.388516 +system.cpu.icache.tags.occ_task_id_blocks::1024 1159 +system.cpu.icache.tags.age_task_id_blocks_1024::0 57 +system.cpu.icache.tags.age_task_id_blocks_1024::1 144 +system.cpu.icache.tags.age_task_id_blocks_1024::2 958 +system.cpu.icache.tags.occ_task_id_percent::1024 0.565917 +system.cpu.icache.tags.tag_accesses 181867 +system.cpu.icache.tags.data_accesses 181867 +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 334241000 +system.cpu.icache.ReadReq_hits::cpu.inst 88646 +system.cpu.icache.ReadReq_hits::total 88646 +system.cpu.icache.demand_hits::cpu.inst 88646 +system.cpu.icache.demand_hits::total 88646 +system.cpu.icache.overall_hits::cpu.inst 88646 +system.cpu.icache.overall_hits::total 88646 +system.cpu.icache.ReadReq_misses::cpu.inst 1658 +system.cpu.icache.ReadReq_misses::total 1658 +system.cpu.icache.demand_misses::cpu.inst 1658 +system.cpu.icache.demand_misses::total 1658 +system.cpu.icache.overall_misses::cpu.inst 1658 +system.cpu.icache.overall_misses::total 1658 +system.cpu.icache.ReadReq_miss_latency::cpu.inst 135810998 +system.cpu.icache.ReadReq_miss_latency::total 135810998 +system.cpu.icache.demand_miss_latency::cpu.inst 135810998 +system.cpu.icache.demand_miss_latency::total 135810998 +system.cpu.icache.overall_miss_latency::cpu.inst 135810998 +system.cpu.icache.overall_miss_latency::total 135810998 +system.cpu.icache.ReadReq_accesses::cpu.inst 90304 +system.cpu.icache.ReadReq_accesses::total 90304 +system.cpu.icache.demand_accesses::cpu.inst 90304 +system.cpu.icache.demand_accesses::total 90304 +system.cpu.icache.overall_accesses::cpu.inst 90304 +system.cpu.icache.overall_accesses::total 90304 +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.018360 +system.cpu.icache.ReadReq_miss_rate::total 0.018360 +system.cpu.icache.demand_miss_rate::cpu.inst 0.018360 +system.cpu.icache.demand_miss_rate::total 0.018360 +system.cpu.icache.overall_miss_rate::cpu.inst 0.018360 +system.cpu.icache.overall_miss_rate::total 0.018360 +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81912.544028 +system.cpu.icache.ReadReq_avg_miss_latency::total 81912.544028 +system.cpu.icache.demand_avg_miss_latency::cpu.inst 81912.544028 +system.cpu.icache.demand_avg_miss_latency::total 81912.544028 +system.cpu.icache.overall_avg_miss_latency::cpu.inst 81912.544028 +system.cpu.icache.overall_avg_miss_latency::total 81912.544028 +system.cpu.icache.blocked_cycles::no_mshrs 1180 +system.cpu.icache.blocked_cycles::no_targets 0 +system.cpu.icache.blocked::no_mshrs 17 +system.cpu.icache.blocked::no_targets 0 +system.cpu.icache.avg_blocked_cycles::no_mshrs 69.411764 +system.cpu.icache.avg_blocked_cycles::no_targets nan +system.cpu.icache.writebacks::writebacks 100 +system.cpu.icache.writebacks::total 100 +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 399 +system.cpu.icache.ReadReq_mshr_hits::total 399 +system.cpu.icache.demand_mshr_hits::cpu.inst 399 +system.cpu.icache.demand_mshr_hits::total 399 +system.cpu.icache.overall_mshr_hits::cpu.inst 399 +system.cpu.icache.overall_mshr_hits::total 399 +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1259 +system.cpu.icache.ReadReq_mshr_misses::total 1259 +system.cpu.icache.demand_mshr_misses::cpu.inst 1259 +system.cpu.icache.demand_mshr_misses::total 1259 +system.cpu.icache.overall_mshr_misses::cpu.inst 1259 +system.cpu.icache.overall_mshr_misses::total 1259 +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 107535499 +system.cpu.icache.ReadReq_mshr_miss_latency::total 107535499 +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 107535499 +system.cpu.icache.demand_mshr_miss_latency::total 107535499 +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 107535499 +system.cpu.icache.overall_mshr_miss_latency::total 107535499 +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013941 +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013941 +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013941 +system.cpu.icache.demand_mshr_miss_rate::total 0.013941 +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013941 +system.cpu.icache.overall_mshr_miss_rate::total 0.013941 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 85413.422557 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 85413.422557 +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 85413.422557 +system.cpu.icache.demand_avg_mshr_miss_latency::total 85413.422557 +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 85413.422557 +system.cpu.icache.overall_avg_mshr_miss_latency::total 85413.422557 +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 334241000 +system.cpu.l2cache.tags.replacements 0 +system.cpu.l2cache.tags.tagsinuse 1270.385229 +system.cpu.l2cache.tags.total_refs 117 +system.cpu.l2cache.tags.sampled_refs 1782 +system.cpu.l2cache.tags.avg_refs 0.065656 +system.cpu.l2cache.tags.warmup_cycle 0 +system.cpu.l2cache.tags.occ_blocks::cpu.inst 839.405439 +system.cpu.l2cache.tags.occ_blocks::cpu.data 430.979790 +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.025616 +system.cpu.l2cache.tags.occ_percent::cpu.data 0.013152 +system.cpu.l2cache.tags.occ_percent::total 0.038769 +system.cpu.l2cache.tags.occ_task_id_blocks::1024 1782 +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 69 +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 169 +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1544 +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.054382 +system.cpu.l2cache.tags.tag_accesses 16974 +system.cpu.l2cache.tags.data_accesses 16974 +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 334241000 +system.cpu.l2cache.WritebackDirty_hits::writebacks 2 +system.cpu.l2cache.WritebackDirty_hits::total 2 +system.cpu.l2cache.WritebackClean_hits::writebacks 99 +system.cpu.l2cache.WritebackClean_hits::total 99 +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 15 +system.cpu.l2cache.ReadCleanReq_hits::total 15 +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 +system.cpu.l2cache.ReadSharedReq_hits::total 1 +system.cpu.l2cache.demand_hits::cpu.inst 15 +system.cpu.l2cache.demand_hits::cpu.data 1 +system.cpu.l2cache.demand_hits::total 16 +system.cpu.l2cache.overall_hits::cpu.inst 15 +system.cpu.l2cache.overall_hits::cpu.data 1 +system.cpu.l2cache.overall_hits::total 16 +system.cpu.l2cache.ReadExReq_misses::cpu.data 219 +system.cpu.l2cache.ReadExReq_misses::total 219 +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1244 +system.cpu.l2cache.ReadCleanReq_misses::total 1244 +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 319 +system.cpu.l2cache.ReadSharedReq_misses::total 319 +system.cpu.l2cache.demand_misses::cpu.inst 1244 +system.cpu.l2cache.demand_misses::cpu.data 538 +system.cpu.l2cache.demand_misses::total 1782 +system.cpu.l2cache.overall_misses::cpu.inst 1244 +system.cpu.l2cache.overall_misses::cpu.data 538 +system.cpu.l2cache.overall_misses::total 1782 +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 19111500 +system.cpu.l2cache.ReadExReq_miss_latency::total 19111500 +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 105481500 +system.cpu.l2cache.ReadCleanReq_miss_latency::total 105481500 +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 28555500 +system.cpu.l2cache.ReadSharedReq_miss_latency::total 28555500 +system.cpu.l2cache.demand_miss_latency::cpu.inst 105481500 +system.cpu.l2cache.demand_miss_latency::cpu.data 47667000 +system.cpu.l2cache.demand_miss_latency::total 153148500 +system.cpu.l2cache.overall_miss_latency::cpu.inst 105481500 +system.cpu.l2cache.overall_miss_latency::cpu.data 47667000 +system.cpu.l2cache.overall_miss_latency::total 153148500 +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2 +system.cpu.l2cache.WritebackDirty_accesses::total 2 +system.cpu.l2cache.WritebackClean_accesses::writebacks 99 +system.cpu.l2cache.WritebackClean_accesses::total 99 +system.cpu.l2cache.ReadExReq_accesses::cpu.data 219 +system.cpu.l2cache.ReadExReq_accesses::total 219 +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1259 +system.cpu.l2cache.ReadCleanReq_accesses::total 1259 +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 320 +system.cpu.l2cache.ReadSharedReq_accesses::total 320 +system.cpu.l2cache.demand_accesses::cpu.inst 1259 +system.cpu.l2cache.demand_accesses::cpu.data 539 +system.cpu.l2cache.demand_accesses::total 1798 +system.cpu.l2cache.overall_accesses::cpu.inst 1259 +system.cpu.l2cache.overall_accesses::cpu.data 539 +system.cpu.l2cache.overall_accesses::total 1798 +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 +system.cpu.l2cache.ReadExReq_miss_rate::total 1 +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.988085 +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.988085 +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.996874 +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.996874 +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.988085 +system.cpu.l2cache.demand_miss_rate::cpu.data 0.998144 +system.cpu.l2cache.demand_miss_rate::total 0.991101 +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.988085 +system.cpu.l2cache.overall_miss_rate::cpu.data 0.998144 +system.cpu.l2cache.overall_miss_rate::total 0.991101 +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87267.123287 +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87267.123287 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84792.202572 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84792.202572 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89515.673981 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89515.673981 +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84792.202572 +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88600.371747 +system.cpu.l2cache.demand_avg_miss_latency::total 85941.919191 +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84792.202572 +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88600.371747 +system.cpu.l2cache.overall_avg_miss_latency::total 85941.919191 +system.cpu.l2cache.blocked_cycles::no_mshrs 0 +system.cpu.l2cache.blocked_cycles::no_targets 0 +system.cpu.l2cache.blocked::no_mshrs 0 +system.cpu.l2cache.blocked::no_targets 0 +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan +system.cpu.l2cache.avg_blocked_cycles::no_targets nan +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 219 +system.cpu.l2cache.ReadExReq_mshr_misses::total 219 +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1244 +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1244 +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 319 +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 319 +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1244 +system.cpu.l2cache.demand_mshr_misses::cpu.data 538 +system.cpu.l2cache.demand_mshr_misses::total 1782 +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1244 +system.cpu.l2cache.overall_mshr_misses::cpu.data 538 +system.cpu.l2cache.overall_mshr_misses::total 1782 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16921500 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16921500 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 93041500 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 93041500 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 25365500 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 25365500 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 93041500 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 42287000 +system.cpu.l2cache.demand_mshr_miss_latency::total 135328500 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 93041500 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 42287000 +system.cpu.l2cache.overall_mshr_miss_latency::total 135328500 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.988085 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.988085 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.996874 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.996874 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.988085 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.998144 +system.cpu.l2cache.demand_mshr_miss_rate::total 0.991101 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.988085 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.998144 +system.cpu.l2cache.overall_mshr_miss_rate::total 0.991101 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77267.123287 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77267.123287 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74792.202572 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74792.202572 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79515.673981 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79515.673981 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74792.202572 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78600.371747 +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75941.919191 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74792.202572 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78600.371747 +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75941.919191 +system.cpu.toL2Bus.snoop_filter.tot_requests 1900 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 105 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 334241000 +system.cpu.toL2Bus.trans_dist::ReadResp 1579 +system.cpu.toL2Bus.trans_dist::WritebackDirty 2 +system.cpu.toL2Bus.trans_dist::WritebackClean 100 +system.cpu.toL2Bus.trans_dist::ReadExReq 219 +system.cpu.toL2Bus.trans_dist::ReadExResp 219 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1259 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 320 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2618 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1080 +system.cpu.toL2Bus.pkt_count::total 3698 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86976 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 34624 +system.cpu.toL2Bus.pkt_size::total 121600 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 1798 +system.cpu.toL2Bus.snoop_fanout::mean 0.002224 +system.cpu.toL2Bus.snoop_fanout::stdev 0.047127 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 1794 99.77% 99.77% +system.cpu.toL2Bus.snoop_fanout::1 4 0.22% 99.99% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 99.99% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 99.99% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 1798 +system.cpu.toL2Bus.reqLayer0.occupancy 1052000 +system.cpu.toL2Bus.reqLayer0.utilization 0.3 +system.cpu.toL2Bus.respLayer0.occupancy 1888500 +system.cpu.toL2Bus.respLayer0.utilization 0.5 +system.cpu.toL2Bus.respLayer1.occupancy 808500 +system.cpu.toL2Bus.respLayer1.utilization 0.2 +system.membus.snoop_filter.tot_requests 1782 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 334241000 +system.membus.trans_dist::ReadResp 1563 +system.membus.trans_dist::ReadExReq 219 +system.membus.trans_dist::ReadExResp 219 +system.membus.trans_dist::ReadSharedReq 1563 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3564 +system.membus.pkt_count::total 3564 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 114048 +system.membus.pkt_size::total 114048 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 1782 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev -0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 1782 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 1782 +system.membus.reqLayer0.occupancy 2193000 +system.membus.reqLayer0.utilization 0.6 +system.membus.respLayer1.occupancy 9460500 +system.membus.respLayer1.utilization 2.8 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/config.ini index 50ff7280f..3bd760d52 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/config.ini +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/config.ini @@ -88,8 +88,10 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer +wait_for_remote_gdb=false width=1 workload=system.cpu.workload dcache_port=system.membus.slave[2] @@ -118,7 +120,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=insttest cwd= drivers= @@ -127,14 +129,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64f/insttest gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/config.json index ecd3e1c52..8a3f65b56 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/config.json +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/config.json @@ -192,6 +192,7 @@ }, "p_state_clk_gate_bins": 20, "p_state_clk_gate_min": 1000, + "syscallRetryLatency": 10000, "interrupts": [ { "eventq_index": 0, @@ -216,21 +217,22 @@ "uid": 100, "pid": 100, "kvmInSE": false, - "cxx_class": "LiveProcess", - "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest", + "cxx_class": "Process", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64f/insttest", "drivers": [], "system": "system", "gid": 100, "eventq_index": 0, "env": [], - "input": "cin", - "ppid": 99, - "type": "LiveProcess", + "maxStackSize": 67108864, + "ppid": 0, + "type": "Process", "cwd": "", + "pgid": 100, "simpoint": 0, "euid": 100, + "input": "cin", "path": "system.cpu.workload", - "max_stack_size": 67108864, "name": "workload", "cmd": [ "insttest" @@ -242,6 +244,7 @@ } ], "name": "cpu", + "wait_for_remote_gdb": false, "dtb": { "name": "dtb", "eventq_index": 0, diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/simerr index fd133b12b..eaef272b7 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/simerr +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/simerr @@ -1,3 +1,5 @@ -warn: Unknown operating system; assuming Linux. warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings. + Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest' +info: Increasing stack size by one page. diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/simout index 1aedc7412..bbbf6fc92 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/simout +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/simout @@ -3,14 +3,12 @@ Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv6 gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 30 2016 14:33:35 -gem5 started Nov 30 2016 16:18:33 -gem5 executing on zizzer, pid 34079 -command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-atomic -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/simple-atomic +gem5 compiled Jul 13 2017 17:09:45 +gem5 started Jul 13 2017 17:11:10 +gem5 executing on boldrock, pid 1746 +command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. clear fsflags: PASS flw: PASS fsw: PASS @@ -118,4 +116,105 @@ fcvt.w.s, truncate negative: PASS fcvt.w.s, 0.0: PASS fcvt.w.s, -0.0: PASS fcvt.w.s, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) -Exiting @ tick 113137000 because target called exit() +fcvt.w.s, underflow: PASS +fcvt.w.s, infinity: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +fcvt.w.s, -infinity: PASS +fcvt.w.s, quiet NaN: PASS +fcvt.w.s, quiet -NaN: PASS +fcvt.w.s, signaling NaN: PASS +fcvt.wu.s, truncate positive: PASS +fcvt.wu.s, truncate negative: PASS +fcvt.wu.s, 0.0: PASS +fcvt.wu.s, -0.0: PASS +fcvt.wu.s, overflow: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.s, underflow: PASS +fcvt.wu.s, infinity: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.s, -infinity: PASS +fcvt.wu.s, quiet NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.s, quiet -NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.s, signaling NaN: PASS +fmv.x.s, positive: PASS +fmv.x.s, negative: PASS +fmv.x.s, 0.0: PASS +fmv.x.s, -0.0: PASS +feq.s, equal: PASS +feq.s, not equal: PASS +feq.s, 0 == -0: PASS +feq.s, quiet NaN first: PASS +feq.s, quiet NaN second: PASS +feq.s, quiet NaN both: PASS +feq.s, signaling NaN first: PASS +feq.s, signaling NaN second: PASS +feq.s, signaling NaN both: PASS +flt.s, equal: PASS +flt.s, less: PASS +flt.s, greater: PASS +flt.s, quiet NaN first: PASS +flt.s, quiet NaN second: PASS +flt.s, quiet NaN both: PASS +flt.s, signaling NaN first: PASS +flt.s, signaling NaN second: PASS +flt.s, signaling NaN both: PASS +fle.s, equal: PASS +fle.s, less: PASS +fle.s, greater: PASS +fle.s, 0 == -0: PASS +fle.s, quiet NaN first: PASS +fle.s, quiet NaN second: PASS +fle.s, quiet NaN both: PASS +fle.s, signaling NaN first: PASS +fle.s, signaling NaN second: PASS +fle.s, signaling NaN both: PASS +fclass.s, -infinity: PASS +fclass.s, -normal: PASS +fclass.s, -subnormal: PASS +fclass.s, -0.0: PASS +fclass.s, 0.0: PASS +fclass.s, subnormal: PASS +fclass.s, normal: PASS +fclass.s, infinity: PASS +fclass.s, signaling NaN: PASS +fclass.s, quiet NaN: PASS +fcvt.s.w, 0: PASS +fcvt.s.w, negative: PASS +fcvt.s.w, truncate: PASS +fcvt.s.wu, 0: PASS +fcvt.s.wu: PASS +fcvt.s.wu, truncate: PASS +fmv.s.x: PASS +fmv.s.x, truncate: PASS +fsrm: PASS +fsflags: PASS +fscsr: PASS +restore initial round mode: PASS +fcvt.l.s, truncate positive: PASS +fcvt.l.s, truncate negative: PASS +fcvt.l.s, 0.0: PASS +fcvt.l.s, -0.0: PASS +fcvt.l.s, 32-bit overflow: PASS +fcvt.l.s, overflow: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.l.s, underflow: PASS +fcvt.l.s, infinity: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.l.s, -infinity: PASS +fcvt.l.s, quiet NaN: PASS +fcvt.l.s, quiet -NaN: PASS +fcvt.l.s, signaling NaN: PASS +fcvt.lu.s, truncate positive: PASS +fcvt.lu.s, truncate negative: PASS +fcvt.lu.s, 0.0: PASS +fcvt.lu.s, -0.0: PASS +fcvt.lu.s, 32-bit overflow: PASS +fcvt.lu.s, overflow: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.lu.s, underflow: PASS +fcvt.lu.s, infinity: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.lu.s, -infinity: PASS +fcvt.lu.s, quiet NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 9223372036854775808) +fcvt.lu.s, quiet -NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 9223372036854775808) +fcvt.lu.s, signaling NaN: PASS +fcvt.s.l, 0: PASS +fcvt.s.l, negative: PASS +fcvt.s.l, 32-bit truncate: PASS +fcvt.s.lu, 0: PASS +fcvt.s.lu: PASS +fcvt.s.lu, 32-bit truncate: PASS +Exiting @ tick 244411500 because exiting with last active thread context diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/stats.txt index eab32259e..9fef2892d 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/stats.txt @@ -1,153 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000113 # Number of seconds simulated -sim_ticks 113137000 # Number of ticks simulated -final_tick 113137000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 28615 # Simulator instruction rate (inst/s) -host_op_rate 28615 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14314809 # Simulator tick rate (ticks/s) -host_mem_usage 234404 # Number of bytes of host memory used -host_seconds 7.90 # Real time elapsed on the host -sim_insts 226159 # Number of instructions simulated -sim_ops 226159 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 113137000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 905100 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 339455 # Number of bytes read from this memory -system.physmem.bytes_read::total 1244555 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 905100 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 905100 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 226262 # Number of bytes written to this memory -system.physmem.bytes_written::total 226262 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 226275 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 51711 # Number of read requests responded to by this memory -system.physmem.num_reads::total 277986 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 37229 # Number of write requests responded to by this memory -system.physmem.num_writes::total 37229 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 8000035355 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3000388909 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11000424264 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8000035355 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8000035355 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1999893934 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1999893934 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8000035355 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5000282843 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13000318198 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 113137000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 115 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 113137000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 226275 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 226159 # Number of instructions committed -system.cpu.committedOps 226159 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 225992 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 862 # Number of float alu accesses -system.cpu.num_func_calls 16616 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 33789 # number of instructions that are conditional controls -system.cpu.num_int_insts 225992 # number of integer instructions -system.cpu.num_fp_insts 862 # number of float instructions -system.cpu.num_int_register_reads 298589 # number of times the integer registers were read -system.cpu.num_int_register_writes 154866 # number of times the integer registers were written -system.cpu.num_fp_register_reads 733 # number of times the floating registers were read -system.cpu.num_fp_register_writes 588 # number of times the floating registers were written -system.cpu.num_mem_refs 88941 # number of memory refs -system.cpu.num_load_insts 51711 # Number of load instructions -system.cpu.num_store_insts 37230 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 226275 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 50405 # Number of branches fetched -system.cpu.op_class::No_OpClass 117 0.05% 0.05% # Class of executed instruction -system.cpu.op_class::IntAlu 136540 60.34% 60.39% # Class of executed instruction -system.cpu.op_class::IntMult 325 0.14% 60.54% # Class of executed instruction -system.cpu.op_class::IntDiv 40 0.02% 60.56% # Class of executed instruction -system.cpu.op_class::FloatAdd 104 0.05% 60.60% # Class of executed instruction -system.cpu.op_class::FloatCmp 119 0.05% 60.65% # Class of executed instruction -system.cpu.op_class::FloatCvt 43 0.02% 60.67% # Class of executed instruction -system.cpu.op_class::FloatMult 30 0.01% 60.69% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::FloatDiv 11 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::FloatSqrt 5 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::MemRead 51297 22.67% 83.36% # Class of executed instruction -system.cpu.op_class::MemWrite 37094 16.39% 99.76% # Class of executed instruction -system.cpu.op_class::FloatMemRead 414 0.18% 99.94% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 136 0.06% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 226275 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 113137000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 277986 # Transaction distribution -system.membus.trans_dist::ReadResp 277986 # Transaction distribution -system.membus.trans_dist::WriteReq 37229 # Transaction distribution -system.membus.trans_dist::WriteResp 37229 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 452550 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 177880 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 630430 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 905100 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 565717 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1470817 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 315215 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 315215 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 315215 # Request fanout histogram +sim_seconds 0.000244 +sim_ticks 244411500 +final_tick 244411500 +sim_freq 1000000000000 +host_inst_rate 4072 +host_op_rate 4084 +host_tick_rate 2392518 +host_mem_usage 259288 +host_seconds 102.15 +sim_insts 416024 +sim_ops 417277 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 244411500 +system.physmem.bytes_read::cpu.inst 1950284 +system.physmem.bytes_read::cpu.data 696743 +system.physmem.bytes_read::total 2647027 +system.physmem.bytes_inst_read::cpu.inst 1950284 +system.physmem.bytes_inst_read::total 1950284 +system.physmem.bytes_written::cpu.data 440589 +system.physmem.bytes_written::total 440589 +system.physmem.num_reads::cpu.inst 487571 +system.physmem.num_reads::cpu.data 105498 +system.physmem.num_reads::total 593069 +system.physmem.num_writes::cpu.data 64126 +system.physmem.num_writes::total 64126 +system.physmem.bw_read::cpu.inst 7979509965 +system.physmem.bw_read::cpu.data 2850696468 +system.physmem.bw_read::total 10830206434 +system.physmem.bw_inst_read::cpu.inst 7979509965 +system.physmem.bw_inst_read::total 7979509965 +system.physmem.bw_write::cpu.data 1802652493 +system.physmem.bw_write::total 1802652493 +system.physmem.bw_total::cpu.inst 7979509965 +system.physmem.bw_total::cpu.data 4653348962 +system.physmem.bw_total::total 12632858928 +system.pwrStateResidencyTicks::UNDEFINED 244411500 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 216 +system.cpu.pwrStateResidencyTicks::ON 244411500 +system.cpu.numCycles 488824 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 416024 +system.cpu.committedOps 417277 +system.cpu.num_int_alu_accesses 415220 +system.cpu.num_fp_alu_accesses 1163 +system.cpu.num_vec_alu_accesses 0 +system.cpu.num_func_calls 23050 +system.cpu.num_conditional_control_insts 67806 +system.cpu.num_int_insts 415220 +system.cpu.num_fp_insts 1163 +system.cpu.num_vec_insts 0 +system.cpu.num_int_register_reads 525251 +system.cpu.num_int_register_writes 276296 +system.cpu.num_fp_register_reads 936 +system.cpu.num_fp_register_writes 756 +system.cpu.num_vec_register_reads 0 +system.cpu.num_vec_register_writes 0 +system.cpu.num_mem_refs 169624 +system.cpu.num_load_insts 105498 +system.cpu.num_store_insts 64126 +system.cpu.num_idle_cycles -0 +system.cpu.num_busy_cycles 488824 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction -0 +system.cpu.Branches 90856 +system.cpu.op_class::No_OpClass 236 0.05% 0.05% +system.cpu.op_class::IntAlu 245871 58.89% 58.94% +system.cpu.op_class::IntMult 674 0.16% 59.11% +system.cpu.op_class::IntDiv 644 0.15% 59.26% +system.cpu.op_class::FloatAdd 128 0.03% 59.29% +system.cpu.op_class::FloatCmp 161 0.03% 59.33% +system.cpu.op_class::FloatCvt 109 0.02% 59.35% +system.cpu.op_class::FloatMult 30 0.00% 59.36% +system.cpu.op_class::FloatMultAcc 0 0.00% 59.36% +system.cpu.op_class::FloatDiv 11 0.00% 59.36% +system.cpu.op_class::FloatMisc 0 0.00% 59.36% +system.cpu.op_class::FloatSqrt 5 0.00% 59.37% +system.cpu.op_class::SimdAdd 0 0.00% 59.37% +system.cpu.op_class::SimdAddAcc 0 0.00% 59.37% +system.cpu.op_class::SimdAlu 0 0.00% 59.37% +system.cpu.op_class::SimdCmp 0 0.00% 59.37% +system.cpu.op_class::SimdCvt 0 0.00% 59.37% +system.cpu.op_class::SimdMisc 0 0.00% 59.37% +system.cpu.op_class::SimdMult 0 0.00% 59.37% +system.cpu.op_class::SimdMultAcc 0 0.00% 59.37% +system.cpu.op_class::SimdShift 0 0.00% 59.37% +system.cpu.op_class::SimdShiftAcc 0 0.00% 59.37% +system.cpu.op_class::SimdSqrt 0 0.00% 59.37% +system.cpu.op_class::SimdFloatAdd 0 0.00% 59.37% +system.cpu.op_class::SimdFloatAlu 0 0.00% 59.37% +system.cpu.op_class::SimdFloatCmp 0 0.00% 59.37% +system.cpu.op_class::SimdFloatCvt 0 0.00% 59.37% +system.cpu.op_class::SimdFloatDiv 0 0.00% 59.37% +system.cpu.op_class::SimdFloatMisc 0 0.00% 59.37% +system.cpu.op_class::SimdFloatMult 0 0.00% 59.37% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 59.37% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 59.37% +system.cpu.op_class::MemRead 104951 25.13% 84.50% +system.cpu.op_class::MemWrite 63954 15.31% 99.82% +system.cpu.op_class::FloatMemRead 547 0.13% 99.95% +system.cpu.op_class::FloatMemWrite 172 0.04% 99.99% +system.cpu.op_class::IprAccess 0 0.00% 99.99% +system.cpu.op_class::InstPrefetch 0 0.00% 99.99% +system.cpu.op_class::total 417493 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 244411500 +system.membus.trans_dist::ReadReq 591378 +system.membus.trans_dist::ReadResp 593069 +system.membus.trans_dist::WriteReq 62435 +system.membus.trans_dist::WriteResp 62435 +system.membus.trans_dist::LoadLockedReq 1691 +system.membus.trans_dist::StoreCondReq 1691 +system.membus.trans_dist::StoreCondResp 1691 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 975142 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 339248 +system.membus.pkt_count::total 1314390 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1950284 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1137332 +system.membus.pkt_size::total 3087616 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 657195 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev -0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 657195 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 657195 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/config.ini index eb91af64f..3114d8fbe 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/config.ini +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/config.ini @@ -85,8 +85,10 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer +wait_for_remote_gdb=false workload=system.cpu.workload dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] @@ -122,7 +124,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=insttest cwd= drivers= @@ -131,14 +133,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64f/insttest gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -266,6 +269,7 @@ voltage_domain=system.voltage_domain [system.ruby.dir_cntrl0] type=Directory_Controller children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory +addr_ranges=0:268435455:5:0:0:0 buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 @@ -288,16 +292,14 @@ responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory ruby_system=system.ruby system=system to_memory_controller_latency=1 -transitions_per_cycle=4 +transitions_per_cycle=32 version=0 memory=system.mem_ctrls.port [system.ruby.dir_cntrl0.directory] type=RubyDirectoryMemory +addr_ranges=0:268435455:5:0:0:0 eventq_index=0 -numa_high_bit=5 -size=268435456 -version=0 [system.ruby.dir_cntrl0.dmaRequestToDir] type=MessageBuffer @@ -349,6 +351,7 @@ randomization=false [system.ruby.l1_cntrl0] type=L1Cache_Controller children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer +addr_ranges=0:18446744073709551615:0:0:0:0 buffer_size=0 cacheMemory=system.ruby.l1_cntrl0.cacheMemory cache_response_latency=12 diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/config.json index 10ddc0f69..54c018454 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/config.json +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/config.json @@ -115,7 +115,6 @@ "path": "system.ruby.l1_cntrl0.requestFromCache", "type": "MessageBuffer" }, - "cxx_class": "L1Cache_Controller", "forwardToCache": { "ordered": true, "name": "forwardToCache", @@ -168,8 +167,9 @@ "support_data_reqs": true, "is_cpu_sequencer": true }, - "type": "L1Cache_Controller", + "cxx_class": "L1Cache_Controller", "issue_latency": 2, + "type": "L1Cache_Controller", "recycle_latency": 10, "clk_domain": "system.cpu.clk_domain", "version": 0, @@ -241,6 +241,9 @@ }, "ruby_system": "system.ruby", "name": "l1_cntrl0", + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], "p_state_clk_gate_bins": 20, "mandatoryQueue": { "ordered": false, @@ -1447,12 +1450,15 @@ "path": "system.ruby.dir_cntrl0.responseFromDir", "type": "MessageBuffer" }, - "transitions_per_cycle": 4, + "transitions_per_cycle": 32, "memory": { "peer": "system.mem_ctrls.port", "role": "MASTER" }, "power_model": null, + "addr_ranges": [ + "0:268435455:5:0:0:0" + ], "buffer_size": 0, "ruby_system": "system.ruby", "requestToDir": { @@ -1487,13 +1493,13 @@ "p_state_clk_gate_bins": 20, "directory": { "name": "directory", - "version": 0, + "addr_ranges": [ + "0:268435455:5:0:0:0" + ], "eventq_index": 0, "cxx_class": "DirectoryMemory", "path": "system.ruby.dir_cntrl0.directory", - "type": "RubyDirectoryMemory", - "numa_high_bit": 5, - "size": 268435456 + "type": "RubyDirectoryMemory" }, "path": "system.ruby.dir_cntrl0" } @@ -1548,6 +1554,7 @@ }, "p_state_clk_gate_bins": 20, "p_state_clk_gate_min": 1, + "syscallRetryLatency": 10000, "interrupts": [ { "eventq_index": 0, @@ -1572,21 +1579,22 @@ "uid": 100, "pid": 100, "kvmInSE": false, - "cxx_class": "LiveProcess", - "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest", + "cxx_class": "Process", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64f/insttest", "drivers": [], "system": "system", "gid": 100, "eventq_index": 0, "env": [], - "input": "cin", - "ppid": 99, - "type": "LiveProcess", + "maxStackSize": 67108864, + "ppid": 0, + "type": "Process", "cwd": "", + "pgid": 100, "simpoint": 0, "euid": 100, + "input": "cin", "path": "system.cpu.workload", - "max_stack_size": 67108864, "name": "workload", "cmd": [ "insttest" @@ -1598,6 +1606,7 @@ } ], "name": "cpu", + "wait_for_remote_gdb": false, "dtb": { "name": "dtb", "eventq_index": 0, diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/simerr index 63b14556f..9ef353764 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/simerr +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/simerr @@ -4,8 +4,12 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) -warn: Unknown operating system; assuming Linux. warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! +warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings. + Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest' +info: Increasing stack size by one page. diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/simout index 5fb7ec2e1..437078d7e 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/simout +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/simout @@ -3,14 +3,12 @@ Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv6 gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 30 2016 14:33:35 -gem5 started Nov 30 2016 16:18:42 -gem5 executing on zizzer, pid 34083 -command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/simple-timing-ruby +gem5 compiled Jul 13 2017 17:09:45 +gem5 started Jul 13 2017 17:11:34 +gem5 executing on boldrock, pid 1867 +command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing-ruby --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/simple-timing-ruby Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. clear fsflags: PASS flw: PASS fsw: PASS @@ -118,4 +116,105 @@ fcvt.w.s, truncate negative: PASS fcvt.w.s, 0.0: PASS fcvt.w.s, -0.0: PASS fcvt.w.s, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) -Exiting @ tick 4665394 because target called exit() +fcvt.w.s, underflow: PASS +fcvt.w.s, infinity: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +fcvt.w.s, -infinity: PASS +fcvt.w.s, quiet NaN: PASS +fcvt.w.s, quiet -NaN: PASS +fcvt.w.s, signaling NaN: PASS +fcvt.wu.s, truncate positive: PASS +fcvt.wu.s, truncate negative: PASS +fcvt.wu.s, 0.0: PASS +fcvt.wu.s, -0.0: PASS +fcvt.wu.s, overflow: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.s, underflow: PASS +fcvt.wu.s, infinity: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.s, -infinity: PASS +fcvt.wu.s, quiet NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.s, quiet -NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.s, signaling NaN: PASS +fmv.x.s, positive: PASS +fmv.x.s, negative: PASS +fmv.x.s, 0.0: PASS +fmv.x.s, -0.0: PASS +feq.s, equal: PASS +feq.s, not equal: PASS +feq.s, 0 == -0: PASS +feq.s, quiet NaN first: PASS +feq.s, quiet NaN second: PASS +feq.s, quiet NaN both: PASS +feq.s, signaling NaN first: PASS +feq.s, signaling NaN second: PASS +feq.s, signaling NaN both: PASS +flt.s, equal: PASS +flt.s, less: PASS +flt.s, greater: PASS +flt.s, quiet NaN first: PASS +flt.s, quiet NaN second: PASS +flt.s, quiet NaN both: PASS +flt.s, signaling NaN first: PASS +flt.s, signaling NaN second: PASS +flt.s, signaling NaN both: PASS +fle.s, equal: PASS +fle.s, less: PASS +fle.s, greater: PASS +fle.s, 0 == -0: PASS +fle.s, quiet NaN first: PASS +fle.s, quiet NaN second: PASS +fle.s, quiet NaN both: PASS +fle.s, signaling NaN first: PASS +fle.s, signaling NaN second: PASS +fle.s, signaling NaN both: PASS +fclass.s, -infinity: PASS +fclass.s, -normal: PASS +fclass.s, -subnormal: PASS +fclass.s, -0.0: PASS +fclass.s, 0.0: PASS +fclass.s, subnormal: PASS +fclass.s, normal: PASS +fclass.s, infinity: PASS +fclass.s, signaling NaN: PASS +fclass.s, quiet NaN: PASS +fcvt.s.w, 0: PASS +fcvt.s.w, negative: PASS +fcvt.s.w, truncate: PASS +fcvt.s.wu, 0: PASS +fcvt.s.wu: PASS +fcvt.s.wu, truncate: PASS +fmv.s.x: PASS +fmv.s.x, truncate: PASS +fsrm: PASS +fsflags: PASS +fscsr: PASS +restore initial round mode: PASS +fcvt.l.s, truncate positive: PASS +fcvt.l.s, truncate negative: PASS +fcvt.l.s, 0.0: PASS +fcvt.l.s, -0.0: PASS +fcvt.l.s, 32-bit overflow: PASS +fcvt.l.s, overflow: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.l.s, underflow: PASS +fcvt.l.s, infinity: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.l.s, -infinity: PASS +fcvt.l.s, quiet NaN: PASS +fcvt.l.s, quiet -NaN: PASS +fcvt.l.s, signaling NaN: PASS +fcvt.lu.s, truncate positive: PASS +fcvt.lu.s, truncate negative: PASS +fcvt.lu.s, 0.0: PASS +fcvt.lu.s, -0.0: PASS +fcvt.lu.s, 32-bit overflow: PASS +fcvt.lu.s, overflow: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.lu.s, underflow: PASS +fcvt.lu.s, infinity: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.lu.s, -infinity: PASS +fcvt.lu.s, quiet NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 9223372036854775808) +fcvt.lu.s, quiet -NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 9223372036854775808) +fcvt.lu.s, signaling NaN: PASS +fcvt.s.l, 0: PASS +fcvt.s.l, negative: PASS +fcvt.s.l, 32-bit truncate: PASS +fcvt.s.lu, 0: PASS +fcvt.s.lu: PASS +fcvt.s.lu, 32-bit truncate: PASS +Exiting @ tick 7772689 because exiting with last active thread context diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/stats.txt index 0deaa3f4e..ecbfc3977 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/stats.txt @@ -1,617 +1,658 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.004665 # Number of seconds simulated -sim_ticks 4665394 # Number of ticks simulated -final_tick 4665394 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 87650 # Simulator instruction rate (inst/s) -host_op_rate 87650 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1808106 # Simulator tick rate (ticks/s) -host_mem_usage 429644 # Number of bytes of host memory used -host_seconds 2.58 # Real time elapsed on the host -sim_insts 226159 # Number of instructions simulated -sim_ops 226159 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 4623808 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 4623808 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 4623552 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 4623552 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 72247 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 72247 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 72243 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 72243 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 991086283 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 991086283 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 991031411 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 991031411 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1982117695 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1982117695 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 72247 # Number of read requests accepted -system.mem_ctrls.writeReqs 72243 # Number of write requests accepted -system.mem_ctrls.readBursts 72247 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 72243 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 2375168 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 2248640 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 2474112 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 4623808 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 4623552 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 35135 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 33568 # Number of DRAM write bursts merged with an existing one -system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 360 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 641 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 33 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 2702 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 5567 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 5413 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 5211 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 1018 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 201 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 679 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 1777 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 10251 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 1439 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 1161 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 39 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 620 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 374 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 689 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 35 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 2847 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 5733 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 5572 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 5809 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 1085 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 201 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 742 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 1831 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 10392 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 1454 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 1229 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 39 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 626 # Per bank write bursts -system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 4665243 # Total gap between requests -system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 72247 # Read request sizes (log2) -system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 72243 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 37112 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 208 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 255 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 2030 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 2392 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 2414 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 2512 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 2548 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 2499 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 2385 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 2380 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 2383 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 2379 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 2380 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 2379 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 2379 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 2379 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 2379 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 2379 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 13232 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 366.340992 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 230.810737 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 342.245951 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 3082 23.29% 23.29% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 3681 27.82% 51.11% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 1764 13.33% 64.44% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 976 7.38% 71.82% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 696 5.26% 77.08% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 455 3.44% 80.52% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 307 2.32% 82.84% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 275 2.08% 84.92% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 1996 15.08% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 13232 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 2379 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 15.599412 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 15.547106 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 1.309736 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 94 3.95% 3.95% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 1021 42.92% 46.87% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 1131 47.54% 94.41% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 122 5.13% 99.54% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-21 10 0.42% 99.96% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::36-37 1 0.04% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 2379 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 2379 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.249685 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.232515 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.782399 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 2139 89.91% 89.91% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 18 0.76% 90.67% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 109 4.58% 95.25% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 94 3.95% 99.20% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 19 0.80% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 2379 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 719075 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 1424203 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 185560 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 19.38 # Average queueing delay per DRAM burst -system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 38.38 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 509.10 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 530.31 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 991.09 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 991.03 # Average system write bandwidth in MiByte/s -system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 8.12 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 3.98 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 4.14 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.97 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 27462 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 35070 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 74.00 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 90.68 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 32.29 # Average gap between requests -system.mem_ctrls.pageHitRate 82.51 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 60632880 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 32801496 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 239275680 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 184946688 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 366325440.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 608748144 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 8669568 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 1381360344 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 69824640 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 28732560 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 2981317440 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 639.028009 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 3307806 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 5774 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 155020 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 96709 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 181835 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 1196757 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 3029299 # Time in different power states -system.mem_ctrls_1.actEnergy 33886440 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 18326952 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 184691808 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 137924928 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 348500880.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 590211744 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 11048832 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 1320078504 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 60484992 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 72883440 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 2778038520 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 595.456358 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 3342297 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 12341 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 147456 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 289875 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 157513 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 1163300 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 2894909 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states -system.cpu.clk_domain.clock 1 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 115 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 4665394 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 4665394 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 226159 # Number of instructions committed -system.cpu.committedOps 226159 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 225992 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 862 # Number of float alu accesses -system.cpu.num_func_calls 16616 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 33789 # number of instructions that are conditional controls -system.cpu.num_int_insts 225992 # number of integer instructions -system.cpu.num_fp_insts 862 # number of float instructions -system.cpu.num_int_register_reads 298589 # number of times the integer registers were read -system.cpu.num_int_register_writes 154866 # number of times the integer registers were written -system.cpu.num_fp_register_reads 733 # number of times the floating registers were read -system.cpu.num_fp_register_writes 588 # number of times the floating registers were written -system.cpu.num_mem_refs 88941 # number of memory refs -system.cpu.num_load_insts 51711 # Number of load instructions -system.cpu.num_store_insts 37230 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4665394 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 50405 # Number of branches fetched -system.cpu.op_class::No_OpClass 117 0.05% 0.05% # Class of executed instruction -system.cpu.op_class::IntAlu 136540 60.34% 60.39% # Class of executed instruction -system.cpu.op_class::IntMult 325 0.14% 60.54% # Class of executed instruction -system.cpu.op_class::IntDiv 40 0.02% 60.56% # Class of executed instruction -system.cpu.op_class::FloatAdd 104 0.05% 60.60% # Class of executed instruction -system.cpu.op_class::FloatCmp 119 0.05% 60.65% # Class of executed instruction -system.cpu.op_class::FloatCvt 43 0.02% 60.67% # Class of executed instruction -system.cpu.op_class::FloatMult 30 0.01% 60.69% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::FloatDiv 11 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::FloatSqrt 5 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::MemRead 51297 22.67% 83.36% # Class of executed instruction -system.cpu.op_class::MemWrite 37094 16.39% 99.76% # Class of executed instruction -system.cpu.op_class::FloatMemRead 414 0.18% 99.94% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 136 0.06% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 226275 # Class of executed instruction -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states -system.ruby.delayHist::bucket_size 1 # delay histogram for all message -system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 144490 # delay histogram for all message -system.ruby.delayHist | 144490 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 144490 # delay histogram for all message +sim_seconds 0.007772 +sim_ticks 7772689 +final_tick 7772689 +sim_freq 1000000000 +host_inst_rate 4127 +host_op_rate 4139 +host_tick_rate 77114 +host_mem_usage 439776 +host_seconds 100.79 +sim_insts 416024 +sim_ops 417277 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1 +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 7772689 +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 7083968 +system.mem_ctrls.bytes_read::total 7083968 +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 7083712 +system.mem_ctrls.bytes_written::total 7083712 +system.mem_ctrls.num_reads::ruby.dir_cntrl0 110687 +system.mem_ctrls.num_reads::total 110687 +system.mem_ctrls.num_writes::ruby.dir_cntrl0 110683 +system.mem_ctrls.num_writes::total 110683 +system.mem_ctrls.bw_read::ruby.dir_cntrl0 911392183 +system.mem_ctrls.bw_read::total 911392183 +system.mem_ctrls.bw_write::ruby.dir_cntrl0 911359247 +system.mem_ctrls.bw_write::total 911359247 +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1822751431 +system.mem_ctrls.bw_total::total 1822751431 +system.mem_ctrls.readReqs 110687 +system.mem_ctrls.writeReqs 110683 +system.mem_ctrls.readBursts 110687 +system.mem_ctrls.writeBursts 110683 +system.mem_ctrls.bytesReadDRAM 3722624 +system.mem_ctrls.bytesReadWrQ 3361344 +system.mem_ctrls.bytesWritten 3934464 +system.mem_ctrls.bytesReadSys 7083968 +system.mem_ctrls.bytesWrittenSys 7083712 +system.mem_ctrls.servicedByWrQ 52521 +system.mem_ctrls.mergedWrBursts 49178 +system.mem_ctrls.neitherReadNorWriteReqs 0 +system.mem_ctrls.perBankRdBursts::0 10729 +system.mem_ctrls.perBankRdBursts::1 4116 +system.mem_ctrls.perBankRdBursts::2 13533 +system.mem_ctrls.perBankRdBursts::3 1653 +system.mem_ctrls.perBankRdBursts::4 4321 +system.mem_ctrls.perBankRdBursts::5 1347 +system.mem_ctrls.perBankRdBursts::6 3789 +system.mem_ctrls.perBankRdBursts::7 6835 +system.mem_ctrls.perBankRdBursts::8 81 +system.mem_ctrls.perBankRdBursts::9 120 +system.mem_ctrls.perBankRdBursts::10 223 +system.mem_ctrls.perBankRdBursts::11 51 +system.mem_ctrls.perBankRdBursts::12 1584 +system.mem_ctrls.perBankRdBursts::13 1923 +system.mem_ctrls.perBankRdBursts::14 5368 +system.mem_ctrls.perBankRdBursts::15 2493 +system.mem_ctrls.perBankWrBursts::0 11322 +system.mem_ctrls.perBankWrBursts::1 4210 +system.mem_ctrls.perBankWrBursts::2 15017 +system.mem_ctrls.perBankWrBursts::3 1660 +system.mem_ctrls.perBankWrBursts::4 4443 +system.mem_ctrls.perBankWrBursts::5 1372 +system.mem_ctrls.perBankWrBursts::6 3914 +system.mem_ctrls.perBankWrBursts::7 7213 +system.mem_ctrls.perBankWrBursts::8 83 +system.mem_ctrls.perBankWrBursts::9 126 +system.mem_ctrls.perBankWrBursts::10 222 +system.mem_ctrls.perBankWrBursts::11 53 +system.mem_ctrls.perBankWrBursts::12 1604 +system.mem_ctrls.perBankWrBursts::13 2035 +system.mem_ctrls.perBankWrBursts::14 5698 +system.mem_ctrls.perBankWrBursts::15 2504 +system.mem_ctrls.numRdRetry 0 +system.mem_ctrls.numWrRetry 0 +system.mem_ctrls.totGap 7772603 +system.mem_ctrls.readPktSize::0 0 +system.mem_ctrls.readPktSize::1 0 +system.mem_ctrls.readPktSize::2 0 +system.mem_ctrls.readPktSize::3 0 +system.mem_ctrls.readPktSize::4 0 +system.mem_ctrls.readPktSize::5 0 +system.mem_ctrls.readPktSize::6 110687 +system.mem_ctrls.writePktSize::0 0 +system.mem_ctrls.writePktSize::1 0 +system.mem_ctrls.writePktSize::2 0 +system.mem_ctrls.writePktSize::3 0 +system.mem_ctrls.writePktSize::4 0 +system.mem_ctrls.writePktSize::5 0 +system.mem_ctrls.writePktSize::6 110683 +system.mem_ctrls.rdQLenPdf::0 58166 +system.mem_ctrls.rdQLenPdf::1 0 +system.mem_ctrls.rdQLenPdf::2 0 +system.mem_ctrls.rdQLenPdf::3 0 +system.mem_ctrls.rdQLenPdf::4 0 +system.mem_ctrls.rdQLenPdf::5 0 +system.mem_ctrls.rdQLenPdf::6 0 +system.mem_ctrls.rdQLenPdf::7 0 +system.mem_ctrls.rdQLenPdf::8 0 +system.mem_ctrls.rdQLenPdf::9 0 +system.mem_ctrls.rdQLenPdf::10 0 +system.mem_ctrls.rdQLenPdf::11 0 +system.mem_ctrls.rdQLenPdf::12 0 +system.mem_ctrls.rdQLenPdf::13 0 +system.mem_ctrls.rdQLenPdf::14 0 +system.mem_ctrls.rdQLenPdf::15 0 +system.mem_ctrls.rdQLenPdf::16 0 +system.mem_ctrls.rdQLenPdf::17 0 +system.mem_ctrls.rdQLenPdf::18 0 +system.mem_ctrls.rdQLenPdf::19 0 +system.mem_ctrls.rdQLenPdf::20 0 +system.mem_ctrls.rdQLenPdf::21 0 +system.mem_ctrls.rdQLenPdf::22 0 +system.mem_ctrls.rdQLenPdf::23 0 +system.mem_ctrls.rdQLenPdf::24 0 +system.mem_ctrls.rdQLenPdf::25 0 +system.mem_ctrls.rdQLenPdf::26 0 +system.mem_ctrls.rdQLenPdf::27 0 +system.mem_ctrls.rdQLenPdf::28 0 +system.mem_ctrls.rdQLenPdf::29 0 +system.mem_ctrls.rdQLenPdf::30 0 +system.mem_ctrls.rdQLenPdf::31 0 +system.mem_ctrls.wrQLenPdf::0 1 +system.mem_ctrls.wrQLenPdf::1 1 +system.mem_ctrls.wrQLenPdf::2 1 +system.mem_ctrls.wrQLenPdf::3 1 +system.mem_ctrls.wrQLenPdf::4 1 +system.mem_ctrls.wrQLenPdf::5 1 +system.mem_ctrls.wrQLenPdf::6 1 +system.mem_ctrls.wrQLenPdf::7 1 +system.mem_ctrls.wrQLenPdf::8 1 +system.mem_ctrls.wrQLenPdf::9 1 +system.mem_ctrls.wrQLenPdf::10 1 +system.mem_ctrls.wrQLenPdf::11 1 +system.mem_ctrls.wrQLenPdf::12 1 +system.mem_ctrls.wrQLenPdf::13 1 +system.mem_ctrls.wrQLenPdf::14 1 +system.mem_ctrls.wrQLenPdf::15 506 +system.mem_ctrls.wrQLenPdf::16 617 +system.mem_ctrls.wrQLenPdf::17 3261 +system.mem_ctrls.wrQLenPdf::18 3801 +system.mem_ctrls.wrQLenPdf::19 3848 +system.mem_ctrls.wrQLenPdf::20 3957 +system.mem_ctrls.wrQLenPdf::21 4025 +system.mem_ctrls.wrQLenPdf::22 3917 +system.mem_ctrls.wrQLenPdf::23 3770 +system.mem_ctrls.wrQLenPdf::24 3755 +system.mem_ctrls.wrQLenPdf::25 3756 +system.mem_ctrls.wrQLenPdf::26 3755 +system.mem_ctrls.wrQLenPdf::27 3753 +system.mem_ctrls.wrQLenPdf::28 3754 +system.mem_ctrls.wrQLenPdf::29 3756 +system.mem_ctrls.wrQLenPdf::30 3755 +system.mem_ctrls.wrQLenPdf::31 3752 +system.mem_ctrls.wrQLenPdf::32 3752 +system.mem_ctrls.wrQLenPdf::33 0 +system.mem_ctrls.wrQLenPdf::34 0 +system.mem_ctrls.wrQLenPdf::35 0 +system.mem_ctrls.wrQLenPdf::36 0 +system.mem_ctrls.wrQLenPdf::37 0 +system.mem_ctrls.wrQLenPdf::38 0 +system.mem_ctrls.wrQLenPdf::39 0 +system.mem_ctrls.wrQLenPdf::40 0 +system.mem_ctrls.wrQLenPdf::41 0 +system.mem_ctrls.wrQLenPdf::42 0 +system.mem_ctrls.wrQLenPdf::43 0 +system.mem_ctrls.wrQLenPdf::44 0 +system.mem_ctrls.wrQLenPdf::45 0 +system.mem_ctrls.wrQLenPdf::46 0 +system.mem_ctrls.wrQLenPdf::47 0 +system.mem_ctrls.wrQLenPdf::48 0 +system.mem_ctrls.wrQLenPdf::49 0 +system.mem_ctrls.wrQLenPdf::50 0 +system.mem_ctrls.wrQLenPdf::51 0 +system.mem_ctrls.wrQLenPdf::52 0 +system.mem_ctrls.wrQLenPdf::53 0 +system.mem_ctrls.wrQLenPdf::54 0 +system.mem_ctrls.wrQLenPdf::55 0 +system.mem_ctrls.wrQLenPdf::56 0 +system.mem_ctrls.wrQLenPdf::57 0 +system.mem_ctrls.wrQLenPdf::58 0 +system.mem_ctrls.wrQLenPdf::59 0 +system.mem_ctrls.wrQLenPdf::60 0 +system.mem_ctrls.wrQLenPdf::61 0 +system.mem_ctrls.wrQLenPdf::62 0 +system.mem_ctrls.wrQLenPdf::63 0 +system.mem_ctrls.bytesPerActivate::samples 32257 +system.mem_ctrls.bytesPerActivate::mean 237.353752 +system.mem_ctrls.bytesPerActivate::gmean 168.258285 +system.mem_ctrls.bytesPerActivate::stdev 215.463152 +system.mem_ctrls.bytesPerActivate::0-127 9760 30.25% 30.25% +system.mem_ctrls.bytesPerActivate::128-255 10338 32.04% 62.30% +system.mem_ctrls.bytesPerActivate::256-383 4791 14.85% 77.15% +system.mem_ctrls.bytesPerActivate::384-511 3665 11.36% 88.52% +system.mem_ctrls.bytesPerActivate::512-639 1586 4.91% 93.43% +system.mem_ctrls.bytesPerActivate::640-767 710 2.20% 95.63% +system.mem_ctrls.bytesPerActivate::768-895 378 1.17% 96.80% +system.mem_ctrls.bytesPerActivate::896-1023 231 0.71% 97.52% +system.mem_ctrls.bytesPerActivate::1024-1151 798 2.47% 99.99% +system.mem_ctrls.bytesPerActivate::total 32257 +system.mem_ctrls.rdPerTurnAround::samples 3752 +system.mem_ctrls.rdPerTurnAround::mean 15.498933 +system.mem_ctrls.rdPerTurnAround::gmean 15.432189 +system.mem_ctrls.rdPerTurnAround::stdev 1.461493 +system.mem_ctrls.rdPerTurnAround::12-13 256 6.82% 6.82% +system.mem_ctrls.rdPerTurnAround::14-15 1729 46.08% 52.90% +system.mem_ctrls.rdPerTurnAround::16-17 1426 38.00% 90.91% +system.mem_ctrls.rdPerTurnAround::18-19 315 8.39% 99.30% +system.mem_ctrls.rdPerTurnAround::20-21 25 0.66% 99.97% +system.mem_ctrls.rdPerTurnAround::34-35 1 0.02% 99.99% +system.mem_ctrls.rdPerTurnAround::total 3752 +system.mem_ctrls.wrPerTurnAround::samples 3752 +system.mem_ctrls.wrPerTurnAround::mean 16.384861 +system.mem_ctrls.wrPerTurnAround::gmean 16.360190 +system.mem_ctrls.wrPerTurnAround::stdev 0.935433 +system.mem_ctrls.wrPerTurnAround::16 3165 84.35% 84.35% +system.mem_ctrls.wrPerTurnAround::17 46 1.22% 85.58% +system.mem_ctrls.wrPerTurnAround::18 249 6.63% 92.21% +system.mem_ctrls.wrPerTurnAround::19 268 7.14% 99.36% +system.mem_ctrls.wrPerTurnAround::20 24 0.63% 99.99% +system.mem_ctrls.wrPerTurnAround::total 3752 +system.mem_ctrls.totQLat 1340204 +system.mem_ctrls.totMemAccLat 2445358 +system.mem_ctrls.totBusLat 290830 +system.mem_ctrls.avgQLat 23.04 +system.mem_ctrls.avgBusLat 5.00 +system.mem_ctrls.avgMemAccLat 42.04 +system.mem_ctrls.avgRdBW 478.93 +system.mem_ctrls.avgWrBW 506.19 +system.mem_ctrls.avgRdBWSys 911.39 +system.mem_ctrls.avgWrBWSys 911.35 +system.mem_ctrls.peakBW 12800.00 +system.mem_ctrls.busUtil 7.69 +system.mem_ctrls.busUtilRead 3.74 +system.mem_ctrls.busUtilWrite 3.95 +system.mem_ctrls.avgRdQLen 0.99 +system.mem_ctrls.avgWrQLen 25.93 +system.mem_ctrls.readRowHits 33196 +system.mem_ctrls.writeRowHits 54183 +system.mem_ctrls.readRowHitRate 57.07 +system.mem_ctrls.writeRowHitRate 88.09 +system.mem_ctrls.avgGap 35.11 +system.mem_ctrls.pageHitRate 73.01 +system.mem_ctrls_0.actEnergy 163991520 +system.mem_ctrls_0.preEnergy 88736760 +system.mem_ctrls_0.readEnergy 529193952 +system.mem_ctrls_0.writeEnergy 410509152 +system.mem_ctrls_0.refreshEnergy 615254640 +system.mem_ctrls_0.actBackEnergy 1051423824 +system.mem_ctrls_0.preBackEnergy 13695360 +system.mem_ctrls_0.actPowerDownEnergy 2416771728 +system.mem_ctrls_0.prePowerDownEnergy 44670336 +system.mem_ctrls_0.selfRefreshEnergy 6943896 +system.mem_ctrls_0.totalEnergy 5341236672 +system.mem_ctrls_0.averagePower 687.180031 +system.mem_ctrls_0.totalIdleTime 5430822 +system.mem_ctrls_0.memoryStateTime::IDLE 6041 +system.mem_ctrls_0.memoryStateTime::REF 260302 +system.mem_ctrls_0.memoryStateTime::SREF 14901 +system.mem_ctrls_0.memoryStateTime::PRE_PDN 116329 +system.mem_ctrls_0.memoryStateTime::ACT 2075178 +system.mem_ctrls_0.memoryStateTime::ACT_PDN 5299938 +system.mem_ctrls_1.actEnergy 66366300 +system.mem_ctrls_1.preEnergy 35904288 +system.mem_ctrls_1.readEnergy 135294432 +system.mem_ctrls_1.writeEnergy 102938400 +system.mem_ctrls_1.refreshEnergy 606649680 +system.mem_ctrls_1.actBackEnergy 871351248 +system.mem_ctrls_1.preBackEnergy 14361600 +system.mem_ctrls_1.actPowerDownEnergy 2420686032 +system.mem_ctrls_1.prePowerDownEnergy 151412736 +system.mem_ctrls_1.selfRefreshEnergy 31946400 +system.mem_ctrls_1.totalEnergy 4436911116 +system.mem_ctrls_1.averagePower 570.833480 +system.mem_ctrls_1.totalIdleTime 5824394 +system.mem_ctrls_1.memoryStateTime::IDLE 8460 +system.mem_ctrls_1.memoryStateTime::REF 256650 +system.mem_ctrls_1.memoryStateTime::SREF 121605 +system.mem_ctrls_1.memoryStateTime::PRE_PDN 394304 +system.mem_ctrls_1.memoryStateTime::ACT 1683148 +system.mem_ctrls_1.memoryStateTime::ACT_PDN 5308522 +system.pwrStateResidencyTicks::UNDEFINED 7772689 +system.cpu.clk_domain.clock 1 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 216 +system.cpu.pwrStateResidencyTicks::ON 7772689 +system.cpu.numCycles 7772689 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 416024 +system.cpu.committedOps 417277 +system.cpu.num_int_alu_accesses 415220 +system.cpu.num_fp_alu_accesses 1163 +system.cpu.num_vec_alu_accesses 0 +system.cpu.num_func_calls 23050 +system.cpu.num_conditional_control_insts 67806 +system.cpu.num_int_insts 415220 +system.cpu.num_fp_insts 1163 +system.cpu.num_vec_insts 0 +system.cpu.num_int_register_reads 525251 +system.cpu.num_int_register_writes 276296 +system.cpu.num_fp_register_reads 936 +system.cpu.num_fp_register_writes 756 +system.cpu.num_vec_register_reads 0 +system.cpu.num_vec_register_writes 0 +system.cpu.num_mem_refs 169624 +system.cpu.num_load_insts 105498 +system.cpu.num_store_insts 64126 +system.cpu.num_idle_cycles -0 +system.cpu.num_busy_cycles 7772689 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction -0 +system.cpu.Branches 90856 +system.cpu.op_class::No_OpClass 236 0.05% 0.05% +system.cpu.op_class::IntAlu 245871 58.89% 58.94% +system.cpu.op_class::IntMult 674 0.16% 59.11% +system.cpu.op_class::IntDiv 644 0.15% 59.26% +system.cpu.op_class::FloatAdd 128 0.03% 59.29% +system.cpu.op_class::FloatCmp 161 0.03% 59.33% +system.cpu.op_class::FloatCvt 109 0.02% 59.35% +system.cpu.op_class::FloatMult 30 0.00% 59.36% +system.cpu.op_class::FloatMultAcc 0 0.00% 59.36% +system.cpu.op_class::FloatDiv 11 0.00% 59.36% +system.cpu.op_class::FloatMisc 0 0.00% 59.36% +system.cpu.op_class::FloatSqrt 5 0.00% 59.37% +system.cpu.op_class::SimdAdd 0 0.00% 59.37% +system.cpu.op_class::SimdAddAcc 0 0.00% 59.37% +system.cpu.op_class::SimdAlu 0 0.00% 59.37% +system.cpu.op_class::SimdCmp 0 0.00% 59.37% +system.cpu.op_class::SimdCvt 0 0.00% 59.37% +system.cpu.op_class::SimdMisc 0 0.00% 59.37% +system.cpu.op_class::SimdMult 0 0.00% 59.37% +system.cpu.op_class::SimdMultAcc 0 0.00% 59.37% +system.cpu.op_class::SimdShift 0 0.00% 59.37% +system.cpu.op_class::SimdShiftAcc 0 0.00% 59.37% +system.cpu.op_class::SimdSqrt 0 0.00% 59.37% +system.cpu.op_class::SimdFloatAdd 0 0.00% 59.37% +system.cpu.op_class::SimdFloatAlu 0 0.00% 59.37% +system.cpu.op_class::SimdFloatCmp 0 0.00% 59.37% +system.cpu.op_class::SimdFloatCvt 0 0.00% 59.37% +system.cpu.op_class::SimdFloatDiv 0 0.00% 59.37% +system.cpu.op_class::SimdFloatMisc 0 0.00% 59.37% +system.cpu.op_class::SimdFloatMult 0 0.00% 59.37% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 59.37% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 59.37% +system.cpu.op_class::MemRead 104951 25.13% 84.50% +system.cpu.op_class::MemWrite 63954 15.31% 99.82% +system.cpu.op_class::FloatMemRead 547 0.13% 99.95% +system.cpu.op_class::FloatMemWrite 172 0.04% 99.99% +system.cpu.op_class::IprAccess 0 0.00% 99.99% +system.cpu.op_class::InstPrefetch 0 0.00% 99.99% +system.cpu.op_class::total 417493 +system.ruby.clk_domain.clock 1 +system.ruby.pwrStateResidencyTicks::UNDEFINED 7772689 +system.ruby.delayHist::bucket_size 1 +system.ruby.delayHist::max_bucket 9 +system.ruby.delayHist::samples 221370 +system.ruby.delayHist | 221370 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayHist::total 221370 system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 315216 +system.ruby.outstanding_req_hist_seqr::samples 657196 system.ruby.outstanding_req_hist_seqr::mean 1 system.ruby.outstanding_req_hist_seqr::gmean 1 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 315216 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 315216 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 657196 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 657196 system.ruby.latency_hist_seqr::bucket_size 64 system.ruby.latency_hist_seqr::max_bucket 639 -system.ruby.latency_hist_seqr::samples 315215 -system.ruby.latency_hist_seqr::mean 13.800673 -system.ruby.latency_hist_seqr::gmean 2.449814 -system.ruby.latency_hist_seqr::stdev 29.448647 -system.ruby.latency_hist_seqr | 279385 88.63% 88.63% | 33252 10.55% 99.18% | 1716 0.54% 99.73% | 307 0.10% 99.82% | 278 0.09% 99.91% | 236 0.07% 99.99% | 20 0.01% 99.99% | 8 0.00% 100.00% | 0 0.00% 100.00% | 13 0.00% 100.00% -system.ruby.latency_hist_seqr::total 315215 +system.ruby.latency_hist_seqr::samples 657195 +system.ruby.latency_hist_seqr::mean 10.827066 +system.ruby.latency_hist_seqr::gmean 1.943036 +system.ruby.latency_hist_seqr::stdev 26.888474 +system.ruby.latency_hist_seqr | 600343 91.34% 91.34% | 52822 8.03% 99.38% | 2558 0.38% 99.77% | 638 0.09% 99.87% | 440 0.06% 99.94% | 345 0.05% 99.99% | 31 0.00% 99.99% | 8 0.00% 99.99% | 0 0.00% 99.99% | 10 0.00% 99.99% +system.ruby.latency_hist_seqr::total 657195 system.ruby.hit_latency_hist_seqr::bucket_size 1 system.ruby.hit_latency_hist_seqr::max_bucket 9 -system.ruby.hit_latency_hist_seqr::samples 242968 +system.ruby.hit_latency_hist_seqr::samples 546508 system.ruby.hit_latency_hist_seqr::mean 1 system.ruby.hit_latency_hist_seqr::gmean 1 -system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 242968 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 242968 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 546508 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 546508 system.ruby.miss_latency_hist_seqr::bucket_size 64 system.ruby.miss_latency_hist_seqr::max_bucket 639 -system.ruby.miss_latency_hist_seqr::samples 72247 -system.ruby.miss_latency_hist_seqr::mean 56.849572 -system.ruby.miss_latency_hist_seqr::gmean 49.864909 -system.ruby.miss_latency_hist_seqr::stdev 37.140999 -system.ruby.miss_latency_hist_seqr | 36417 50.41% 50.41% | 33252 46.03% 96.43% | 1716 2.38% 98.81% | 307 0.42% 99.23% | 278 0.38% 99.62% | 236 0.33% 99.94% | 20 0.03% 99.97% | 8 0.01% 99.98% | 0 0.00% 99.98% | 13 0.02% 100.00% -system.ruby.miss_latency_hist_seqr::total 72247 -system.ruby.Directory.incomplete_times_seqr 72246 -system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.015485 # Average number of messages in buffer -system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.999904 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.030971 # Average number of messages in buffer -system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.751856 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.015486 # Average number of messages in buffer -system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999985 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.030971 # Average number of messages in buffer -system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999985 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.cacheMemory.demand_hits 242968 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 72247 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 315215 # Number of cache demand accesses -system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.015485 # Average number of messages in buffer -system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.999322 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.067565 # Average number of messages in buffer -system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 1.000000 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.061941 # Average number of messages in buffer -system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999999 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.015486 # Average number of messages in buffer -system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.999887 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.015485 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers03.avg_stall_time 5.999420 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.015486 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers04.avg_stall_time 5.999905 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.092910 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers07.avg_stall_time 6.751873 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 7.742647 -system.ruby.network.routers0.msg_count.Control::2 72247 -system.ruby.network.routers0.msg_count.Data::2 72243 -system.ruby.network.routers0.msg_count.Response_Data::4 72247 -system.ruby.network.routers0.msg_count.Writeback_Control::3 72243 -system.ruby.network.routers0.msg_bytes.Control::2 577976 -system.ruby.network.routers0.msg_bytes.Data::2 5201496 -system.ruby.network.routers0.msg_bytes.Response_Data::4 5201784 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 577944 -system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.030971 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers02.avg_stall_time 10.751860 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.015485 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers06.avg_stall_time 1.999808 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.015486 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers07.avg_stall_time 1.999970 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 7.742647 -system.ruby.network.routers1.msg_count.Control::2 72247 -system.ruby.network.routers1.msg_count.Data::2 72243 -system.ruby.network.routers1.msg_count.Response_Data::4 72247 -system.ruby.network.routers1.msg_count.Writeback_Control::3 72243 -system.ruby.network.routers1.msg_bytes.Control::2 577976 -system.ruby.network.routers1.msg_bytes.Data::2 5201496 -system.ruby.network.routers1.msg_bytes.Response_Data::4 5201784 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 577944 -system.ruby.network.int_link_buffers02.avg_buf_msgs 0.030971 # Average number of messages in buffer -system.ruby.network.int_link_buffers02.avg_stall_time 7.751870 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers08.avg_buf_msgs 0.015485 # Average number of messages in buffer -system.ruby.network.int_link_buffers08.avg_stall_time 2.999712 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers09.avg_buf_msgs 0.015486 # Average number of messages in buffer -system.ruby.network.int_link_buffers09.avg_stall_time 2.999954 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers13.avg_buf_msgs 0.015485 # Average number of messages in buffer -system.ruby.network.int_link_buffers13.avg_stall_time 4.999518 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers14.avg_buf_msgs 0.015486 # Average number of messages in buffer -system.ruby.network.int_link_buffers14.avg_stall_time 4.999922 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers17.avg_buf_msgs 0.030971 # Average number of messages in buffer -system.ruby.network.int_link_buffers17.avg_stall_time 9.751864 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.015485 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers03.avg_stall_time 3.999615 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.015486 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers04.avg_stall_time 3.999938 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.030971 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers07.avg_stall_time 8.751867 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 7.742647 -system.ruby.network.routers2.msg_count.Control::2 72247 -system.ruby.network.routers2.msg_count.Data::2 72243 -system.ruby.network.routers2.msg_count.Response_Data::4 72247 -system.ruby.network.routers2.msg_count.Writeback_Control::3 72243 -system.ruby.network.routers2.msg_bytes.Control::2 577976 -system.ruby.network.routers2.msg_bytes.Data::2 5201496 -system.ruby.network.routers2.msg_bytes.Response_Data::4 5201784 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 577944 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Control 216741 -system.ruby.network.msg_count.Data 216729 -system.ruby.network.msg_count.Response_Data 216741 -system.ruby.network.msg_count.Writeback_Control 216729 -system.ruby.network.msg_byte.Control 1733928 -system.ruby.network.msg_byte.Data 15604488 -system.ruby.network.msg_byte.Response_Data 15605352 -system.ruby.network.msg_byte.Writeback_Control 1733832 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 7.742819 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 72247 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 72243 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 5201784 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 577944 -system.ruby.network.routers0.throttle1.link_utilization 7.742476 -system.ruby.network.routers0.throttle1.msg_count.Control::2 72247 -system.ruby.network.routers0.throttle1.msg_count.Data::2 72243 -system.ruby.network.routers0.throttle1.msg_bytes.Control::2 577976 -system.ruby.network.routers0.throttle1.msg_bytes.Data::2 5201496 -system.ruby.network.routers1.throttle0.link_utilization 7.742476 -system.ruby.network.routers1.throttle0.msg_count.Control::2 72247 -system.ruby.network.routers1.throttle0.msg_count.Data::2 72243 -system.ruby.network.routers1.throttle0.msg_bytes.Control::2 577976 -system.ruby.network.routers1.throttle0.msg_bytes.Data::2 5201496 -system.ruby.network.routers1.throttle1.link_utilization 7.742819 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 72247 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 72243 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 5201784 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 577944 -system.ruby.network.routers2.throttle0.link_utilization 7.742819 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 72247 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 72243 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 5201784 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 577944 -system.ruby.network.routers2.throttle1.link_utilization 7.742476 -system.ruby.network.routers2.throttle1.msg_count.Control::2 72247 -system.ruby.network.routers2.throttle1.msg_count.Data::2 72243 -system.ruby.network.routers2.throttle1.msg_bytes.Control::2 577976 -system.ruby.network.routers2.throttle1.msg_bytes.Data::2 5201496 -system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 72247 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 72247 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 72247 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 72243 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 72243 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 72243 # delay histogram for vnet_2 +system.ruby.miss_latency_hist_seqr::samples 110687 +system.ruby.miss_latency_hist_seqr::mean 59.347403 +system.ruby.miss_latency_hist_seqr::gmean 51.621697 +system.ruby.miss_latency_hist_seqr::stdev 38.231731 +system.ruby.miss_latency_hist_seqr | 53835 48.63% 48.63% | 52822 47.72% 96.35% | 2558 2.31% 98.67% | 638 0.57% 99.24% | 440 0.39% 99.64% | 345 0.31% 99.95% | 31 0.02% 99.98% | 8 0.00% 99.99% | 0 0.00% 99.99% | 10 0.00% 99.99% +system.ruby.miss_latency_hist_seqr::total 110687 +system.ruby.Directory.incomplete_times_seqr 110686 +system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.014239 +system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.999949 +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.028480 +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.771956 +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.014240 +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999991 +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.028480 +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999991 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 7772689 +system.ruby.l1_cntrl0.cacheMemory.demand_hits 546508 +system.ruby.l1_cntrl0.cacheMemory.demand_misses 110687 +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 657195 +system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.014239 +system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.999643 +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.084551 +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999999 +system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.056960 +system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999999 +system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.014240 +system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.999932 +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 7772689 +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 7772689 +system.ruby.memctrl_clk_domain.clock 3 +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.014239 +system.ruby.network.routers0.port_buffers03.avg_stall_time 5.999695 +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.014240 +system.ruby.network.routers0.port_buffers04.avg_stall_time 5.999942 +system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.085440 +system.ruby.network.routers0.port_buffers07.avg_stall_time 6.771967 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 7772689 +system.ruby.network.routers0.percent_links_utilized 7.120122 +system.ruby.network.routers0.msg_count.Control::2 110687 +system.ruby.network.routers0.msg_count.Data::2 110683 +system.ruby.network.routers0.msg_count.Response_Data::4 110687 +system.ruby.network.routers0.msg_count.Writeback_Control::3 110683 +system.ruby.network.routers0.msg_bytes.Control::2 885496 +system.ruby.network.routers0.msg_bytes.Data::2 7969176 +system.ruby.network.routers0.msg_bytes.Response_Data::4 7969464 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 885464 +system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.028480 +system.ruby.network.routers1.port_buffers02.avg_stall_time 10.771959 +system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.014239 +system.ruby.network.routers1.port_buffers06.avg_stall_time 1.999899 +system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.014240 +system.ruby.network.routers1.port_buffers07.avg_stall_time 1.999981 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 7772689 +system.ruby.network.routers1.percent_links_utilized 7.120122 +system.ruby.network.routers1.msg_count.Control::2 110687 +system.ruby.network.routers1.msg_count.Data::2 110683 +system.ruby.network.routers1.msg_count.Response_Data::4 110687 +system.ruby.network.routers1.msg_count.Writeback_Control::3 110683 +system.ruby.network.routers1.msg_bytes.Control::2 885496 +system.ruby.network.routers1.msg_bytes.Data::2 7969176 +system.ruby.network.routers1.msg_bytes.Response_Data::4 7969464 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 885464 +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.028480 +system.ruby.network.int_link_buffers02.avg_stall_time 7.771965 +system.ruby.network.int_link_buffers08.avg_buf_msgs 0.014239 +system.ruby.network.int_link_buffers08.avg_stall_time 2.999848 +system.ruby.network.int_link_buffers09.avg_buf_msgs 0.014240 +system.ruby.network.int_link_buffers09.avg_stall_time 2.999972 +system.ruby.network.int_link_buffers13.avg_buf_msgs 0.014239 +system.ruby.network.int_link_buffers13.avg_stall_time 4.999746 +system.ruby.network.int_link_buffers14.avg_buf_msgs 0.014240 +system.ruby.network.int_link_buffers14.avg_stall_time 4.999953 +system.ruby.network.int_link_buffers17.avg_buf_msgs 0.028480 +system.ruby.network.int_link_buffers17.avg_stall_time 9.771961 +system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.014239 +system.ruby.network.routers2.port_buffers03.avg_stall_time 3.999797 +system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.014240 +system.ruby.network.routers2.port_buffers04.avg_stall_time 3.999962 +system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.028480 +system.ruby.network.routers2.port_buffers07.avg_stall_time 8.771963 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 7772689 +system.ruby.network.routers2.percent_links_utilized 7.120122 +system.ruby.network.routers2.msg_count.Control::2 110687 +system.ruby.network.routers2.msg_count.Data::2 110683 +system.ruby.network.routers2.msg_count.Response_Data::4 110687 +system.ruby.network.routers2.msg_count.Writeback_Control::3 110683 +system.ruby.network.routers2.msg_bytes.Control::2 885496 +system.ruby.network.routers2.msg_bytes.Data::2 7969176 +system.ruby.network.routers2.msg_bytes.Response_Data::4 7969464 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 885464 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 7772689 +system.ruby.network.msg_count.Control 332061 +system.ruby.network.msg_count.Data 332049 +system.ruby.network.msg_count.Response_Data 332061 +system.ruby.network.msg_count.Writeback_Control 332049 +system.ruby.network.msg_byte.Control 2656488 +system.ruby.network.msg_byte.Data 23907528 +system.ruby.network.msg_byte.Response_Data 23908392 +system.ruby.network.msg_byte.Writeback_Control 2656392 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 7772689 +system.ruby.network.routers0.throttle0.link_utilization 7.120225 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 110687 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 110683 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 7969464 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 885464 +system.ruby.network.routers0.throttle1.link_utilization 7.120019 +system.ruby.network.routers0.throttle1.msg_count.Control::2 110687 +system.ruby.network.routers0.throttle1.msg_count.Data::2 110683 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 885496 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 7969176 +system.ruby.network.routers1.throttle0.link_utilization 7.120019 +system.ruby.network.routers1.throttle0.msg_count.Control::2 110687 +system.ruby.network.routers1.throttle0.msg_count.Data::2 110683 +system.ruby.network.routers1.throttle0.msg_bytes.Control::2 885496 +system.ruby.network.routers1.throttle0.msg_bytes.Data::2 7969176 +system.ruby.network.routers1.throttle1.link_utilization 7.120225 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 110687 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 110683 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 7969464 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 885464 +system.ruby.network.routers2.throttle0.link_utilization 7.120225 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 110687 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 110683 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 7969464 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 885464 +system.ruby.network.routers2.throttle1.link_utilization 7.120019 +system.ruby.network.routers2.throttle1.msg_count.Control::2 110687 +system.ruby.network.routers2.throttle1.msg_count.Data::2 110683 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 885496 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 7969176 +system.ruby.delayVCHist.vnet_1::bucket_size 1 +system.ruby.delayVCHist.vnet_1::max_bucket 9 +system.ruby.delayVCHist.vnet_1::samples 110687 +system.ruby.delayVCHist.vnet_1 | 110687 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayVCHist.vnet_1::total 110687 +system.ruby.delayVCHist.vnet_2::bucket_size 1 +system.ruby.delayVCHist.vnet_2::max_bucket 9 +system.ruby.delayVCHist.vnet_2::samples 110683 +system.ruby.delayVCHist.vnet_2 | 110683 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayVCHist.vnet_2::total 110683 system.ruby.LD.latency_hist_seqr::bucket_size 64 system.ruby.LD.latency_hist_seqr::max_bucket 639 -system.ruby.LD.latency_hist_seqr::samples 51711 -system.ruby.LD.latency_hist_seqr::mean 28.269208 -system.ruby.LD.latency_hist_seqr::gmean 7.619512 -system.ruby.LD.latency_hist_seqr::stdev 36.060908 -system.ruby.LD.latency_hist_seqr | 41177 79.63% 79.63% | 9735 18.83% 98.45% | 541 1.05% 99.50% | 99 0.19% 99.69% | 79 0.15% 99.85% | 70 0.14% 99.98% | 7 0.01% 99.99% | 2 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% -system.ruby.LD.latency_hist_seqr::total 51711 +system.ruby.LD.latency_hist_seqr::samples 103807 +system.ruby.LD.latency_hist_seqr::mean 27.942055 +system.ruby.LD.latency_hist_seqr::gmean 6.842921 +system.ruby.LD.latency_hist_seqr::stdev 37.598173 +system.ruby.LD.latency_hist_seqr | 81931 78.92% 78.92% | 20231 19.48% 98.41% | 1027 0.98% 99.40% | 266 0.25% 99.66% | 192 0.18% 99.84% | 140 0.13% 99.98% | 15 0.01% 99.99% | 2 0.00% 99.99% | 0 0.00% 99.99% | 3 0.00% 99.99% +system.ruby.LD.latency_hist_seqr::total 103807 system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 -system.ruby.LD.hit_latency_hist_seqr::samples 24257 +system.ruby.LD.hit_latency_hist_seqr::samples 52206 system.ruby.LD.hit_latency_hist_seqr::mean 1 system.ruby.LD.hit_latency_hist_seqr::gmean 1 -system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 24257 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 24257 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 52206 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 52206 system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 -system.ruby.LD.miss_latency_hist_seqr::samples 27454 -system.ruby.LD.miss_latency_hist_seqr::mean 52.362934 -system.ruby.LD.miss_latency_hist_seqr::gmean 45.830488 -system.ruby.LD.miss_latency_hist_seqr::stdev 34.811219 -system.ruby.LD.miss_latency_hist_seqr | 16920 61.63% 61.63% | 9735 35.46% 97.09% | 541 1.97% 99.06% | 99 0.36% 99.42% | 79 0.29% 99.71% | 70 0.25% 99.96% | 7 0.03% 99.99% | 2 0.01% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 27454 +system.ruby.LD.miss_latency_hist_seqr::samples 51601 +system.ruby.LD.miss_latency_hist_seqr::mean 55.199996 +system.ruby.LD.miss_latency_hist_seqr::gmean 47.893438 +system.ruby.LD.miss_latency_hist_seqr::stdev 36.965366 +system.ruby.LD.miss_latency_hist_seqr | 29725 57.60% 57.60% | 20231 39.20% 96.81% | 1027 1.99% 98.80% | 266 0.51% 99.31% | 192 0.37% 99.68% | 140 0.27% 99.96% | 15 0.02% 99.99% | 2 0.00% 99.99% | 0 0.00% 99.99% | 3 0.00% 99.99% +system.ruby.LD.miss_latency_hist_seqr::total 51601 system.ruby.ST.latency_hist_seqr::bucket_size 64 system.ruby.ST.latency_hist_seqr::max_bucket 639 -system.ruby.ST.latency_hist_seqr::samples 37229 -system.ruby.ST.latency_hist_seqr::mean 15.219587 -system.ruby.ST.latency_hist_seqr::gmean 3.175846 -system.ruby.ST.latency_hist_seqr::stdev 28.311515 -system.ruby.ST.latency_hist_seqr | 33814 90.83% 90.83% | 3147 8.45% 99.28% | 181 0.49% 99.77% | 30 0.08% 99.85% | 22 0.06% 99.91% | 24 0.06% 99.97% | 1 0.00% 99.97% | 1 0.00% 99.98% | 0 0.00% 99.98% | 9 0.02% 100.00% -system.ruby.ST.latency_hist_seqr::total 37229 +system.ruby.ST.latency_hist_seqr::samples 62435 +system.ruby.ST.latency_hist_seqr::mean 13.837302 +system.ruby.ST.latency_hist_seqr::gmean 2.836323 +system.ruby.ST.latency_hist_seqr::stdev 26.755275 +system.ruby.ST.latency_hist_seqr | 57924 92.77% 92.77% | 4106 6.57% 99.35% | 298 0.47% 99.82% | 54 0.08% 99.91% | 24 0.03% 99.95% | 20 0.03% 99.98% | 5 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 4 0.00% 99.99% +system.ruby.ST.latency_hist_seqr::total 62435 system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 -system.ruby.ST.hit_latency_hist_seqr::samples 25699 +system.ruby.ST.hit_latency_hist_seqr::samples 44922 system.ruby.ST.hit_latency_hist_seqr::mean 1 system.ruby.ST.hit_latency_hist_seqr::gmean 1 -system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 25699 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist_seqr::total 25699 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 44922 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 44922 system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 -system.ruby.ST.miss_latency_hist_seqr::samples 11530 -system.ruby.ST.miss_latency_hist_seqr::mean 46.913356 -system.ruby.ST.miss_latency_hist_seqr::gmean 41.729617 -system.ruby.ST.miss_latency_hist_seqr::stdev 33.659248 -system.ruby.ST.miss_latency_hist_seqr | 8115 70.38% 70.38% | 3147 27.29% 97.68% | 181 1.57% 99.25% | 30 0.26% 99.51% | 22 0.19% 99.70% | 24 0.21% 99.90% | 1 0.01% 99.91% | 1 0.01% 99.92% | 0 0.00% 99.92% | 9 0.08% 100.00% -system.ruby.ST.miss_latency_hist_seqr::total 11530 +system.ruby.ST.miss_latency_hist_seqr::samples 17513 +system.ruby.ST.miss_latency_hist_seqr::mean 46.765831 +system.ruby.ST.miss_latency_hist_seqr::gmean 41.124814 +system.ruby.ST.miss_latency_hist_seqr::stdev 32.327249 +system.ruby.ST.miss_latency_hist_seqr | 13002 74.24% 74.24% | 4106 23.44% 97.68% | 298 1.70% 99.38% | 54 0.30% 99.69% | 24 0.13% 99.83% | 20 0.11% 99.94% | 5 0.02% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 4 0.02% 99.99% +system.ruby.ST.miss_latency_hist_seqr::total 17513 system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.latency_hist_seqr::samples 226275 -system.ruby.IFETCH.latency_hist_seqr::mean 10.260700 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.811203 -system.ruby.IFETCH.latency_hist_seqr::stdev 26.801914 -system.ruby.IFETCH.latency_hist_seqr | 204394 90.33% 90.33% | 20370 9.00% 99.33% | 994 0.44% 99.77% | 178 0.08% 99.85% | 177 0.08% 99.93% | 142 0.06% 99.99% | 12 0.01% 100.00% | 5 0.00% 100.00% | 0 0.00% 100.00% | 3 0.00% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 226275 +system.ruby.IFETCH.latency_hist_seqr::samples 487571 +system.ruby.IFETCH.latency_hist_seqr::mean 6.860430 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.421640 +system.ruby.IFETCH.latency_hist_seqr::stdev 22.402281 +system.ruby.IFETCH.latency_hist_seqr | 457111 93.75% 93.75% | 28480 5.84% 99.59% | 1233 0.25% 99.84% | 318 0.06% 99.91% | 224 0.04% 99.95% | 185 0.03% 99.99% | 11 0.00% 99.99% | 6 0.00% 99.99% | 0 0.00% 99.99% | 3 0.00% 99.99% +system.ruby.IFETCH.latency_hist_seqr::total 487571 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 193012 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 446077 system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 -system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 193012 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 193012 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 446077 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 446077 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.miss_latency_hist_seqr::samples 33263 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 63.996873 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 56.865504 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 38.748066 -system.ruby.IFETCH.miss_latency_hist_seqr | 11382 34.22% 34.22% | 20370 61.24% 95.46% | 994 2.99% 98.45% | 178 0.54% 98.98% | 177 0.53% 99.51% | 142 0.43% 99.94% | 12 0.04% 99.98% | 5 0.02% 99.99% | 0 0.00% 99.99% | 3 0.01% 100.00% -system.ruby.IFETCH.miss_latency_hist_seqr::total 33263 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 41494 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 69.862389 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 62.422428 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 39.479620 +system.ruby.IFETCH.miss_latency_hist_seqr | 11034 26.59% 26.59% | 28480 68.63% 95.22% | 1233 2.97% 98.19% | 318 0.76% 98.96% | 224 0.53% 99.50% | 185 0.44% 99.95% | 11 0.02% 99.97% | 6 0.01% 99.99% | 0 0.00% 99.99% | 3 0.00% 99.99% +system.ruby.IFETCH.miss_latency_hist_seqr::total 41494 +system.ruby.Load_Linked.latency_hist_seqr::bucket_size 16 +system.ruby.Load_Linked.latency_hist_seqr::max_bucket 159 +system.ruby.Load_Linked.latency_hist_seqr::samples 1691 +system.ruby.Load_Linked.latency_hist_seqr::mean 2.568302 +system.ruby.Load_Linked.latency_hist_seqr::gmean 1.178593 +system.ruby.Load_Linked.latency_hist_seqr::stdev 7.411124 +system.ruby.Load_Linked.latency_hist_seqr | 1612 95.32% 95.32% | 0 0.00% 95.32% | 74 4.37% 99.70% | 0 0.00% 99.70% | 3 0.17% 99.88% | 2 0.11% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% +system.ruby.Load_Linked.latency_hist_seqr::total 1691 +system.ruby.Load_Linked.hit_latency_hist_seqr::bucket_size 1 +system.ruby.Load_Linked.hit_latency_hist_seqr::max_bucket 9 +system.ruby.Load_Linked.hit_latency_hist_seqr::samples 1612 +system.ruby.Load_Linked.hit_latency_hist_seqr::mean 1 +system.ruby.Load_Linked.hit_latency_hist_seqr::gmean 1 +system.ruby.Load_Linked.hit_latency_hist_seqr | 0 0.00% 0.00% | 1612 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Load_Linked.hit_latency_hist_seqr::total 1612 +system.ruby.Load_Linked.miss_latency_hist_seqr::bucket_size 16 +system.ruby.Load_Linked.miss_latency_hist_seqr::max_bucket 159 +system.ruby.Load_Linked.miss_latency_hist_seqr::samples 79 +system.ruby.Load_Linked.miss_latency_hist_seqr::mean 34.569620 +system.ruby.Load_Linked.miss_latency_hist_seqr::gmean 33.693646 +system.ruby.Load_Linked.miss_latency_hist_seqr::stdev 10.099103 +system.ruby.Load_Linked.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 74 93.67% 93.67% | 0 0.00% 93.67% | 3 3.79% 97.46% | 2 2.53% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% +system.ruby.Load_Linked.miss_latency_hist_seqr::total 79 +system.ruby.Store_Conditional.latency_hist_seqr::bucket_size 1 +system.ruby.Store_Conditional.latency_hist_seqr::max_bucket 9 +system.ruby.Store_Conditional.latency_hist_seqr::samples 1691 +system.ruby.Store_Conditional.latency_hist_seqr::mean 1 +system.ruby.Store_Conditional.latency_hist_seqr::gmean 1 +system.ruby.Store_Conditional.latency_hist_seqr | 0 0.00% 0.00% | 1691 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Store_Conditional.latency_hist_seqr::total 1691 +system.ruby.Store_Conditional.hit_latency_hist_seqr::bucket_size 1 +system.ruby.Store_Conditional.hit_latency_hist_seqr::max_bucket 9 +system.ruby.Store_Conditional.hit_latency_hist_seqr::samples 1691 +system.ruby.Store_Conditional.hit_latency_hist_seqr::mean 1 +system.ruby.Store_Conditional.hit_latency_hist_seqr::gmean 1 +system.ruby.Store_Conditional.hit_latency_hist_seqr | 0 0.00% 0.00% | 1691 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Store_Conditional.hit_latency_hist_seqr::total 1691 system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 -system.ruby.Directory.miss_mach_latency_hist_seqr::samples 72247 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 56.849572 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 49.864909 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 37.140999 -system.ruby.Directory.miss_mach_latency_hist_seqr | 36417 50.41% 50.41% | 33252 46.03% 96.43% | 1716 2.38% 98.81% | 307 0.42% 99.23% | 278 0.38% 99.62% | 236 0.33% 99.94% | 20 0.03% 99.97% | 8 0.01% 99.98% | 0 0.00% 99.98% | 13 0.02% 100.00% -system.ruby.Directory.miss_mach_latency_hist_seqr::total 72247 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 110687 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 59.347403 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 51.621697 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 38.231731 +system.ruby.Directory.miss_mach_latency_hist_seqr | 53835 48.63% 48.63% | 52822 47.72% 96.35% | 2558 2.31% 98.67% | 638 0.57% 99.24% | 440 0.39% 99.64% | 345 0.31% 99.95% | 31 0.02% 99.98% | 8 0.00% 99.99% | 0 0.00% 99.99% | 10 0.00% 99.99% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 110687 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 @@ -634,57 +675,65 @@ system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucke system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 74.999999 system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 27454 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 52.362934 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 45.830488 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 34.811219 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 16920 61.63% 61.63% | 9735 35.46% 97.09% | 541 1.97% 99.06% | 99 0.36% 99.42% | 79 0.29% 99.71% | 70 0.25% 99.96% | 7 0.03% 99.99% | 2 0.01% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 27454 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 51601 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 55.199996 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 47.893438 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 36.965366 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 29725 57.60% 57.60% | 20231 39.20% 96.81% | 1027 1.99% 98.80% | 266 0.51% 99.31% | 192 0.37% 99.68% | 140 0.27% 99.96% | 15 0.02% 99.99% | 2 0.00% 99.99% | 0 0.00% 99.99% | 3 0.00% 99.99% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 51601 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 11530 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 46.913356 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 41.729617 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 33.659248 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 8115 70.38% 70.38% | 3147 27.29% 97.68% | 181 1.57% 99.25% | 30 0.26% 99.51% | 22 0.19% 99.70% | 24 0.21% 99.90% | 1 0.01% 99.91% | 1 0.01% 99.92% | 0 0.00% 99.92% | 9 0.08% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 11530 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 17513 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 46.765831 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 41.124814 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 32.327249 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 13002 74.24% 74.24% | 4106 23.44% 97.68% | 298 1.70% 99.38% | 54 0.30% 99.69% | 24 0.13% 99.83% | 20 0.11% 99.94% | 5 0.02% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 4 0.02% 99.99% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 17513 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 33263 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 63.996873 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 56.865504 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 38.748066 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 11382 34.22% 34.22% | 20370 61.24% 95.46% | 994 2.99% 98.45% | 178 0.54% 98.98% | 177 0.53% 99.51% | 142 0.43% 99.94% | 12 0.04% 99.98% | 5 0.02% 99.99% | 0 0.00% 99.99% | 3 0.01% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 33263 -system.ruby.Directory_Controller.GETX 72247 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 72243 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 72247 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 72243 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 72247 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 72243 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 72247 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 72243 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 51711 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 226275 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 37229 0.00% 0.00% -system.ruby.L1Cache_Controller.Data 72247 0.00% 0.00% -system.ruby.L1Cache_Controller.Replacement 72243 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack 72243 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 27454 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Ifetch 33263 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Store 11530 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Load 24257 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 193012 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Store 25699 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Replacement 72243 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack 72243 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data 60717 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Data 11530 0.00% 0.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 41494 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 69.862389 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 62.422428 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 39.479620 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 11034 26.59% 26.59% | 28480 68.63% 95.22% | 1233 2.97% 98.19% | 318 0.76% 98.96% | 224 0.53% 99.50% | 185 0.44% 99.95% | 11 0.02% 99.97% | 6 0.01% 99.99% | 0 0.00% 99.99% | 3 0.00% 99.99% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 41494 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::bucket_size 16 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::max_bucket 159 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::samples 79 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::mean 34.569620 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::gmean 33.693646 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::stdev 10.099103 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 74 93.67% 93.67% | 0 0.00% 93.67% | 3 3.79% 97.46% | 2 2.53% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::total 79 +system.ruby.Directory_Controller.GETX 110687 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 110683 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 110687 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 110683 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 110687 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 110683 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 110687 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 110683 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 103807 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 487571 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 65817 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 110687 0.00% 0.00% +system.ruby.L1Cache_Controller.Replacement 110683 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 110683 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 51601 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 41494 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 17592 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 52206 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 446077 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Store 48225 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Replacement 110683 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 110683 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 93095 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data 17592 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/config.ini index 47eb7a125..2b4e6310f 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/config.ini @@ -85,8 +85,10 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer +wait_for_remote_gdb=false workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side @@ -287,7 +289,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=insttest cwd= drivers= @@ -296,14 +298,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64f/insttest gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/config.json index 58b36202f..c32e5a537 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/config.json +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/config.json @@ -292,6 +292,7 @@ }, "p_state_clk_gate_bins": 20, "p_state_clk_gate_min": 1000, + "syscallRetryLatency": 10000, "interrupts": [ { "eventq_index": 0, @@ -376,21 +377,22 @@ "uid": 100, "pid": 100, "kvmInSE": false, - "cxx_class": "LiveProcess", - "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest", + "cxx_class": "Process", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64f/insttest", "drivers": [], "system": "system", "gid": 100, "eventq_index": 0, "env": [], - "input": "cin", - "ppid": 99, - "type": "LiveProcess", + "maxStackSize": 67108864, + "ppid": 0, + "type": "Process", "cwd": "", + "pgid": 100, "simpoint": 0, "euid": 100, + "input": "cin", "path": "system.cpu.workload", - "max_stack_size": 67108864, "name": "workload", "cmd": [ "insttest" @@ -402,6 +404,7 @@ } ], "name": "cpu", + "wait_for_remote_gdb": false, "dtb": { "name": "dtb", "eventq_index": 0, diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/simerr index fd133b12b..eaef272b7 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/simerr +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/simerr @@ -1,3 +1,5 @@ -warn: Unknown operating system; assuming Linux. warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings. + Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest' +info: Increasing stack size by one page. diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/simout index 5080c6704..cefbaa693 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/simout +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/simout @@ -3,14 +3,12 @@ Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv6 gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 30 2016 14:33:35 -gem5 started Nov 30 2016 16:18:33 -gem5 executing on zizzer, pid 34081 -command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/simple-timing +gem5 compiled Jul 13 2017 17:09:45 +gem5 started Jul 13 2017 17:10:19 +gem5 executing on boldrock, pid 1506 +command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. clear fsflags: PASS flw: PASS fsw: PASS @@ -118,4 +116,105 @@ fcvt.w.s, truncate negative: PASS fcvt.w.s, 0.0: PASS fcvt.w.s, -0.0: PASS fcvt.w.s, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) -Exiting @ tick 385535500 because target called exit() +fcvt.w.s, underflow: PASS +fcvt.w.s, infinity: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +fcvt.w.s, -infinity: PASS +fcvt.w.s, quiet NaN: PASS +fcvt.w.s, quiet -NaN: PASS +fcvt.w.s, signaling NaN: PASS +fcvt.wu.s, truncate positive: PASS +fcvt.wu.s, truncate negative: PASS +fcvt.wu.s, 0.0: PASS +fcvt.wu.s, -0.0: PASS +fcvt.wu.s, overflow: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.s, underflow: PASS +fcvt.wu.s, infinity: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.s, -infinity: PASS +fcvt.wu.s, quiet NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.s, quiet -NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.wu.s, signaling NaN: PASS +fmv.x.s, positive: PASS +fmv.x.s, negative: PASS +fmv.x.s, 0.0: PASS +fmv.x.s, -0.0: PASS +feq.s, equal: PASS +feq.s, not equal: PASS +feq.s, 0 == -0: PASS +feq.s, quiet NaN first: PASS +feq.s, quiet NaN second: PASS +feq.s, quiet NaN both: PASS +feq.s, signaling NaN first: PASS +feq.s, signaling NaN second: PASS +feq.s, signaling NaN both: PASS +flt.s, equal: PASS +flt.s, less: PASS +flt.s, greater: PASS +flt.s, quiet NaN first: PASS +flt.s, quiet NaN second: PASS +flt.s, quiet NaN both: PASS +flt.s, signaling NaN first: PASS +flt.s, signaling NaN second: PASS +flt.s, signaling NaN both: PASS +fle.s, equal: PASS +fle.s, less: PASS +fle.s, greater: PASS +fle.s, 0 == -0: PASS +fle.s, quiet NaN first: PASS +fle.s, quiet NaN second: PASS +fle.s, quiet NaN both: PASS +fle.s, signaling NaN first: PASS +fle.s, signaling NaN second: PASS +fle.s, signaling NaN both: PASS +fclass.s, -infinity: PASS +fclass.s, -normal: PASS +fclass.s, -subnormal: PASS +fclass.s, -0.0: PASS +fclass.s, 0.0: PASS +fclass.s, subnormal: PASS +fclass.s, normal: PASS +fclass.s, infinity: PASS +fclass.s, signaling NaN: PASS +fclass.s, quiet NaN: PASS +fcvt.s.w, 0: PASS +fcvt.s.w, negative: PASS +fcvt.s.w, truncate: PASS +fcvt.s.wu, 0: PASS +fcvt.s.wu: PASS +fcvt.s.wu, truncate: PASS +fmv.s.x: PASS +fmv.s.x, truncate: PASS +fsrm: PASS +fsflags: PASS +fscsr: PASS +restore initial round mode: PASS +fcvt.l.s, truncate positive: PASS +fcvt.l.s, truncate negative: PASS +fcvt.l.s, 0.0: PASS +fcvt.l.s, -0.0: PASS +fcvt.l.s, 32-bit overflow: PASS +fcvt.l.s, overflow: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.l.s, underflow: PASS +fcvt.l.s, infinity: [1;31mFAIL[0m (expected 9223372036854775807; found -9223372036854775808) +fcvt.l.s, -infinity: PASS +fcvt.l.s, quiet NaN: PASS +fcvt.l.s, quiet -NaN: PASS +fcvt.l.s, signaling NaN: PASS +fcvt.lu.s, truncate positive: PASS +fcvt.lu.s, truncate negative: PASS +fcvt.lu.s, 0.0: PASS +fcvt.lu.s, -0.0: PASS +fcvt.lu.s, 32-bit overflow: PASS +fcvt.lu.s, overflow: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.lu.s, underflow: PASS +fcvt.lu.s, infinity: [1;31mFAIL[0m (expected 18446744073709551615; found 0) +fcvt.lu.s, -infinity: PASS +fcvt.lu.s, quiet NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 9223372036854775808) +fcvt.lu.s, quiet -NaN: [1;31mFAIL[0m (expected 18446744073709551615; found 9223372036854775808) +fcvt.lu.s, signaling NaN: PASS +fcvt.s.l, 0: PASS +fcvt.s.l, negative: PASS +fcvt.s.l, 32-bit truncate: PASS +fcvt.s.lu, 0: PASS +fcvt.s.lu: PASS +fcvt.s.lu, 32-bit truncate: PASS +Exiting @ tick 755664500 because exiting with last active thread context diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/stats.txt index 6fa0e9628..4afe355a4 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/stats.txt @@ -1,521 +1,556 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000386 # Number of seconds simulated -sim_ticks 385535500 # Number of ticks simulated -final_tick 385535500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 27855 # Simulator instruction rate (inst/s) -host_op_rate 27855 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47485128 # Simulator tick rate (ticks/s) -host_mem_usage 243704 # Number of bytes of host memory used -host_seconds 8.12 # Real time elapsed on the host -sim_insts 226159 # Number of instructions simulated -sim_ops 226159 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 53632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18944 # Number of bytes read from this memory -system.physmem.bytes_read::total 72576 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 53632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 53632 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 838 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 296 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1134 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 139110406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 49136850 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 188247256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 139110406 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 139110406 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 139110406 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 49136850 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 188247256 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 115 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 385535500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 771071 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 226159 # Number of instructions committed -system.cpu.committedOps 226159 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 225992 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 862 # Number of float alu accesses -system.cpu.num_func_calls 16616 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 33789 # number of instructions that are conditional controls -system.cpu.num_int_insts 225992 # number of integer instructions -system.cpu.num_fp_insts 862 # number of float instructions -system.cpu.num_int_register_reads 298589 # number of times the integer registers were read -system.cpu.num_int_register_writes 154866 # number of times the integer registers were written -system.cpu.num_fp_register_reads 733 # number of times the floating registers were read -system.cpu.num_fp_register_writes 588 # number of times the floating registers were written -system.cpu.num_mem_refs 88941 # number of memory refs -system.cpu.num_load_insts 51711 # Number of load instructions -system.cpu.num_store_insts 37230 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 771071 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 50405 # Number of branches fetched -system.cpu.op_class::No_OpClass 117 0.05% 0.05% # Class of executed instruction -system.cpu.op_class::IntAlu 136540 60.34% 60.39% # Class of executed instruction -system.cpu.op_class::IntMult 325 0.14% 60.54% # Class of executed instruction -system.cpu.op_class::IntDiv 40 0.02% 60.56% # Class of executed instruction -system.cpu.op_class::FloatAdd 104 0.05% 60.60% # Class of executed instruction -system.cpu.op_class::FloatCmp 119 0.05% 60.65% # Class of executed instruction -system.cpu.op_class::FloatCvt 43 0.02% 60.67% # Class of executed instruction -system.cpu.op_class::FloatMult 30 0.01% 60.69% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::FloatDiv 11 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::FloatSqrt 5 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.69% # Class of executed instruction -system.cpu.op_class::MemRead 51297 22.67% 83.36% # Class of executed instruction -system.cpu.op_class::MemWrite 37094 16.39% 99.76% # Class of executed instruction -system.cpu.op_class::FloatMemRead 414 0.18% 99.94% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 136 0.06% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 226275 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 246.215915 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 88644 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 299.472973 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 246.215915 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.060111 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.060111 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 296 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 278 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.072266 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 178176 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 178176 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 51622 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 51622 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 37022 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 37022 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 88644 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 88644 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 88644 # number of overall hits -system.cpu.dcache.overall_hits::total 88644 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 207 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 207 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 296 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 296 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 296 # number of overall misses -system.cpu.dcache.overall_misses::total 296 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5607000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5607000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 13041000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 13041000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18648000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18648000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18648000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18648000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 51711 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 51711 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 37229 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 37229 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 88940 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 88940 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 88940 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 88940 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001721 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.001721 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005560 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005560 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003328 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.003328 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.003328 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.003328 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 89 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 89 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 207 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 207 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 296 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 296 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 296 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5518000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5518000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12834000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12834000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18352000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18352000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18352000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18352000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001721 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001721 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005560 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005560 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003328 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003328 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003328 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003328 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 31 # number of replacements -system.cpu.icache.tags.tagsinuse 467.546782 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 225437 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 839 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 268.697259 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 467.546782 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.228294 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.228294 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 808 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 642 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.394531 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 453391 # Number of tag accesses -system.cpu.icache.tags.data_accesses 453391 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 225437 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 225437 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 225437 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 225437 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 225437 # number of overall hits -system.cpu.icache.overall_hits::total 225437 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 839 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 839 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 839 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 839 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 839 # number of overall misses -system.cpu.icache.overall_misses::total 839 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 52807500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 52807500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 52807500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 52807500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 52807500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 52807500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 226276 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 226276 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 226276 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 226276 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 226276 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 226276 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003708 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.003708 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.003708 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.003708 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.003708 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.003708 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62941.001192 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62941.001192 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62941.001192 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62941.001192 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62941.001192 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62941.001192 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 31 # number of writebacks -system.cpu.icache.writebacks::total 31 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 839 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 839 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 839 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 839 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 839 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 839 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51968500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 51968500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51968500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 51968500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51968500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 51968500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.003708 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.003708 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.003708 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.003708 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.003708 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.003708 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61941.001192 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61941.001192 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61941.001192 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 61941.001192 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61941.001192 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61941.001192 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 727.343781 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1134 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.028219 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 481.119804 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 246.223977 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.014683 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.007514 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.022197 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 1134 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 950 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.034607 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 10462 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 10462 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackClean_hits::writebacks 31 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 31 # number of WritebackClean hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits -system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 207 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 207 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 838 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 838 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 89 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 89 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 838 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 296 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1134 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 838 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 296 # number of overall misses -system.cpu.l2cache.overall_misses::total 1134 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12523500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 12523500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 50699500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 50699500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5384500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 5384500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 50699500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 17908000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 68607500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 50699500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 17908000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 68607500 # number of overall miss cycles -system.cpu.l2cache.WritebackClean_accesses::writebacks 31 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 31 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 207 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 207 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 839 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 839 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 89 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 89 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 839 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 296 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1135 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 839 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 296 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1135 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.998808 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.998808 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.998808 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.999119 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998808 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.999119 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60500.596659 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60500.596659 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60500.596659 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60500.440917 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60500.596659 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60500.440917 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 207 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 207 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 838 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 838 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 89 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 89 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 838 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 296 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1134 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 838 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 296 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1134 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10453500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10453500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 42319500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 42319500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4494500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4494500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 42319500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14948000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 57267500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 42319500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14948000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 57267500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.998808 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.998808 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998808 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.999119 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998808 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.999119 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50500.596659 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50500.596659 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50500.596659 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.440917 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50500.596659 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.440917 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1166 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 31 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 928 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 31 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 207 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 207 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 839 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 89 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1709 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 592 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2301 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 55680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 74624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1135 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1135 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1135 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 614000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1258500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 444000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 1134 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 927 # Transaction distribution -system.membus.trans_dist::ReadExReq 207 # Transaction distribution -system.membus.trans_dist::ReadExResp 207 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 927 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2268 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2268 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 72576 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1134 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1134 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1134 # Request fanout histogram -system.membus.reqLayer0.occupancy 1134500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 5670000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.5 # Layer utilization (%) +sim_seconds 0.000755 +sim_ticks 755664500 +final_tick 755664500 +sim_freq 1000000000000 +host_inst_rate 3560 +host_op_rate 3571 +host_tick_rate 6467277 +host_mem_usage 270048 +host_seconds 116.84 +sim_insts 416024 +sim_ops 417277 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 755664500 +system.physmem.bytes_read::cpu.inst 67712 +system.physmem.bytes_read::cpu.data 33920 +system.physmem.bytes_read::total 101632 +system.physmem.bytes_inst_read::cpu.inst 67712 +system.physmem.bytes_inst_read::total 67712 +system.physmem.num_reads::cpu.inst 1058 +system.physmem.num_reads::cpu.data 530 +system.physmem.num_reads::total 1588 +system.physmem.bw_read::cpu.inst 89605903 +system.physmem.bw_read::cpu.data 44887645 +system.physmem.bw_read::total 134493548 +system.physmem.bw_inst_read::cpu.inst 89605903 +system.physmem.bw_inst_read::total 89605903 +system.physmem.bw_total::cpu.inst 89605903 +system.physmem.bw_total::cpu.data 44887645 +system.physmem.bw_total::total 134493548 +system.pwrStateResidencyTicks::UNDEFINED 755664500 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 216 +system.cpu.pwrStateResidencyTicks::ON 755664500 +system.cpu.numCycles 1511329 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 416024 +system.cpu.committedOps 417277 +system.cpu.num_int_alu_accesses 415220 +system.cpu.num_fp_alu_accesses 1163 +system.cpu.num_vec_alu_accesses 0 +system.cpu.num_func_calls 23050 +system.cpu.num_conditional_control_insts 67806 +system.cpu.num_int_insts 415220 +system.cpu.num_fp_insts 1163 +system.cpu.num_vec_insts 0 +system.cpu.num_int_register_reads 525251 +system.cpu.num_int_register_writes 276296 +system.cpu.num_fp_register_reads 936 +system.cpu.num_fp_register_writes 756 +system.cpu.num_vec_register_reads 0 +system.cpu.num_vec_register_writes 0 +system.cpu.num_mem_refs 169624 +system.cpu.num_load_insts 105498 +system.cpu.num_store_insts 64126 +system.cpu.num_idle_cycles -0 +system.cpu.num_busy_cycles 1511329 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction -0 +system.cpu.Branches 90856 +system.cpu.op_class::No_OpClass 236 0.05% 0.05% +system.cpu.op_class::IntAlu 245871 58.89% 58.94% +system.cpu.op_class::IntMult 674 0.16% 59.11% +system.cpu.op_class::IntDiv 644 0.15% 59.26% +system.cpu.op_class::FloatAdd 128 0.03% 59.29% +system.cpu.op_class::FloatCmp 161 0.03% 59.33% +system.cpu.op_class::FloatCvt 109 0.02% 59.35% +system.cpu.op_class::FloatMult 30 0.00% 59.36% +system.cpu.op_class::FloatMultAcc 0 0.00% 59.36% +system.cpu.op_class::FloatDiv 11 0.00% 59.36% +system.cpu.op_class::FloatMisc 0 0.00% 59.36% +system.cpu.op_class::FloatSqrt 5 0.00% 59.37% +system.cpu.op_class::SimdAdd 0 0.00% 59.37% +system.cpu.op_class::SimdAddAcc 0 0.00% 59.37% +system.cpu.op_class::SimdAlu 0 0.00% 59.37% +system.cpu.op_class::SimdCmp 0 0.00% 59.37% +system.cpu.op_class::SimdCvt 0 0.00% 59.37% +system.cpu.op_class::SimdMisc 0 0.00% 59.37% +system.cpu.op_class::SimdMult 0 0.00% 59.37% +system.cpu.op_class::SimdMultAcc 0 0.00% 59.37% +system.cpu.op_class::SimdShift 0 0.00% 59.37% +system.cpu.op_class::SimdShiftAcc 0 0.00% 59.37% +system.cpu.op_class::SimdSqrt 0 0.00% 59.37% +system.cpu.op_class::SimdFloatAdd 0 0.00% 59.37% +system.cpu.op_class::SimdFloatAlu 0 0.00% 59.37% +system.cpu.op_class::SimdFloatCmp 0 0.00% 59.37% +system.cpu.op_class::SimdFloatCvt 0 0.00% 59.37% +system.cpu.op_class::SimdFloatDiv 0 0.00% 59.37% +system.cpu.op_class::SimdFloatMisc 0 0.00% 59.37% +system.cpu.op_class::SimdFloatMult 0 0.00% 59.37% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 59.37% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 59.37% +system.cpu.op_class::MemRead 104951 25.13% 84.50% +system.cpu.op_class::MemWrite 63954 15.31% 99.82% +system.cpu.op_class::FloatMemRead 547 0.13% 99.95% +system.cpu.op_class::FloatMemWrite 172 0.04% 99.99% +system.cpu.op_class::IprAccess 0 0.00% 99.99% +system.cpu.op_class::InstPrefetch 0 0.00% 99.99% +system.cpu.op_class::total 417493 +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 755664500 +system.cpu.dcache.tags.replacements 2 +system.cpu.dcache.tags.tagsinuse 436.556179 +system.cpu.dcache.tags.total_refs 169094 +system.cpu.dcache.tags.sampled_refs 530 +system.cpu.dcache.tags.avg_refs 319.045283 +system.cpu.dcache.tags.warmup_cycle 0 +system.cpu.dcache.tags.occ_blocks::cpu.data 436.556179 +system.cpu.dcache.tags.occ_percent::cpu.data 0.106581 +system.cpu.dcache.tags.occ_percent::total 0.106581 +system.cpu.dcache.tags.occ_task_id_blocks::1024 528 +system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 +system.cpu.dcache.tags.age_task_id_blocks_1024::1 9 +system.cpu.dcache.tags.age_task_id_blocks_1024::2 504 +system.cpu.dcache.tags.occ_task_id_percent::1024 0.128906 +system.cpu.dcache.tags.tag_accesses 339778 +system.cpu.dcache.tags.data_accesses 339778 +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 755664500 +system.cpu.dcache.ReadReq_hits::cpu.data 103506 +system.cpu.dcache.ReadReq_hits::total 103506 +system.cpu.dcache.WriteReq_hits::cpu.data 62208 +system.cpu.dcache.WriteReq_hits::total 62208 +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1689 +system.cpu.dcache.LoadLockedReq_hits::total 1689 +system.cpu.dcache.StoreCondReq_hits::cpu.data 1691 +system.cpu.dcache.StoreCondReq_hits::total 1691 +system.cpu.dcache.demand_hits::cpu.data 165714 +system.cpu.dcache.demand_hits::total 165714 +system.cpu.dcache.overall_hits::cpu.data 165714 +system.cpu.dcache.overall_hits::total 165714 +system.cpu.dcache.ReadReq_misses::cpu.data 301 +system.cpu.dcache.ReadReq_misses::total 301 +system.cpu.dcache.WriteReq_misses::cpu.data 227 +system.cpu.dcache.WriteReq_misses::total 227 +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 +system.cpu.dcache.LoadLockedReq_misses::total 2 +system.cpu.dcache.demand_misses::cpu.data 528 +system.cpu.dcache.demand_misses::total 528 +system.cpu.dcache.overall_misses::cpu.data 528 +system.cpu.dcache.overall_misses::total 528 +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18963000 +system.cpu.dcache.ReadReq_miss_latency::total 18963000 +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14301000 +system.cpu.dcache.WriteReq_miss_latency::total 14301000 +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 126000 +system.cpu.dcache.LoadLockedReq_miss_latency::total 126000 +system.cpu.dcache.demand_miss_latency::cpu.data 33264000 +system.cpu.dcache.demand_miss_latency::total 33264000 +system.cpu.dcache.overall_miss_latency::cpu.data 33264000 +system.cpu.dcache.overall_miss_latency::total 33264000 +system.cpu.dcache.ReadReq_accesses::cpu.data 103807 +system.cpu.dcache.ReadReq_accesses::total 103807 +system.cpu.dcache.WriteReq_accesses::cpu.data 62435 +system.cpu.dcache.WriteReq_accesses::total 62435 +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1691 +system.cpu.dcache.LoadLockedReq_accesses::total 1691 +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1691 +system.cpu.dcache.StoreCondReq_accesses::total 1691 +system.cpu.dcache.demand_accesses::cpu.data 166242 +system.cpu.dcache.demand_accesses::total 166242 +system.cpu.dcache.overall_accesses::cpu.data 166242 +system.cpu.dcache.overall_accesses::total 166242 +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002899 +system.cpu.dcache.ReadReq_miss_rate::total 0.002899 +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003635 +system.cpu.dcache.WriteReq_miss_rate::total 0.003635 +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001182 +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001182 +system.cpu.dcache.demand_miss_rate::cpu.data 0.003176 +system.cpu.dcache.demand_miss_rate::total 0.003176 +system.cpu.dcache.overall_miss_rate::cpu.data 0.003176 +system.cpu.dcache.overall_miss_rate::total 0.003176 +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 +system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 +system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63000 +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63000 +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 +system.cpu.dcache.demand_avg_miss_latency::total 63000 +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 +system.cpu.dcache.overall_avg_miss_latency::total 63000 +system.cpu.dcache.blocked_cycles::no_mshrs 0 +system.cpu.dcache.blocked_cycles::no_targets 0 +system.cpu.dcache.blocked::no_mshrs 0 +system.cpu.dcache.blocked::no_targets 0 +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan +system.cpu.dcache.avg_blocked_cycles::no_targets nan +system.cpu.dcache.writebacks::writebacks 2 +system.cpu.dcache.writebacks::total 2 +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 301 +system.cpu.dcache.ReadReq_mshr_misses::total 301 +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 227 +system.cpu.dcache.WriteReq_mshr_misses::total 227 +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 2 +system.cpu.dcache.LoadLockedReq_mshr_misses::total 2 +system.cpu.dcache.demand_mshr_misses::cpu.data 528 +system.cpu.dcache.demand_mshr_misses::total 528 +system.cpu.dcache.overall_mshr_misses::cpu.data 528 +system.cpu.dcache.overall_mshr_misses::total 528 +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18662000 +system.cpu.dcache.ReadReq_mshr_miss_latency::total 18662000 +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14074000 +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14074000 +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 124000 +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 124000 +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32736000 +system.cpu.dcache.demand_mshr_miss_latency::total 32736000 +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32736000 +system.cpu.dcache.overall_mshr_miss_latency::total 32736000 +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002899 +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002899 +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003635 +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003635 +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.001182 +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.001182 +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003176 +system.cpu.dcache.demand_mshr_miss_rate::total 0.003176 +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003176 +system.cpu.dcache.overall_mshr_miss_rate::total 0.003176 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 62000 +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 62000 +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 755664500 +system.cpu.icache.tags.replacements 55 +system.cpu.icache.tags.tagsinuse 692.579354 +system.cpu.icache.tags.total_refs 486513 +system.cpu.icache.tags.sampled_refs 1059 +system.cpu.icache.tags.avg_refs 459.407932 +system.cpu.icache.tags.warmup_cycle 0 +system.cpu.icache.tags.occ_blocks::cpu.inst 692.579354 +system.cpu.icache.tags.occ_percent::cpu.inst 0.338173 +system.cpu.icache.tags.occ_percent::total 0.338173 +system.cpu.icache.tags.occ_task_id_blocks::1024 1004 +system.cpu.icache.tags.age_task_id_blocks_1024::0 41 +system.cpu.icache.tags.age_task_id_blocks_1024::1 45 +system.cpu.icache.tags.age_task_id_blocks_1024::2 918 +system.cpu.icache.tags.occ_task_id_percent::1024 0.490234 +system.cpu.icache.tags.tag_accesses 976203 +system.cpu.icache.tags.data_accesses 976203 +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 755664500 +system.cpu.icache.ReadReq_hits::cpu.inst 486513 +system.cpu.icache.ReadReq_hits::total 486513 +system.cpu.icache.demand_hits::cpu.inst 486513 +system.cpu.icache.demand_hits::total 486513 +system.cpu.icache.overall_hits::cpu.inst 486513 +system.cpu.icache.overall_hits::total 486513 +system.cpu.icache.ReadReq_misses::cpu.inst 1059 +system.cpu.icache.ReadReq_misses::total 1059 +system.cpu.icache.demand_misses::cpu.inst 1059 +system.cpu.icache.demand_misses::total 1059 +system.cpu.icache.overall_misses::cpu.inst 1059 +system.cpu.icache.overall_misses::total 1059 +system.cpu.icache.ReadReq_miss_latency::cpu.inst 66668500 +system.cpu.icache.ReadReq_miss_latency::total 66668500 +system.cpu.icache.demand_miss_latency::cpu.inst 66668500 +system.cpu.icache.demand_miss_latency::total 66668500 +system.cpu.icache.overall_miss_latency::cpu.inst 66668500 +system.cpu.icache.overall_miss_latency::total 66668500 +system.cpu.icache.ReadReq_accesses::cpu.inst 487572 +system.cpu.icache.ReadReq_accesses::total 487572 +system.cpu.icache.demand_accesses::cpu.inst 487572 +system.cpu.icache.demand_accesses::total 487572 +system.cpu.icache.overall_accesses::cpu.inst 487572 +system.cpu.icache.overall_accesses::total 487572 +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002171 +system.cpu.icache.ReadReq_miss_rate::total 0.002171 +system.cpu.icache.demand_miss_rate::cpu.inst 0.002171 +system.cpu.icache.demand_miss_rate::total 0.002171 +system.cpu.icache.overall_miss_rate::cpu.inst 0.002171 +system.cpu.icache.overall_miss_rate::total 0.002171 +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62954.202077 +system.cpu.icache.ReadReq_avg_miss_latency::total 62954.202077 +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62954.202077 +system.cpu.icache.demand_avg_miss_latency::total 62954.202077 +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62954.202077 +system.cpu.icache.overall_avg_miss_latency::total 62954.202077 +system.cpu.icache.blocked_cycles::no_mshrs 0 +system.cpu.icache.blocked_cycles::no_targets 0 +system.cpu.icache.blocked::no_mshrs 0 +system.cpu.icache.blocked::no_targets 0 +system.cpu.icache.avg_blocked_cycles::no_mshrs nan +system.cpu.icache.avg_blocked_cycles::no_targets nan +system.cpu.icache.writebacks::writebacks 55 +system.cpu.icache.writebacks::total 55 +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1059 +system.cpu.icache.ReadReq_mshr_misses::total 1059 +system.cpu.icache.demand_mshr_misses::cpu.inst 1059 +system.cpu.icache.demand_mshr_misses::total 1059 +system.cpu.icache.overall_mshr_misses::cpu.inst 1059 +system.cpu.icache.overall_mshr_misses::total 1059 +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 65609500 +system.cpu.icache.ReadReq_mshr_miss_latency::total 65609500 +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 65609500 +system.cpu.icache.demand_mshr_miss_latency::total 65609500 +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 65609500 +system.cpu.icache.overall_mshr_miss_latency::total 65609500 +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002171 +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002171 +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002171 +system.cpu.icache.demand_mshr_miss_rate::total 0.002171 +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002171 +system.cpu.icache.overall_mshr_miss_rate::total 0.002171 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61954.202077 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61954.202077 +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61954.202077 +system.cpu.icache.demand_avg_mshr_miss_latency::total 61954.202077 +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61954.202077 +system.cpu.icache.overall_avg_mshr_miss_latency::total 61954.202077 +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 755664500 +system.cpu.l2cache.tags.replacements 0 +system.cpu.l2cache.tags.tagsinuse 1156.359441 +system.cpu.l2cache.tags.total_refs 58 +system.cpu.l2cache.tags.sampled_refs 1588 +system.cpu.l2cache.tags.avg_refs 0.036523 +system.cpu.l2cache.tags.warmup_cycle 0 +system.cpu.l2cache.tags.occ_blocks::cpu.inst 719.404689 +system.cpu.l2cache.tags.occ_blocks::cpu.data 436.954751 +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.021954 +system.cpu.l2cache.tags.occ_percent::cpu.data 0.013334 +system.cpu.l2cache.tags.occ_percent::total 0.035289 +system.cpu.l2cache.tags.occ_task_id_blocks::1024 1588 +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 54 +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1478 +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.048461 +system.cpu.l2cache.tags.tag_accesses 14756 +system.cpu.l2cache.tags.data_accesses 14756 +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 755664500 +system.cpu.l2cache.WritebackDirty_hits::writebacks 2 +system.cpu.l2cache.WritebackDirty_hits::total 2 +system.cpu.l2cache.WritebackClean_hits::writebacks 55 +system.cpu.l2cache.WritebackClean_hits::total 55 +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 +system.cpu.l2cache.ReadCleanReq_hits::total 1 +system.cpu.l2cache.demand_hits::cpu.inst 1 +system.cpu.l2cache.demand_hits::total 1 +system.cpu.l2cache.overall_hits::cpu.inst 1 +system.cpu.l2cache.overall_hits::total 1 +system.cpu.l2cache.ReadExReq_misses::cpu.data 227 +system.cpu.l2cache.ReadExReq_misses::total 227 +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1058 +system.cpu.l2cache.ReadCleanReq_misses::total 1058 +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 303 +system.cpu.l2cache.ReadSharedReq_misses::total 303 +system.cpu.l2cache.demand_misses::cpu.inst 1058 +system.cpu.l2cache.demand_misses::cpu.data 530 +system.cpu.l2cache.demand_misses::total 1588 +system.cpu.l2cache.overall_misses::cpu.inst 1058 +system.cpu.l2cache.overall_misses::cpu.data 530 +system.cpu.l2cache.overall_misses::total 1588 +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13733500 +system.cpu.l2cache.ReadExReq_miss_latency::total 13733500 +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 64010000 +system.cpu.l2cache.ReadCleanReq_miss_latency::total 64010000 +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18331500 +system.cpu.l2cache.ReadSharedReq_miss_latency::total 18331500 +system.cpu.l2cache.demand_miss_latency::cpu.inst 64010000 +system.cpu.l2cache.demand_miss_latency::cpu.data 32065000 +system.cpu.l2cache.demand_miss_latency::total 96075000 +system.cpu.l2cache.overall_miss_latency::cpu.inst 64010000 +system.cpu.l2cache.overall_miss_latency::cpu.data 32065000 +system.cpu.l2cache.overall_miss_latency::total 96075000 +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2 +system.cpu.l2cache.WritebackDirty_accesses::total 2 +system.cpu.l2cache.WritebackClean_accesses::writebacks 55 +system.cpu.l2cache.WritebackClean_accesses::total 55 +system.cpu.l2cache.ReadExReq_accesses::cpu.data 227 +system.cpu.l2cache.ReadExReq_accesses::total 227 +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1059 +system.cpu.l2cache.ReadCleanReq_accesses::total 1059 +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 303 +system.cpu.l2cache.ReadSharedReq_accesses::total 303 +system.cpu.l2cache.demand_accesses::cpu.inst 1059 +system.cpu.l2cache.demand_accesses::cpu.data 530 +system.cpu.l2cache.demand_accesses::total 1589 +system.cpu.l2cache.overall_accesses::cpu.inst 1059 +system.cpu.l2cache.overall_accesses::cpu.data 530 +system.cpu.l2cache.overall_accesses::total 1589 +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 +system.cpu.l2cache.ReadExReq_miss_rate::total 1 +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.999055 +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.999055 +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.999055 +system.cpu.l2cache.demand_miss_rate::cpu.data 1 +system.cpu.l2cache.demand_miss_rate::total 0.999370 +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.999055 +system.cpu.l2cache.overall_miss_rate::cpu.data 1 +system.cpu.l2cache.overall_miss_rate::total 0.999370 +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60500.945179 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60500.945179 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60500.945179 +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 +system.cpu.l2cache.demand_avg_miss_latency::total 60500.629722 +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60500.945179 +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 +system.cpu.l2cache.overall_avg_miss_latency::total 60500.629722 +system.cpu.l2cache.blocked_cycles::no_mshrs 0 +system.cpu.l2cache.blocked_cycles::no_targets 0 +system.cpu.l2cache.blocked::no_mshrs 0 +system.cpu.l2cache.blocked::no_targets 0 +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan +system.cpu.l2cache.avg_blocked_cycles::no_targets nan +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 227 +system.cpu.l2cache.ReadExReq_mshr_misses::total 227 +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1058 +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1058 +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 303 +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 303 +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1058 +system.cpu.l2cache.demand_mshr_misses::cpu.data 530 +system.cpu.l2cache.demand_mshr_misses::total 1588 +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1058 +system.cpu.l2cache.overall_mshr_misses::cpu.data 530 +system.cpu.l2cache.overall_mshr_misses::total 1588 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11463500 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11463500 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 53430000 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 53430000 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15301500 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15301500 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53430000 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26765000 +system.cpu.l2cache.demand_mshr_miss_latency::total 80195000 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53430000 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26765000 +system.cpu.l2cache.overall_mshr_miss_latency::total 80195000 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.999055 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.999055 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.999055 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 +system.cpu.l2cache.demand_mshr_miss_rate::total 0.999370 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.999055 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 +system.cpu.l2cache.overall_mshr_miss_rate::total 0.999370 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50500.945179 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50500.945179 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50500.945179 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.629722 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50500.945179 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.629722 +system.cpu.toL2Bus.snoop_filter.tot_requests 1646 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 57 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 755664500 +system.cpu.toL2Bus.trans_dist::ReadResp 1362 +system.cpu.toL2Bus.trans_dist::WritebackDirty 2 +system.cpu.toL2Bus.trans_dist::WritebackClean 55 +system.cpu.toL2Bus.trans_dist::ReadExReq 227 +system.cpu.toL2Bus.trans_dist::ReadExResp 227 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1059 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 303 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2173 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1062 +system.cpu.toL2Bus.pkt_count::total 3235 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 71296 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 34048 +system.cpu.toL2Bus.pkt_size::total 105344 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 1589 +system.cpu.toL2Bus.snoop_fanout::mean 0 +system.cpu.toL2Bus.snoop_fanout::stdev -0 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 1589 100.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 0 +system.cpu.toL2Bus.snoop_fanout::total 1589 +system.cpu.toL2Bus.reqLayer0.occupancy 880000 +system.cpu.toL2Bus.reqLayer0.utilization 0.1 +system.cpu.toL2Bus.respLayer0.occupancy 1588500 +system.cpu.toL2Bus.respLayer0.utilization 0.2 +system.cpu.toL2Bus.respLayer1.occupancy 795000 +system.cpu.toL2Bus.respLayer1.utilization 0.1 +system.membus.snoop_filter.tot_requests 1588 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 755664500 +system.membus.trans_dist::ReadResp 1361 +system.membus.trans_dist::ReadExReq 227 +system.membus.trans_dist::ReadExResp 227 +system.membus.trans_dist::ReadSharedReq 1361 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3176 +system.membus.pkt_count::total 3176 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 101632 +system.membus.pkt_size::total 101632 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 1588 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev -0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 1588 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 1588 +system.membus.reqLayer0.occupancy 1589000 +system.membus.reqLayer0.utilization 0.2 +system.membus.respLayer1.occupancy 7940000 +system.membus.respLayer1.utilization 1.0 ---------- End Simulation Statistics ---------- |