diff options
Diffstat (limited to 'tests')
64 files changed, 2889 insertions, 2828 deletions
diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini index 503c61f1c..9a2e60122 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -488,7 +488,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing +cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout index 3dbb4b0b4..d3a2b5cda 100755 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:13 +M5 compiled Feb 12 2011 02:22:23 +M5 revision 5e76f9de6972 7961 default qtip tip x86branchdetectstats.patch +M5 started Feb 12 2011 02:22:27 M5 executing on burrito -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -1067,4 +1067,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 772390499500 because target called exit() +Exiting @ tick 766217705000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt index 05b37528b..cc548bebc 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 168346 # Simulator instruction rate (inst/s) -host_mem_usage 232444 # Number of bytes of host memory used -host_seconds 9631.89 # Real time elapsed on the host -host_tick_rate 80190939 # Simulator tick rate (ticks/s) +host_inst_rate 123498 # Simulator instruction rate (inst/s) +host_mem_usage 236748 # Number of bytes of host memory used +host_seconds 13129.74 # Real time elapsed on the host +host_tick_rate 58357436 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1621493982 # Number of instructions simulated -sim_seconds 0.772390 # Number of seconds simulated -sim_ticks 772390499500 # Number of ticks simulated +sim_seconds 0.766218 # Number of seconds simulated +sim_ticks 766217705000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 126254885 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 126894033 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 169776992 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 171183773 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 5933287 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 126894073 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 126894073 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 8003535 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 180455810 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 180455810 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 107161579 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3710402 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 7534042 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1511501895 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.072770 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.173458 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 1432274296 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.132111 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.344268 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 505879323 33.47% 33.47% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 677452709 44.82% 78.29% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 153213861 10.14% 88.43% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 112394621 7.44% 95.86% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 32585093 2.16% 98.02% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 19016713 1.26% 99.27% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 5421676 0.36% 99.63% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 1827497 0.12% 99.75% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 3710402 0.25% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 536173455 37.44% 37.44% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 547306108 38.21% 75.65% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 130197340 9.09% 84.74% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 136647601 9.54% 94.28% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 42821104 2.99% 97.27% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 22915800 1.60% 98.87% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 3037283 0.21% 99.08% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 5641563 0.39% 99.47% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 7534042 0.53% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1511501895 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 1432274296 # Number of insts commited each cycle system.cpu.commit.COM:count 1621493982 # Number of instructions committed system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 0 # Number of function calls committed. @@ -44,422 +44,422 @@ system.cpu.commit.COM:loads 419042125 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 607228182 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 5933318 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 8003567 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 227874068 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 729601482 # The number of squashed insts skipped by commit system.cpu.committedInsts 1621493982 # Number of Instructions Simulated system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated -system.cpu.cpi 0.952690 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.952690 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 326327666 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 10363.748203 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7391.735933 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 326125265 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2097633000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000620 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 202401 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 1725 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1483344000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000615 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 200676 # number of ReadReq MSHR misses +system.cpu.cpi 0.945076 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.945076 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 330979138 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 10103.492713 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7153.561618 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 330761084 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2203107000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000659 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 218054 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 3264 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1536513500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000649 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 214790 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 19667.198248 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10021.451346 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 186945733 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 24393698000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.006591 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1240324 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 994745 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2461058000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001305 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 245579 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 19459.417847 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10004.386505 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 186948986 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 24072681495 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.006574 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1237071 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 986986 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2501946999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001329 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 250085 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15789.833755 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1149.728625 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles::no_targets 16007.596007 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 1113.654359 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 29234 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 29555 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 461600000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 473104500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 514513723 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 18362.010085 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 8838.897043 # average overall mshr miss latency -system.cpu.dcache.demand_hits 513070998 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 26491331000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.002804 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1442725 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 996470 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3944402000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000867 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 446255 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 519165195 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 18057.409841 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 8687.196556 # average overall mshr miss latency +system.cpu.dcache.demand_hits 517710070 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 26275788495 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.002803 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1455125 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 990250 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 4038460499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000895 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 464875 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999781 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4095.101758 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 514513723 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 18362.010085 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 8838.897043 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.999796 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4095.162912 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 519165195 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 18057.409841 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 8687.196556 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 513070998 # number of overall hits -system.cpu.dcache.overall_miss_latency 26491331000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.002804 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1442725 # number of overall misses -system.cpu.dcache.overall_mshr_hits 996470 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3944402000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000867 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 446255 # number of overall MSHR misses +system.cpu.dcache.overall_hits 517710070 # number of overall hits +system.cpu.dcache.overall_miss_latency 26275788495 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.002803 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1455125 # number of overall misses +system.cpu.dcache.overall_mshr_hits 990250 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 4038460499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000895 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 464875 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 442158 # number of replacements -system.cpu.dcache.sampled_refs 446254 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 460779 # number of replacements +system.cpu.dcache.sampled_refs 464875 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.101758 # Cycle average of tags in use -system.cpu.dcache.total_refs 513070998 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 331552000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 398281 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 176333648 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 1886463332 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 320369444 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 981528406 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 33063147 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 33270397 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 126894073 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 119630706 # Number of cache lines fetched -system.cpu.fetch.Cycles 1056772647 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 432705 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 1026147627 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 46 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 9324994 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.082144 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 119630706 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 126254885 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.664267 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 1544565042 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.230490 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.292215 # Number of instructions fetched each cycle (Total) +system.cpu.dcache.tagsinuse 4095.162912 # Cycle average of tags in use +system.cpu.dcache.total_refs 517710070 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 317835000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 411288 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 610366395 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 2477699501 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 436378814 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 330621598 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 99870091 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 54907489 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 180455810 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 168863429 # Number of cache lines fetched +system.cpu.fetch.Cycles 400342229 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 931185 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 1404767222 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 14936403 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.117758 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 168863429 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 169776992 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.916689 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1532144387 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.666939 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.038798 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 522111775 33.80% 33.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 496583342 32.15% 65.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 273451194 17.70% 83.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 224891951 14.56% 98.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8280335 0.54% 98.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1557581 0.10% 98.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 722 0.00% 98.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8665 0.00% 98.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 17679477 1.14% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1134818986 74.07% 74.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25831687 1.69% 75.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14383456 0.94% 76.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 13631087 0.89% 77.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 30570437 2.00% 79.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 20250642 1.32% 80.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 34285955 2.24% 83.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 37728615 2.46% 85.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 220643522 14.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1544565042 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 2 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 119630706 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 37171.926007 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35433.712121 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 119629787 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 34161000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000008 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 919 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 127 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 28063500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 792 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 1532144387 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 12 # number of floating regfile reads +system.cpu.icache.ReadReq_accesses 168863429 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 34706.050695 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35310.841984 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 168862206 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 42445500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000007 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 1223 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 356 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 30614500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 867 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 151047.710859 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 194766.096886 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 119630706 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 37171.926007 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35433.712121 # average overall mshr miss latency -system.cpu.icache.demand_hits 119629787 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 34161000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000008 # miss rate for demand accesses -system.cpu.icache.demand_misses 919 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 127 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 28063500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000007 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 792 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 168863429 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 34706.050695 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35310.841984 # average overall mshr miss latency +system.cpu.icache.demand_hits 168862206 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 42445500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000007 # miss rate for demand accesses +system.cpu.icache.demand_misses 1223 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 356 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 30614500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 867 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.352078 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 721.055018 # Average occupied blocks per context -system.cpu.icache.overall_accesses 119630706 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 37171.926007 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35433.712121 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.386137 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 790.808810 # Average occupied blocks per context +system.cpu.icache.overall_accesses 168863429 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 34706.050695 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35310.841984 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 119629787 # number of overall hits -system.cpu.icache.overall_miss_latency 34161000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000008 # miss rate for overall accesses -system.cpu.icache.overall_misses 919 # number of overall misses -system.cpu.icache.overall_mshr_hits 127 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 28063500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 792 # number of overall MSHR misses +system.cpu.icache.overall_hits 168862206 # number of overall hits +system.cpu.icache.overall_miss_latency 42445500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000007 # miss rate for overall accesses +system.cpu.icache.overall_misses 1223 # number of overall misses +system.cpu.icache.overall_mshr_hits 356 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 30614500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 867 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.sampled_refs 792 # Sample count of references to valid blocks. +system.cpu.icache.replacements 11 # number of replacements +system.cpu.icache.sampled_refs 867 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 721.055018 # Cycle average of tags in use -system.cpu.icache.total_refs 119629787 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 790.808810 # Cycle average of tags in use +system.cpu.icache.total_refs 168862206 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 215958 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 108586362 # Number of branches executed +system.cpu.idleCycles 291024 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 111314295 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.090888 # Inst execution rate -system.cpu.iew.EXEC:refs 624680336 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 190102881 # Number of stores executed +system.cpu.iew.EXEC:rate 1.203312 # Inst execution rate +system.cpu.iew.EXEC:refs 636104355 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 191312994 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 2506292363 # num instructions consuming a value -system.cpu.iew.WB:count 1680860111 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.529936 # average fanout of values written-back +system.cpu.iew.WB:consumers 2089450315 # num instructions consuming a value +system.cpu.iew.WB:count 1839101566 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.684612 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1328173821 # num instructions producing a value -system.cpu.iew.WB:rate 1.088090 # insts written-back per cycle -system.cpu.iew.WB:sent 1681411195 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 6122546 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 1253236 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 492554241 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 66 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 3215387 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 210212351 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 1849358863 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 434577455 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 8332046 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1685183738 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 18939 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1430463261 # num instructions producing a value +system.cpu.iew.WB:rate 1.200117 # insts written-back per cycle +system.cpu.iew.WB:sent 1842290775 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 8145736 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 1415270 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 617903270 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 78 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 633937 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 251132554 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2351086206 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 444791361 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 11969895 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1843997360 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 60905 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 33063147 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 72665 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 99870091 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 117847 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 29234 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 108234700 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 16690 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 29753 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 113796852 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 8470 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 3968261 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 13 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 73512116 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 22026294 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 3968261 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 2078 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 6120468 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 4148897019 # number of integer regfile reads -system.cpu.int_regfile_writes 1677631671 # number of integer regfile writes -system.cpu.ipc 1.049659 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.049659 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 24157467 1.43% 1.43% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1040578234 61.44% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 438214492 25.88% 88.75% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 190565591 11.25% 100.00% # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 6921754 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 21 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 198861145 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 62946497 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 6921754 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 3700861 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 4444875 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 3233304065 # number of integer regfile reads +system.cpu.int_regfile_writes 1832324218 # number of integer regfile writes +system.cpu.ipc 1.058116 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.058116 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 27128947 1.46% 1.46% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 1186880889 63.95% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 450365179 24.27% 89.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 191592240 10.32% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 1693515784 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 252744 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.000149 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 1855967255 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 4437489 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.002391 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 40 0.02% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 250833 99.24% 99.26% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 1871 0.74% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 118316 2.67% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 3486899 78.58% 81.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 832274 18.76% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1544565042 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.096435 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 0.983023 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 1532144387 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.211353 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.177271 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 454758636 29.44% 29.44% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 667103033 43.19% 72.63% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 281275831 18.21% 90.84% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 105166888 6.81% 97.65% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 33264638 2.15% 99.81% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 2679834 0.17% 99.98% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 311387 0.02% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 3979 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 816 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 466354124 30.44% 30.44% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 601647548 39.27% 69.71% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 244545222 15.96% 85.67% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 139808763 9.13% 94.79% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 60228260 3.93% 98.72% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 13792665 0.90% 99.62% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 4627487 0.30% 99.93% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 960857 0.06% 99.99% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 179461 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1544565042 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.096282 # Inst issue rate -system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 1669611057 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 4931850619 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 1680860109 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 2080058032 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 1849358797 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1693515784 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 66 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 226765112 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 1273 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 584800312 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 245580 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34276.926221 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31075.745964 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 186864 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 2012604000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.239091 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 58716 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1824643500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.239091 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 58716 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 201467 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34133.939861 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31003.577487 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 169042 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1106793000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.160944 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 32425 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1005291000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.160944 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 32425 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 398281 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 398281 # number of Writeback hits +system.cpu.iq.ISSUE:issued_per_cycle::total 1532144387 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.211123 # Inst issue rate +system.cpu.iq.fp_alu_accesses 18 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 33 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 32 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 1833275779 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 5248603279 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1839101554 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 3087460502 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 2351086128 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1855967255 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 78 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 729454588 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 86926 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 1543114171 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 250094 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34363.888228 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31092.455043 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 191260 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 2021765000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.235248 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 58834 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1829293500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235248 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 58834 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 215648 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34134.880348 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.967489 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 182552 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1129728000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.153472 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 33096 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1026173500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.153472 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 33096 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 411288 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 411288 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.844642 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 5.099303 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 447047 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34226.056330 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31050.070769 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 355906 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3119397000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.203873 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 91141 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 465742 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34281.442402 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31061.318394 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 373812 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 3151493000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.197384 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 91930 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2829934500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.203873 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 91141 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 2855467000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.197384 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 91930 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.058867 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.490866 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1928.938344 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16084.711341 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 447047 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34226.056330 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31050.070769 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.059053 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.491352 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1935.054426 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 16100.609355 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 465742 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34281.442402 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31061.318394 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 355906 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3119397000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.203873 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 91141 # number of overall misses +system.cpu.l2cache.overall_hits 373812 # number of overall hits +system.cpu.l2cache.overall_miss_latency 3151493000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.197384 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 91930 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2829934500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.203873 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 91141 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 2855467000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.197384 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 91930 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 72873 # number of replacements -system.cpu.l2cache.sampled_refs 88473 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 73661 # number of replacements +system.cpu.l2cache.sampled_refs 89262 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18013.649684 # Cycle average of tags in use -system.cpu.l2cache.total_refs 428620 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 18035.663781 # Cycle average of tags in use +system.cpu.l2cache.total_refs 455174 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 58405 # number of writebacks -system.cpu.memDep0.conflictingLoads 289036318 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 113016383 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 492554241 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 210212351 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 864820574 # number of misc regfile reads -system.cpu.numCycles 1544781000 # number of cpu cycles simulated +system.cpu.l2cache.writebacks 58542 # number of writebacks +system.cpu.memDep0.conflictingLoads 537232404 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 219207458 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 617903270 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 251132554 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 931505074 # number of misc regfile reads +system.cpu.numCycles 1532435411 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 55578139 # Number of cycles rename is blocking +system.cpu.rename.RENAME:BlockCycles 175534951 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1617994650 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 65710608 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 361165681 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 36822801 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 16 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 5668050381 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 1874385455 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 1871676358 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 968560202 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 33063147 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 126195704 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 253681708 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 32 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 5668050349 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 2169 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 67 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 186996608 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 71 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 3357159543 # The number of ROB reads -system.cpu.rob.rob_writes 3732197477 # The number of ROB writes -system.cpu.timesIdled 45108 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 318243703 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 499996104 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 107154792 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 44 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 5827367622 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 2403532061 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2403383901 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 306300874 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 99870091 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 450439326 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 785389251 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 96 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 5827367526 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 3041 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 87 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 739921776 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 87 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 3775835718 # The number of ROB reads +system.cpu.rob.rob_writes 4802062478 # The number of ROB writes +system.cpu.timesIdled 45517 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout index 1dd3bb0d2..bb6395625 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:38:48 +M5 compiled Feb 8 2011 00:58:32 +M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip +M5 started Feb 8 2011 00:58:34 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt index ce8635d17..5b839ec88 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1066510 # Simulator instruction rate (inst/s) -host_mem_usage 223440 # Number of bytes of host memory used -host_seconds 1520.37 # Real time elapsed on the host -host_tick_rate 634049597 # Simulator tick rate (ticks/s) +host_inst_rate 2470310 # Simulator instruction rate (inst/s) +host_mem_usage 224012 # Number of bytes of host memory used +host_seconds 656.39 # Real time elapsed on the host +host_tick_rate 1468620897 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1621493983 # Number of instructions simulated sim_seconds 0.963993 # Number of seconds simulated @@ -24,7 +24,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 1621493983 # Number of instructions executed system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses system.cpu.num_int_insts 1621354493 # number of integer instructions -system.cpu.num_int_register_reads 4883555465 # number of times the integer registers were read +system.cpu.num_int_register_reads 3953866002 # number of times the integer registers were read system.cpu.num_int_register_writes 1617994650 # number of times the integer registers were written system.cpu.num_load_insts 419042125 # Number of load instructions system.cpu.num_mem_refs 607228182 # number of memory refs diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout index 889c6868b..920574653 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:35 +M5 compiled Feb 8 2011 00:58:32 +M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip +M5 started Feb 8 2011 00:58:34 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt index 46400c920..120240c59 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 685934 # Simulator instruction rate (inst/s) -host_mem_usage 231240 # Number of bytes of host memory used -host_seconds 2363.92 # Real time elapsed on the host -host_tick_rate 762824620 # Simulator tick rate (ticks/s) +host_inst_rate 1667736 # Simulator instruction rate (inst/s) +host_mem_usage 231728 # Number of bytes of host memory used +host_seconds 972.27 # Real time elapsed on the host +host_tick_rate 1854683738 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1621493983 # Number of instructions simulated sim_seconds 1.803259 # Number of seconds simulated @@ -213,7 +213,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 1621493983 # Number of instructions executed system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses system.cpu.num_int_insts 1621354493 # number of integer instructions -system.cpu.num_int_register_reads 4883555465 # number of times the integer registers were read +system.cpu.num_int_register_reads 3953866002 # number of times the integer registers were read system.cpu.num_int_register_writes 1617994650 # number of times the integer registers were written system.cpu.num_load_insts 419042125 # Number of load instructions system.cpu.num_mem_refs 607228182 # number of memory refs diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout index 1d5316147..30d3a70e1 100755 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout @@ -5,13 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:04:06 -M5 revision 8e058bca28fb 7927 default qtip tip x86fsstats.patch -M5 started Feb 7 2011 01:04:09 +M5 compiled Feb 8 2011 00:58:27 +M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip +M5 started Feb 8 2011 00:58:30 M5 executing on burrito -command line: build/X86_FS/m5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-atomic +command line: build/X86_FS/m5.fast -d build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 - 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 5112051463500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 1cabd6a2d..113af673f 100644 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2329852 # Simulator instruction rate (inst/s) -host_mem_usage 370744 # Number of bytes of host memory used -host_seconds 174.53 # Real time elapsed on the host -host_tick_rate 29290692573 # Simulator tick rate (ticks/s) +host_inst_rate 1892986 # Simulator instruction rate (inst/s) +host_mem_usage 370804 # Number of bytes of host memory used +host_seconds 214.81 # Real time elapsed on the host +host_tick_rate 23798444654 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 406624453 # Number of instructions simulated sim_seconds 5.112051 # Number of seconds simulated @@ -341,7 +341,7 @@ system.cpu.num_idle_cycles 9770620811.997942 system.cpu.num_insts 406624453 # Number of instructions executed system.cpu.num_int_alu_accesses 391833833 # Number of integer alu accesses system.cpu.num_int_insts 391833833 # number of integer instructions -system.cpu.num_int_register_reads 1007515486 # number of times the integer registers were read +system.cpu.num_int_register_reads 836347867 # number of times the integer registers were read system.cpu.num_int_register_writes 419160860 # number of times the integer registers were written system.cpu.num_load_insts 29720540 # Number of load instructions system.cpu.num_mem_refs 38133606 # number of memory refs diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simout index 6d191e20f..628b3cd61 100755 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simout +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simout @@ -5,13 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:04:06 -M5 revision 8e058bca28fb 7927 default qtip tip x86fsstats.patch -M5 started Feb 7 2011 01:04:09 +M5 compiled Feb 8 2011 00:58:27 +M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip +M5 started Feb 8 2011 00:58:30 M5 executing on burrito -command line: build/X86_FS/m5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-timing +command line: build/X86_FS/m5.fast -d build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 - 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 5187506658000 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index b4552b7b7..091a2e71c 100644 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1700985 # Simulator instruction rate (inst/s) -host_mem_usage 367580 # Number of bytes of host memory used -host_seconds 155.42 # Real time elapsed on the host -host_tick_rate 33377224644 # Simulator tick rate (ticks/s) +host_inst_rate 1227876 # Simulator instruction rate (inst/s) +host_mem_usage 367348 # Number of bytes of host memory used +host_seconds 215.31 # Real time elapsed on the host +host_tick_rate 24093749418 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 264367743 # Number of instructions simulated sim_seconds 5.187507 # Number of seconds simulated @@ -395,7 +395,7 @@ system.cpu.num_idle_cycles 9771315874.126116 system.cpu.num_insts 264367743 # Number of instructions executed system.cpu.num_int_alu_accesses 249584659 # Number of integer alu accesses system.cpu.num_int_insts 249584659 # number of integer instructions -system.cpu.num_int_register_reads 660399505 # number of times the integer registers were read +system.cpu.num_int_register_reads 543556622 # number of times the integer registers were read system.cpu.num_int_register_writes 266062505 # number of times the integer registers were written system.cpu.num_load_insts 14817593 # Number of load instructions system.cpu.num_mem_refs 23178416 # number of memory refs diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini index 8e006cde5..31cbafe2a 100644 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -488,7 +488,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing +cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout index bf0cc96de..41587c0af 100755 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:24 +M5 compiled Feb 12 2011 02:22:23 +M5 revision 5e76f9de6972 7961 default qtip tip x86branchdetectstats.patch +M5 started Feb 12 2011 02:22:27 M5 executing on burrito -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -28,4 +28,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 170680631000 because target called exit() +Exiting @ tick 98622214000 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt index 3db6ff161..33b45551d 100644 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 83481 # Simulator instruction rate (inst/s) -host_mem_usage 366872 # Number of bytes of host memory used -host_seconds 3332.41 # Real time elapsed on the host -host_tick_rate 51218385 # Simulator tick rate (ticks/s) +host_inst_rate 133029 # Simulator instruction rate (inst/s) +host_mem_usage 371192 # Number of bytes of host memory used +host_seconds 2091.22 # Real time elapsed on the host +host_tick_rate 47160241 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 278192519 # Number of instructions simulated -sim_seconds 0.170681 # Number of seconds simulated -sim_ticks 170680631000 # Number of ticks simulated +sim_seconds 0.098622 # Number of seconds simulated +sim_ticks 98622214000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 50810617 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 51416767 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 44152407 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 44769192 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 4328981 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 51416803 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 51416803 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 3292099 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 50608102 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 50608102 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 29309710 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 2488105 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 11603540 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 321793097 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.864507 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.425920 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 176948364 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.572168 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 2.280995 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 183622049 57.06% 57.06% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 75902754 23.59% 80.65% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 27223254 8.46% 89.11% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 17908154 5.57% 94.67% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 5463718 1.70% 96.37% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 3630830 1.13% 97.50% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 4674698 1.45% 98.95% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 879535 0.27% 99.23% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 2488105 0.77% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 83964580 47.45% 47.45% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 36146762 20.43% 67.88% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 16087394 9.09% 76.97% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 14069173 7.95% 84.92% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 7224288 4.08% 89.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 2649535 1.50% 90.50% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 3731341 2.11% 92.61% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 1471751 0.83% 93.44% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 11603540 6.56% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 321793097 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 176948364 # Number of insts commited each cycle system.cpu.commit.COM:count 278192519 # Number of instructions committed system.cpu.commit.COM:fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 0 # Number of function calls committed. @@ -44,421 +44,430 @@ system.cpu.commit.COM:loads 90779388 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 122219139 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 4328992 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 3292117 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 111464423 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 130955012 # The number of squashed insts skipped by commit system.cpu.committedInsts 278192519 # Number of Instructions Simulated system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated -system.cpu.cpi 1.227068 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.227068 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 82779625 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 5978.815311 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2941.059048 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 80764514 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 12047976500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.024343 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 2015111 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 45360 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 5793154000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.023795 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1969751 # number of ReadReq MSHR misses +system.cpu.cpi 0.709021 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.709021 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 69458873 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 6142.707591 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3039.983703 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 67343989 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 12991114000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.030448 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 2114884 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 142693 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 5995428500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.028394 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1972191 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 20696.077989 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 15440.513442 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 31284703 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3208885500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.004932 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 155048 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 48629 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1643164000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.003385 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 106419 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 17842.235128 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17696.947420 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 31210017 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 4098968045 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.007307 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 229734 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 123609 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 1878088545 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.003376 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 106125 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3358.823529 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 53.969218 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.avg_refs 47.420176 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 85 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 285500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 114219376 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 7030.296858 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3581.748123 # average overall mshr miss latency -system.cpu.dcache.demand_hits 112049217 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 15256862000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.019000 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2170159 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 93989 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 7436318000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.018177 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2076170 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 100898624 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 7289.068857 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3788.411890 # average overall mshr miss latency +system.cpu.dcache.demand_hits 98554006 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 17090082045 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.023237 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2344618 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 266302 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 7873517045 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.020598 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2078316 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.995143 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4076.104755 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 114219376 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 7030.296858 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3581.748123 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.994974 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4075.414607 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 100898624 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 7289.068857 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3788.411890 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 112049217 # number of overall hits -system.cpu.dcache.overall_miss_latency 15256862000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.019000 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2170159 # number of overall misses -system.cpu.dcache.overall_mshr_hits 93989 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 7436318000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.018177 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2076170 # number of overall MSHR misses +system.cpu.dcache.overall_hits 98554006 # number of overall hits +system.cpu.dcache.overall_miss_latency 17090082045 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.023237 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2344618 # number of overall misses +system.cpu.dcache.overall_mshr_hits 266302 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 7873517045 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.020598 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2078316 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 2072073 # number of replacements -system.cpu.dcache.sampled_refs 2076169 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 2074218 # number of replacements +system.cpu.dcache.sampled_refs 2078314 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4076.104755 # Cycle average of tags in use -system.cpu.dcache.total_refs 112049217 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 66009760000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 1440063 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 922031 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 437195268 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 92021485 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 228705655 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 19453848 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 143926 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 51416803 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 39245397 # Number of cache lines fetched -system.cpu.fetch.Cycles 242939967 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 793923 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 249694241 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 16 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 9845420 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.150623 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 39245397 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 50810617 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.731466 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 341246945 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.321737 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.251135 # Number of instructions fetched each cycle (Total) +system.cpu.dcache.tagsinuse 4075.414607 # Cycle average of tags in use +system.cpu.dcache.total_refs 98554015 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 40655663000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 1442059 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 21837286 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 443283148 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 77587406 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 75762450 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 19022168 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 1761222 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 50608102 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 34652495 # Number of cache lines fetched +system.cpu.fetch.Cycles 82344495 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 326035 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 259681215 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 35 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 3883025 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.256576 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 34652495 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 44152407 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.316545 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 195970532 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.323843 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.188074 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 105340577 30.87% 30.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 115413940 33.82% 64.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 47580781 13.94% 78.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 58732555 17.21% 95.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7189604 2.11% 97.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6451059 1.89% 99.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 527277 0.15% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 932 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10220 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 116145210 59.27% 59.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6750085 3.44% 62.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3016102 1.54% 64.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 8362073 4.27% 68.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7646936 3.90% 72.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6348764 3.24% 75.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 9080088 4.63% 80.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8246058 4.21% 84.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 30375216 15.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 341246945 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 44 # number of floating regfile reads -system.cpu.fp_regfile_writes 31 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 39245397 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 37208.490566 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35316.192560 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 39244337 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 39441000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1060 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 146 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 32279000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 914 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 195970532 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 75 # number of floating regfile reads +system.cpu.fp_regfile_writes 41 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses 34652495 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35675.242356 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35201.684836 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 34651154 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 47840500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000039 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 1341 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 332 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 35518500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000029 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 1009 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 42936.911379 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 34376.144841 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 39245397 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 37208.490566 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35316.192560 # average overall mshr miss latency -system.cpu.icache.demand_hits 39244337 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 39441000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000027 # miss rate for demand accesses -system.cpu.icache.demand_misses 1060 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 146 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 32279000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000023 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 914 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 34652495 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35675.242356 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35201.684836 # average overall mshr miss latency +system.cpu.icache.demand_hits 34651154 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 47840500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000039 # miss rate for demand accesses +system.cpu.icache.demand_misses 1341 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 332 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 35518500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000029 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 1009 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.360466 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 738.235227 # Average occupied blocks per context -system.cpu.icache.overall_accesses 39245397 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 37208.490566 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35316.192560 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.392466 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 803.770978 # Average occupied blocks per context +system.cpu.icache.overall_accesses 34652495 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35675.242356 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35201.684836 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 39244337 # number of overall hits -system.cpu.icache.overall_miss_latency 39441000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000027 # miss rate for overall accesses -system.cpu.icache.overall_misses 1060 # number of overall misses -system.cpu.icache.overall_mshr_hits 146 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 32279000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000023 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 914 # number of overall MSHR misses +system.cpu.icache.overall_hits 34651154 # number of overall hits +system.cpu.icache.overall_miss_latency 47840500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000039 # miss rate for overall accesses +system.cpu.icache.overall_misses 1341 # number of overall misses +system.cpu.icache.overall_mshr_hits 332 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 35518500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000029 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 1009 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 37 # number of replacements -system.cpu.icache.sampled_refs 914 # Sample count of references to valid blocks. +system.cpu.icache.replacements 60 # number of replacements +system.cpu.icache.sampled_refs 1008 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 738.235227 # Cycle average of tags in use -system.cpu.icache.total_refs 39244337 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 803.770978 # Cycle average of tags in use +system.cpu.icache.total_refs 34651154 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 114318 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 31118985 # Number of branches executed +system.cpu.idleCycles 1273897 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 33755681 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.940576 # Inst execution rate -system.cpu.iew.EXEC:refs 137464023 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 32172568 # Number of stores executed +system.cpu.iew.EXEC:rate 1.719732 # Inst execution rate +system.cpu.iew.EXEC:refs 143271490 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 33964004 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 361852587 # num instructions consuming a value -system.cpu.iew.WB:count 317781549 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.623035 # average fanout of values written-back +system.cpu.iew.WB:consumers 356152066 # num instructions consuming a value +system.cpu.iew.WB:count 334303723 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.713943 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 225446782 # num instructions producing a value -system.cpu.iew.WB:rate 0.930924 # insts written-back per cycle -system.cpu.iew.WB:sent 318008427 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 5390321 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 197365 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 131280417 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 455 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 3671049 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 41039188 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 389592858 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 105291455 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 12266571 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 321076071 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 2799 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 254272214 # num instructions producing a value +system.cpu.iew.WB:rate 1.694870 # insts written-back per cycle +system.cpu.iew.WB:sent 336664522 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 3987132 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 754395 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 138835558 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 663120 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 42750154 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 409142439 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 109307486 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6572046 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 339207523 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 2275 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 1704 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 19453848 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 10507 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 78833 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 19022168 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 104797 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 22405068 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 64376 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 14565 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 39666706 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 30063 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 5520980 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 2668 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 40501029 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 9599437 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 5520980 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 16897 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 5373424 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 754340794 # number of integer regfile reads -system.cpu.int_regfile_writes 286169707 # number of integer regfile writes -system.cpu.ipc 0.814950 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.814950 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 16700 0.01% 0.01% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 193455065 58.03% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 15 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 107162338 32.15% 90.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 32708524 9.81% 100.00% # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 1469253 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 2742 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 48056170 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 11310403 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 1469253 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 865481 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 3121651 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 577634708 # number of integer regfile reads +system.cpu.int_regfile_writes 302216415 # number of integer regfile writes +system.cpu.ipc 1.410395 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.410395 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 16702 0.00% 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 200471700 57.98% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 15 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 110857049 32.06% 90.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 34434103 9.96% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 333342642 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 98152 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.000294 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 345779569 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 4109732 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011885 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 15 0.02% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 97651 99.49% 99.50% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 486 0.50% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 26819 0.65% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 3817756 92.90% 93.55% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 265157 6.45% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 341246945 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.976837 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.032280 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 195970532 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.764447 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.745109 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 143332703 42.00% 42.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 98734149 28.93% 70.94% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 68142120 19.97% 90.90% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 26890607 7.88% 98.78% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 3089152 0.91% 99.69% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 1054470 0.31% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 2951 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 576 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 217 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 63955785 32.64% 32.64% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 38956843 19.88% 52.51% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 30997952 15.82% 68.33% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 27554899 14.06% 82.39% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 19728653 10.07% 92.46% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 8783605 4.48% 96.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 3191043 1.63% 98.57% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 2230786 1.14% 99.71% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 570966 0.29% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 341246945 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.976510 # Inst issue rate -system.cpu.iq.fp_alu_accesses 55 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 110 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 49 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 110 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 333424039 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 1008030271 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 317781500 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 504991584 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 389592403 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 333342642 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 455 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 109882124 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 237362106 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 106419 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34277.831445 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31049.336758 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 63976 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 1454854000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.398829 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 42443 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1317827000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.398829 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 42443 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 1970665 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34310.495712 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31007.530164 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1936270 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1180109500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.017453 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 34395 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1066504000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017453 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 34395 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 1440063 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 1440063 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.iq.ISSUE:issued_per_cycle::total 195970532 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.753051 # Inst issue rate +system.cpu.iq.fp_alu_accesses 110 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 224 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 83 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 263 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 349872489 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 891669703 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 334303640 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 540919004 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 409141974 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 345779569 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 465 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 130872312 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 30525 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 221868127 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 106126 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34139.167845 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31050.412541 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 63706 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 1448183500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.399714 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 42420 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1317158500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.399714 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 42420 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 1973197 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34279.521718 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31013.978995 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1938824 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1178290000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.017420 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 34373 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1066043500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017420 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 34373 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 1442058 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 1442058 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2176.470588 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 42.751383 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 42.835533 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 17 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 37000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 2077084 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34292.452953 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31030.622869 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2000246 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2634963500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.036993 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 76838 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 2079323 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34201.991067 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31034.104671 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 2002530 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 2626473500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.036932 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 76793 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2384331000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.036993 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 76838 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 2383202000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.036932 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 76793 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.192442 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.349126 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 6305.950681 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 11440.167306 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 2077084 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34292.452953 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31030.622869 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.185144 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.337522 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 6066.784489 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 11059.931141 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 2079323 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34201.991067 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31034.104671 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2000246 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2634963500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.036993 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 76838 # number of overall misses +system.cpu.l2cache.overall_hits 2002530 # number of overall hits +system.cpu.l2cache.overall_miss_latency 2626473500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.036932 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 76793 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2384331000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.036993 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 76838 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 2383202000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.036932 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 76793 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 49392 # number of replacements -system.cpu.l2cache.sampled_refs 77392 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 49342 # number of replacements +system.cpu.l2cache.sampled_refs 77347 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 17746.117987 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3308615 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 17126.715630 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3313200 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 29474 # number of writebacks -system.cpu.memDep0.conflictingLoads 22358679 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3757180 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 131280417 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 41039188 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 204301939 # number of misc regfile reads -system.cpu.numCycles 341361263 # number of cpu cycles simulated +system.cpu.l2cache.writebacks 29450 # number of writebacks +system.cpu.memDep0.conflictingLoads 87882428 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 16100005 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 138835558 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42750154 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 218323859 # number of misc regfile reads +system.cpu.numCycles 197244429 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 486743 # Number of cycles rename is blocking +system.cpu.rename.RENAME:BlockCycles 6557218 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 248344192 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 12249 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 98511117 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 368076 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 1292599643 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 423407319 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 377348250 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 222275258 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 19453848 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 514692 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 129004058 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 291 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 1292599352 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 5287 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 454 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 779091 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 452 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 708961934 # The number of ROB reads -system.cpu.rob.rob_writes 799263493 # The number of ROB writes -system.cpu.timesIdled 5627 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 228138 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 83203716 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 14824029 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 13 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 1059543178 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 431467970 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 388798641 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 71280917 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 19022168 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 15900092 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 140454449 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 574 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 1059542604 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 6421 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 469 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 38067869 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 463 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 574492355 # The number of ROB reads +system.cpu.rob.rob_writes 837321831 # The number of ROB writes +system.cpu.timesIdled 40675 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 444 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout index e76d60819..2aa2852be 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:12 +M5 compiled Feb 8 2011 00:58:32 +M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip +M5 started Feb 8 2011 00:58:34 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt index bcab65c40..aacdb2309 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 722489 # Simulator instruction rate (inst/s) -host_mem_usage 358012 # Number of bytes of host memory used -host_seconds 385.05 # Real time elapsed on the host -host_tick_rate 438776725 # Simulator tick rate (ticks/s) +host_inst_rate 1568972 # Simulator instruction rate (inst/s) +host_mem_usage 358500 # Number of bytes of host memory used +host_seconds 177.31 # Real time elapsed on the host +host_tick_rate 952856596 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 278192520 # Number of instructions simulated sim_seconds 0.168950 # Number of seconds simulated @@ -24,7 +24,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 278192520 # Number of instructions executed system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses system.cpu.num_int_insts 278186228 # number of integer instructions -system.cpu.num_int_register_reads 855210512 # number of times the integer registers were read +system.cpu.num_int_register_reads 685043114 # number of times the integer registers were read system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written system.cpu.num_load_insts 90779388 # Number of load instructions system.cpu.num_mem_refs 122219139 # number of memory refs diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout index 0b92276cc..56b5fe9df 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:12 +M5 compiled Feb 8 2011 00:58:32 +M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip +M5 started Feb 8 2011 00:58:34 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt index cf6f03e98..e90dea7b7 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 424375 # Simulator instruction rate (inst/s) -host_mem_usage 365728 # Number of bytes of host memory used -host_seconds 655.54 # Real time elapsed on the host -host_tick_rate 564440982 # Simulator tick rate (ticks/s) +host_inst_rate 1018906 # Simulator instruction rate (inst/s) +host_mem_usage 366224 # Number of bytes of host memory used +host_seconds 273.03 # Real time elapsed on the host +host_tick_rate 1355197592 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 278192520 # Number of instructions simulated sim_seconds 0.370011 # Number of seconds simulated @@ -213,7 +213,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 278192520 # Number of instructions executed system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses system.cpu.num_int_insts 278186228 # number of integer instructions -system.cpu.num_int_register_reads 855210512 # number of times the integer registers were read +system.cpu.num_int_register_reads 685043114 # number of times the integer registers were read system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written system.cpu.num_load_insts 90779388 # Number of load instructions system.cpu.num_mem_refs 122219139 # number of memory refs diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini index 8363ae747..da344ea4b 100644 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini @@ -488,7 +488,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing +cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/20.parser/ref/x86/linux/o3-timing/simout index 4d3b5f29b..696087afc 100755 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/simout @@ -5,16 +5,16 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:13 +M5 compiled Feb 12 2011 02:22:23 +M5 revision 5e76f9de6972 7961 default qtip tip x86branchdetectstats.patch +M5 started Feb 12 2011 02:22:27 M5 executing on burrito -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... - Reading the dictionary files: *****************************info: Increasing stack size by one page. -******************** + Reading the dictionary files: ***********************info: Increasing stack size by one page. +************************** 58924 words stored in 3784810 bytes @@ -74,4 +74,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 817002039000 because target called exit() +Exiting @ tick 610952992000 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt index c39e8dfae..070979214 100644 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,475 +1,475 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 160923 # Simulator instruction rate (inst/s) -host_mem_usage 240360 # Number of bytes of host memory used -host_seconds 9501.35 # Real time elapsed on the host -host_tick_rate 85987979 # Simulator tick rate (ticks/s) +host_inst_rate 130186 # Simulator instruction rate (inst/s) +host_mem_usage 285488 # Number of bytes of host memory used +host_seconds 11733.03 # Real time elapsed on the host +host_tick_rate 52071207 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1528988756 # Number of instructions simulated -sim_seconds 0.817002 # Number of seconds simulated -sim_ticks 817002039000 # Number of ticks simulated +sim_insts 1527476062 # Number of instructions simulated +sim_seconds 0.610953 # Number of seconds simulated +sim_ticks 610952992000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 197674461 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 215147546 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 220273443 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 239822696 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 17901021 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 215739151 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 215739151 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 16691862 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 254901320 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 254901320 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 149758588 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 8186576 # number cycles where commit BW limit reached +system.cpu.commit.COM:branches 149616585 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 33918821 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1552269342 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.985002 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.301395 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 1083369873 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.409930 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.877801 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 694185983 44.72% 44.72% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 509617235 32.83% 77.55% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 176087126 11.34% 88.90% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 105147186 6.77% 95.67% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 31137095 2.01% 97.67% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 11224991 0.72% 98.40% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 11192282 0.72% 99.12% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 5490868 0.35% 99.47% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 8186576 0.53% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 454928288 41.99% 41.99% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 282557908 26.08% 68.07% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 120287774 11.10% 79.18% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 105365409 9.73% 88.90% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 40172301 3.71% 92.61% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 27676804 2.55% 95.16% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 11415389 1.05% 96.22% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 7047179 0.65% 96.87% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 33918821 3.13% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1552269342 # Number of insts commited each cycle -system.cpu.commit.COM:count 1528988756 # Number of instructions committed +system.cpu.commit.COM:committed_per_cycle::total 1083369873 # Number of insts commited each cycle +system.cpu.commit.COM:count 1527476062 # Number of instructions committed system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 0 # Number of function calls committed. -system.cpu.commit.COM:int_insts 1528317614 # Number of committed integer instructions. -system.cpu.commit.COM:loads 384102160 # Number of loads committed +system.cpu.commit.COM:int_insts 1526804920 # Number of committed integer instructions. +system.cpu.commit.COM:loads 383724495 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 533262345 # Number of memory references committed +system.cpu.commit.COM:refs 532790180 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 17902344 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions +system.cpu.commit.branchMispredicts 16726957 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 1527476062 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 459109010 # The number of squashed insts skipped by commit -system.cpu.committedInsts 1528988756 # Number of Instructions Simulated -system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated -system.cpu.cpi 1.068683 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.068683 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 352008034 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 14100.976079 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8499.435037 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 350035037 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 27821183500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.005605 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1972997 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 237485 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 14750871500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.004930 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1735512 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 15942.157352 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12645.445755 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 148213244 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 15096537500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.006349 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 946957 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 159966 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 9951852000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.005276 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 786991 # number of WriteReq MSHR misses +system.cpu.commit.commitSquashedInsts 841443918 # The number of squashed insts skipped by commit +system.cpu.committedInsts 1527476062 # Number of Instructions Simulated +system.cpu.committedInsts_total 1527476062 # Number of Instructions Simulated +system.cpu.cpi 0.799951 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.799951 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 320046346 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 15794.070061 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8150.695480 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 317137092 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 45948961500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.009090 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 2909254 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 1183970 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 14062264500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005391 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1725284 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 149065701 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 23554.108597 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 18051.470496 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 147419835 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 38766906500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.011041 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1645866 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 608291 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 18729754500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006961 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1037575 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 197.709284 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 185.704246 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 501168235 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 14698.081203 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9792.941178 # average overall mshr miss latency -system.cpu.dcache.demand_hits 498248281 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 42917721000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.005826 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2919954 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 397451 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 24702723500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.005033 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2522503 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 469112047 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 18597.944291 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 11868.871701 # average overall mshr miss latency +system.cpu.dcache.demand_hits 464556927 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 84715868000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.009710 # miss rate for demand accesses +system.cpu.dcache.demand_misses 4555120 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 1792261 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 32792019000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.005890 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2762859 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.997749 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4086.780222 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 501168235 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 14698.081203 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9792.941178 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.998028 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4087.922333 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 469112047 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 18597.944291 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 11868.871701 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 498248281 # number of overall hits -system.cpu.dcache.overall_miss_latency 42917721000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.005826 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2919954 # number of overall misses -system.cpu.dcache.overall_mshr_hits 397451 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 24702723500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.005033 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2522503 # number of overall MSHR misses +system.cpu.dcache.overall_hits 464556927 # number of overall hits +system.cpu.dcache.overall_miss_latency 84715868000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.009710 # miss rate for overall accesses +system.cpu.dcache.overall_misses 4555120 # number of overall misses +system.cpu.dcache.overall_mshr_hits 1792261 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 32792019000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.005890 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2762859 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 2516044 # number of replacements -system.cpu.dcache.sampled_refs 2520140 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 2504740 # number of replacements +system.cpu.dcache.sampled_refs 2508836 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4086.780222 # Cycle average of tags in use -system.cpu.dcache.total_refs 498255076 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3876881000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 2224034 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 25470243 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 2119227193 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 403203369 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 1116867689 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 71636028 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 6728041 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 215739151 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 165973622 # Number of cache lines fetched -system.cpu.fetch.Cycles 1190006834 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 2725815 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 1144873460 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 1839 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 29822694 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.132031 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 165973622 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 197674461 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.700655 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 1623905370 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.336094 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.273592 # Number of instructions fetched each cycle (Total) +system.cpu.dcache.tagsinuse 4087.922333 # Cycle average of tags in use +system.cpu.dcache.total_refs 465901497 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 2529382000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 2229751 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 215366555 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 2516935544 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 437043857 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 404205746 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 113949773 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 26753715 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 254901320 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 190461812 # Number of cache lines fetched +system.cpu.fetch.Cycles 445534669 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 3068431 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 1374706338 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 85274 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 18549281 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.208610 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 190461812 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 220273443 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.125051 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1197319646 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.144693 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.178811 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 477535637 29.41% 29.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 564706157 34.77% 64.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 259330057 15.97% 80.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 261180842 16.08% 96.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 22809127 1.40% 97.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 31399021 1.93% 99.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 502829 0.03% 99.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 12 0.00% 99.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 6441688 0.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 756027205 63.14% 63.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 34054494 2.84% 65.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 36745231 3.07% 69.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 33767076 2.82% 71.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 21459245 1.79% 73.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 40493114 3.38% 77.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 45860411 3.83% 80.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 35731624 2.98% 83.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 193181246 16.13% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1623905370 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 10 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 165973622 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 22741.617211 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 19372.661290 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 165966882 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 153278500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000041 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 6740 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 540 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 120110500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000037 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 6200 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 1197319646 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 31 # number of floating regfile reads +system.cpu.icache.ReadReq_accesses 190461812 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 6527.954910 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 3419.281975 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 190192396 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1758735500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.001415 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 269416 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 1570 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 915841000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.001406 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 267846 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 49795.025203 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 17699.832480 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 165973622 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 22741.617211 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 19372.661290 # average overall mshr miss latency -system.cpu.icache.demand_hits 165966882 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 153278500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000041 # miss rate for demand accesses -system.cpu.icache.demand_misses 6740 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 540 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 120110500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000037 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 6200 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 190461812 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 6527.954910 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 3419.281975 # average overall mshr miss latency +system.cpu.icache.demand_hits 190192396 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1758735500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.001415 # miss rate for demand accesses +system.cpu.icache.demand_misses 269416 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 1570 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 915841000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.001406 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 267846 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.436573 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 894.100654 # Average occupied blocks per context -system.cpu.icache.overall_accesses 165973622 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 22741.617211 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 19372.661290 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.466021 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 954.411836 # Average occupied blocks per context +system.cpu.icache.overall_accesses 190461812 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 6527.954910 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 3419.281975 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 165966882 # number of overall hits -system.cpu.icache.overall_miss_latency 153278500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000041 # miss rate for overall accesses -system.cpu.icache.overall_misses 6740 # number of overall misses -system.cpu.icache.overall_mshr_hits 540 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 120110500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000037 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 6200 # number of overall MSHR misses +system.cpu.icache.overall_hits 190192396 # number of overall hits +system.cpu.icache.overall_miss_latency 1758735500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.001415 # miss rate for overall accesses +system.cpu.icache.overall_misses 269416 # number of overall misses +system.cpu.icache.overall_mshr_hits 1570 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 915841000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.001406 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 267846 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 1750 # number of replacements -system.cpu.icache.sampled_refs 3333 # Sample count of references to valid blocks. +system.cpu.icache.replacements 9298 # number of replacements +system.cpu.icache.sampled_refs 10745 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 894.100654 # Cycle average of tags in use -system.cpu.icache.total_refs 165966819 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 954.411836 # Cycle average of tags in use +system.cpu.icache.total_refs 190184700 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 10098709 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 158001976 # Number of branches executed +system.cpu.icache.writebacks 3 # number of writebacks +system.cpu.idleCycles 24586339 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 175611349 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.044762 # Inst execution rate -system.cpu.iew.EXEC:refs 586795750 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 160862585 # Number of stores executed +system.cpu.iew.EXEC:rate 1.537639 # Inst execution rate +system.cpu.iew.EXEC:refs 604612823 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 164362000 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 2114014731 # num instructions consuming a value -system.cpu.iew.WB:count 1694146367 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.583880 # average fanout of values written-back +system.cpu.iew.WB:consumers 2150205320 # num instructions consuming a value +system.cpu.iew.WB:count 1865910107 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.666196 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1234331323 # num instructions producing a value -system.cpu.iew.WB:rate 1.036807 # insts written-back per cycle -system.cpu.iew.WB:sent 1697627373 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 18573506 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 6103126 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 508224738 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 579 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 12080656 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 194089353 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 1988097398 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 425933165 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 26013466 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1707144682 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 381189 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1432458045 # num instructions producing a value +system.cpu.iew.WB:rate 1.527049 # insts written-back per cycle +system.cpu.iew.WB:sent 1872952311 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 18187438 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 9702727 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 598780500 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 6555 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 2427132 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 227725972 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2368916953 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 440250823 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 24902522 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1878850199 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 999062 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 10588 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 71636028 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 847228 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 48995 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 113949773 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 1501929 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 72909425 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 277837 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 119150872 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 153037 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 11954619 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 832 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 124122578 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 44929168 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 11954619 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 280770 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 18292736 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 3876226209 # number of integer regfile reads -system.cpu.int_regfile_writes 1582892637 # number of integer regfile writes -system.cpu.ipc 0.935731 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.935731 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 1927969 0.11% 0.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1131725915 65.30% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 435582288 25.13% 90.54% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 163921976 9.46% 100.00% # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 1905759 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1230 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 215056005 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 78660287 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 1905759 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 2718790 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 15468648 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 3097184079 # number of integer regfile reads +system.cpu.int_regfile_writes 1741804464 # number of integer regfile writes +system.cpu.ipc 1.250077 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.250077 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2283854 0.12% 0.12% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 1286143659 67.56% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 446588315 23.46% 91.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 168736893 8.86% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 1733158148 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 1029171 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.000594 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 1903752721 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 12019370 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.006314 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 182 0.02% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 466697 45.35% 45.36% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 562292 54.64% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 1063366 8.85% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 7508013 62.47% 71.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 3447991 28.69% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1623905370 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.067278 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.066518 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 1197319646 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.590012 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.576110 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 608633589 37.48% 37.48% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 503635145 31.01% 68.49% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 353739534 21.78% 90.28% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 117719188 7.25% 97.53% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 32883027 2.02% 99.55% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 6737765 0.41% 99.97% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 234496 0.01% 99.98% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 322546 0.02% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 80 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 380569061 31.79% 31.79% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 297509781 24.85% 56.63% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 210374930 17.57% 74.20% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 147240855 12.30% 86.50% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 95168176 7.95% 94.45% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 42314918 3.53% 97.98% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 17818883 1.49% 99.47% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 5974413 0.50% 99.97% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 348629 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1623905370 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.060682 # Inst issue rate -system.cpu.iq.fp_alu_accesses 24 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 48 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 68 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 1732259326 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 5091250901 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 1694146357 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 2453039449 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 1988096819 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1733158148 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 579 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 452995728 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 112 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 26 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 1010995901 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 789062 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34275.179377 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.682665 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 541538 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 8483929500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.313694 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 247524 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 7673660500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.313694 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 247524 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 1734408 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34153.383782 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31001.108327 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1401925 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 11355419500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.191698 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 332483 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 10307341500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191698 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 332483 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 2863 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 24.346581 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31002.148228 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_hits 70 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_miss_latency 68000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 0.975550 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 2793 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 86589000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.975550 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 2793 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 2224034 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 2224034 # number of Writeback hits +system.cpu.iq.ISSUE:issued_per_cycle::total 1197319646 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.558019 # Inst issue rate +system.cpu.iq.fp_alu_accesses 59 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 119 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 31 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 7970 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 1913488178 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 5017400189 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1865910076 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 3209512631 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 2368910398 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1903752721 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 6555 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 838752495 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 555850 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 6002 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 1472792375 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 786848 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34255.494728 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.453653 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 539884 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 8459874000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.313865 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 246964 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 7656243000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.313865 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 246964 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 1732679 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34171.480760 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.917505 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1415970 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 10822415500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.182786 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 316709 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 9818903000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.182786 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 316709 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 256943 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 40.077896 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31003.030576 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_hits 1216 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_miss_latency 10249000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 0.995267 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 255727 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7928312000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.995267 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 255727 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 2229754 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2229754 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 5.356881 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 5.404070 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 2523470 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34205.361315 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31001.353432 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1943463 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 19839349000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.229845 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 580007 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 2519527 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34208.290090 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31002.276142 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 1955854 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 19282289500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.223722 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 563673 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 17981002000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.229845 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 580007 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 17475146000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.223722 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 563673 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.233067 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.421257 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 7637.149597 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13803.753842 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 2523470 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34205.361315 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31001.353432 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.213694 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.433705 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 7002.339473 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 14211.631717 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 2519527 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34208.290090 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31002.276142 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1943463 # number of overall hits -system.cpu.l2cache.overall_miss_latency 19839349000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.229845 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 580007 # number of overall misses +system.cpu.l2cache.overall_hits 1955854 # number of overall hits +system.cpu.l2cache.overall_miss_latency 19282289500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.223722 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 563673 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 17981002000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.229845 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 580007 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 17475146000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.223722 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 563673 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 569254 # number of replacements -system.cpu.l2cache.sampled_refs 588327 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 553099 # number of replacements +system.cpu.l2cache.sampled_refs 571950 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 21440.903439 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3151598 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 469235659000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 411363 # number of writebacks -system.cpu.memDep0.conflictingLoads 151128770 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 47539398 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 508224738 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 194089353 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 947795380 # number of misc regfile reads -system.cpu.numCycles 1634004079 # number of cpu cycles simulated +system.cpu.l2cache.tagsinuse 21213.971190 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3090858 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 329890014000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 404346 # number of writebacks +system.cpu.memDep0.conflictingLoads 432040536 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 167867809 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 598780500 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 227724252 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1024928879 # number of misc regfile reads +system.cpu.numCycles 1221905985 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 11181498 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1427299027 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 8162354 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 430755417 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1988994 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 37 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 6064799926 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 2072679155 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 1965930252 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1095363349 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 71636028 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 14962968 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 538631225 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 168 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 6064799758 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 6110 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 566 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 21122292 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 563 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 3532180532 # The number of ROB reads -system.cpu.rob.rob_writes 4048956705 # The number of ROB writes -system.cpu.timesIdled 351337 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:BlockCycles 64472267 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 1425688721 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 52544368 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 479786184 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 82632603 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 8428 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 5772028874 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 2456264739 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2290118455 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 385614091 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 113949773 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 153477395 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 864429734 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 19762 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 5772009112 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 19936 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 2550 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 360051799 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 2561 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 3418371032 # The number of ROB reads +system.cpu.rob.rob_writes 4851844016 # The number of ROB writes +system.cpu.timesIdled 625791 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 551 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini index fdc891c59..adfcd9b98 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini @@ -61,7 +61,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic +cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout index 70ab31a10..e27ac87ea 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:12 +M5 compiled Feb 11 2011 23:35:10 +M5 revision c3deaa585dd3 7949 default qtip resforflagsstats.patch tip +M5 started Feb 11 2011 23:35:13 M5 executing on burrito -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt index 836ed1519..afe5ef235 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 904614 # Simulator instruction rate (inst/s) -host_mem_usage 227300 # Number of bytes of host memory used -host_seconds 1690.21 # Real time elapsed on the host -host_tick_rate 523739013 # Simulator tick rate (ticks/s) +host_inst_rate 1866600 # Simulator instruction rate (inst/s) +host_mem_usage 231212 # Number of bytes of host memory used +host_seconds 819.13 # Real time elapsed on the host +host_tick_rate 1080693863 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1528988757 # Number of instructions simulated sim_seconds 0.885229 # Number of seconds simulated @@ -24,7 +24,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 1528988757 # Number of instructions executed system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses system.cpu.num_int_insts 1528317615 # number of integer instructions -system.cpu.num_int_register_reads 4418676175 # number of times the integer registers were read +system.cpu.num_int_register_reads 3581460239 # number of times the integer registers were read system.cpu.num_int_register_writes 1427299027 # number of times the integer registers were written system.cpu.num_load_insts 384102160 # Number of load instructions system.cpu.num_mem_refs 533262345 # number of memory refs diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini index 4c1fe374d..00b5b00f6 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini @@ -161,7 +161,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing +cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout index 9e491e500..1e739aa16 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:36:47 +M5 compiled Feb 11 2011 23:35:10 +M5 revision c3deaa585dd3 7949 default qtip resforflagsstats.patch tip +M5 started Feb 11 2011 23:35:13 M5 executing on burrito -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt index 2cd323573..dbe8c165b 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 738382 # Simulator instruction rate (inst/s) -host_mem_usage 235020 # Number of bytes of host memory used -host_seconds 2070.73 # Real time elapsed on the host -host_tick_rate 801036637 # Simulator tick rate (ticks/s) +host_inst_rate 1188316 # Simulator instruction rate (inst/s) +host_mem_usage 238940 # Number of bytes of host memory used +host_seconds 1286.69 # Real time elapsed on the host +host_tick_rate 1289149200 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1528988757 # Number of instructions simulated sim_seconds 1.658730 # Number of seconds simulated @@ -213,7 +213,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 1528988757 # Number of instructions executed system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses system.cpu.num_int_insts 1528317615 # number of integer instructions -system.cpu.num_int_register_reads 4418676175 # number of times the integer registers were read +system.cpu.num_int_register_reads 3581460239 # number of times the integer registers were read system.cpu.num_int_register_writes 1427299027 # number of times the integer registers were written system.cpu.num_load_insts 384102160 # Number of load instructions system.cpu.num_mem_refs 533262345 # number of memory refs diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout index 1ec8b66f1..55fcb321a 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:38 -M5 executing on burrito +M5 compiled Feb 18 2011 15:40:30 +M5 revision Unknown +M5 started Feb 18 2011 18:53:22 +M5 executing on m55-001.pool command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 43686968500 because halt instruction encountered +Exiting @ tick 43687852500 because target called exit() diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index d26ecb349..883ec05af 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,25 +1,25 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 27953 # Simulator instruction rate (inst/s) -host_mem_usage 1692040 # Number of bytes of host memory used -host_seconds 3160.33 # Real time elapsed on the host -host_tick_rate 13823537 # Simulator tick rate (ticks/s) +host_inst_rate 140237 # Simulator instruction rate (inst/s) +host_mem_usage 237028 # Number of bytes of host memory used +host_seconds 629.94 # Real time elapsed on the host +host_tick_rate 69352666 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 88340674 # Number of instructions simulated -sim_seconds 0.043687 # Number of seconds simulated -sim_ticks 43686968500 # Number of ticks simulated +sim_insts 88340673 # Number of instructions simulated +sim_seconds 0.043688 # Number of seconds simulated +sim_ticks 43687852500 # Number of ticks simulated system.cpu.AGEN-Unit.agens 35033051 # Number of Address Generations -system.cpu.Branch-Predictor.BTBHitPct 40.125175 # BTB Hit Percentage -system.cpu.Branch-Predictor.BTBHits 4678518 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 11659807 # Number of BTB lookups +system.cpu.Branch-Predictor.BTBHitPct 40.125186 # BTB Hit Percentage +system.cpu.Branch-Predictor.BTBHits 4678520 # Number of BTB hits +system.cpu.Branch-Predictor.BTBLookups 11659809 # Number of BTB lookups system.cpu.Branch-Predictor.RASInCorrect 1539 # Number of incorrect RAS predictions. system.cpu.Branch-Predictor.condIncorrect 753993 # Number of conditional branches incorrect -system.cpu.Branch-Predictor.condPredicted 9173158 # Number of conditional branches predicted -system.cpu.Branch-Predictor.lookups 14237669 # Number of BP lookups +system.cpu.Branch-Predictor.condPredicted 9173160 # Number of conditional branches predicted +system.cpu.Branch-Predictor.lookups 14237671 # Number of BP lookups system.cpu.Branch-Predictor.predictedNotTaken 6139595 # Number of Branches Predicted As Not Taken (False). -system.cpu.Branch-Predictor.predictedTaken 8098074 # Number of Branches Predicted As Taken (True). +system.cpu.Branch-Predictor.predictedTaken 8098076 # Number of Branches Predicted As Taken (True). system.cpu.Branch-Predictor.usedRAS 1660495 # Number of times the RAS was used to get a target. -system.cpu.Execution-Unit.executions 53620617 # Number of Instructions Executed. +system.cpu.Execution-Unit.executions 44841137 # Number of Instructions Executed. system.cpu.Execution-Unit.mispredictPct 5.481801 # Percentage of Incorrect Branches Predicts system.cpu.Execution-Unit.mispredicted 753993 # Number of Branches Incorrectly Predicted system.cpu.Execution-Unit.predicted 13000484 # Number of Branches Incorrectly Predicted @@ -27,43 +27,43 @@ system.cpu.Execution-Unit.predictedNotTakenIncorrect 550902 system.cpu.Execution-Unit.predictedTakenIncorrect 203091 # Number of Branches Incorrectly Predicted As Taken. system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed system.cpu.Mult-Div-Unit.multiplies 41101 # Number of Multipy Operations Executed -system.cpu.RegFile-Manager.regFileAccesses 145605016 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.RegFile-Manager.regFileReads 93058135 # Number of Reads from Register File +system.cpu.RegFile-Manager.regFileAccesses 145605009 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.RegFile-Manager.regFileReads 93058128 # Number of Reads from Register File system.cpu.RegFile-Manager.regFileWrites 52546881 # Number of Writes to Register File -system.cpu.RegFile-Manager.regForwards 13517269 # Number of Registers Read Through Forwarding Logic -system.cpu.activity 70.714707 # Percentage of cycles cpu is active +system.cpu.RegFile-Manager.regForwards 13517276 # Number of Registers Read Through Forwarding Logic +system.cpu.activity 70.715162 # Percentage of cycles cpu is active system.cpu.comBranches 13754477 # Number of Branches instructions committed system.cpu.comFloats 151453 # Number of Floating Point instructions committed system.cpu.comInts 30791227 # Number of Integer instructions committed system.cpu.comLoads 20276638 # Number of Load instructions committed -system.cpu.comNonSpec 4584 # Number of Non-Speculative instructions committed +system.cpu.comNonSpec 4583 # Number of Non-Speculative instructions committed system.cpu.comNops 8748916 # Number of Nop instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed -system.cpu.committedInsts 88340674 # Number of Instructions Simulated (Per-Thread) -system.cpu.committedInsts_total 88340674 # Number of Instructions Simulated (Total) +system.cpu.committedInsts 88340673 # Number of Instructions Simulated (Per-Thread) +system.cpu.committedInsts_total 88340673 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 0.989057 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 0.989057 # CPI: Total CPI of All Threads +system.cpu.cpi 0.989077 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 0.989077 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 43413.349504 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34421.543297 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34421.526841 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 20182230 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 4098567500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.004656 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 94408 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 33642 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2091659500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2091658500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 50157.670646 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49503.458051 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 50157.576620 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49503.360543 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 14405989 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 10402099000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 10402079500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.014192 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 207388 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 63810 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 7107607500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 7107593500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 143578 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -75,31 +75,31 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 2727000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 48047.908190 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 45018.532475 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 48047.843576 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 45018.459069 # average overall mshr miss latency system.cpu.dcache.demand_hits 34588219 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 14500666500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 14500647000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.008650 # miss rate for demand accesses system.cpu.dcache.demand_misses 301796 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 97452 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9199267000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 9199252000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 204344 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.994103 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4071.844776 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 4071.844772 # Average occupied blocks per context system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 48047.908190 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 45018.532475 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 48047.843576 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 45018.459069 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 34588219 # number of overall hits -system.cpu.dcache.overall_miss_latency 14500666500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 14500647000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.008650 # miss rate for overall accesses system.cpu.dcache.overall_misses 301796 # number of overall misses system.cpu.dcache.overall_mshr_hits 97452 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9199267000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 9199252000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 204344 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -107,9 +107,9 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 200248 # number of replacements system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4071.844776 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4071.844772 # Cycle average of tags in use system.cpu.dcache.total_refs 34588219 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 497786000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 497796000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 161214 # number of writebacks system.cpu.dtb.data_accesses 34987415 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations @@ -127,51 +127,51 @@ system.cpu.dtb.write_accesses 14620629 # DT system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_hits 14613377 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses -system.cpu.icache.ReadReq_accesses 11384473 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 18619.899316 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 15557.624423 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 11286741 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1819760000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 11384439 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 18620.927639 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 15557.720286 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 11286707 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1819860500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.008585 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 97732 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 9063 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 1379479000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 1379487500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.007789 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 88669 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 18115.384615 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 127.292157 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 127.291774 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 39 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 706500 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 11384473 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 18619.899316 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 15557.624423 # average overall mshr miss latency -system.cpu.icache.demand_hits 11286741 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1819760000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 11384439 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 18620.927639 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 15557.720286 # average overall mshr miss latency +system.cpu.icache.demand_hits 11286707 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1819860500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.008585 # miss rate for demand accesses system.cpu.icache.demand_misses 97732 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 9063 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1379479000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 1379487500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.007789 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 88669 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.918761 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1881.622790 # Average occupied blocks per context -system.cpu.icache.overall_accesses 11384473 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 18619.899316 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 15557.624423 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.918759 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1881.619179 # Average occupied blocks per context +system.cpu.icache.overall_accesses 11384439 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 18620.927639 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 15557.720286 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 11286741 # number of overall hits -system.cpu.icache.overall_miss_latency 1819760000 # number of overall miss cycles +system.cpu.icache.overall_hits 11286707 # number of overall hits +system.cpu.icache.overall_miss_latency 1819860500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.008585 # miss rate for overall accesses system.cpu.icache.overall_misses 97732 # number of overall misses system.cpu.icache.overall_mshr_hits 9063 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1379479000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 1379487500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.007789 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 88669 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -179,20 +179,20 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 86622 # number of replacements system.cpu.icache.sampled_refs 88668 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1881.622790 # Cycle average of tags in use -system.cpu.icache.total_refs 11286741 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1881.619179 # Cycle average of tags in use +system.cpu.icache.total_refs 11286707 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 25587714 # Number of cycles cpu's stages were not processed -system.cpu.ipc 1.011064 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 1.011064 # IPC: Total IPC of All Threads +system.cpu.idleCycles 25587834 # Number of cycles cpu's stages were not processed +system.cpu.ipc 1.011044 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 1.011044 # IPC: Total IPC of All Threads system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 11389750 # ITB accesses +system.cpu.itb.fetch_accesses 11389716 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 11384494 # ITB hits +system.cpu.itb.fetch_hits 11384460 # ITB hits system.cpu.itb.fetch_misses 5256 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations @@ -203,23 +203,23 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 143582 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52040.936228 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000.851808 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52040.829752 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000.848005 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_hits 12097 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 6842602500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 6842588500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 0.915748 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 131485 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 5259512000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 5259511500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915748 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 131485 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 149430 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52294.227145 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40025.874305 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52294.157340 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40025.851037 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 106453 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 2247449000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 2247446000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.287606 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 42977 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1720192000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1720191000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.287606 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 42977 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 161214 # number of Writeback accesses(hits+misses) @@ -233,33 +233,33 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 293012 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52103.331958 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40007.015854 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52103.234515 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40007.007257 # average overall mshr miss latency system.cpu.l2cache.demand_hits 118550 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9090051500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 9090034500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.595409 # miss rate for demand accesses system.cpu.l2cache.demand_misses 174462 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 6979704000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 6979702500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.595409 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 174462 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.093045 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::0 0.093044 # Average percentage of cache occupancy system.cpu.l2cache.occ_%::1 0.476016 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 3048.903015 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15598.107451 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::0 3048.873160 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15598.097053 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 293012 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52103.331958 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40007.015854 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52103.234515 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40007.007257 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 118550 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9090051500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 9090034500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.595409 # miss rate for overall accesses system.cpu.l2cache.overall_misses 174462 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 6979704000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 6979702500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.595409 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 174462 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -267,35 +267,35 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 148090 # number of replacements system.cpu.l2cache.sampled_refs 173435 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18647.010465 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 18646.970214 # Cycle average of tags in use system.cpu.l2cache.total_refs 134496 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 120516 # number of writebacks -system.cpu.numCycles 87373938 # number of cpu cycles simulated +system.cpu.numCycles 87375706 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.runCycles 61786224 # Number of cycles cpu stages are processed. +system.cpu.runCycles 61787872 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 42492197 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 44881741 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 51.367424 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 48180975 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 39192963 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 44.856583 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 46081271 # Number of cycles 0 instructions are processed. -system.cpu.stage-2.runCycles 41292667 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 47.259707 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 63475501 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.idleCycles 42493951 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.runCycles 44881755 # Number of cycles 1+ instructions are processed. +system.cpu.stage-0.utilization 51.366400 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 48181868 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.runCycles 39193838 # Number of cycles 1+ instructions are processed. +system.cpu.stage-1.utilization 44.856677 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 46079607 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.runCycles 41296099 # Number of cycles 1+ instructions are processed. +system.cpu.stage-2.utilization 47.262678 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 63477269 # Number of cycles 0 instructions are processed. system.cpu.stage-3.runCycles 23898437 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 27.351906 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 39335442 # Number of cycles 0 instructions are processed. -system.cpu.stage-4.runCycles 48038496 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 54.980349 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 69006043 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) -system.cpu.timesIdled 289198 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.stage-3.utilization 27.351352 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 39338499 # Number of cycles 0 instructions are processed. +system.cpu.stage-4.runCycles 48037207 # Number of cycles 1+ instructions are processed. +system.cpu.stage-4.utilization 54.977761 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 69007682 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.timesIdled 289197 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout index 228e6ab0c..403cb4d0b 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:13 +M5 compiled Feb 8 2011 00:58:32 +M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip +M5 started Feb 8 2011 00:58:34 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index a0361e843..9e70ccdd1 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1421831 # Simulator instruction rate (inst/s) -host_mem_usage 223380 # Number of bytes of host memory used -host_seconds 3296.36 # Real time elapsed on the host -host_tick_rate 863379215 # Simulator tick rate (ticks/s) +host_inst_rate 2540540 # Simulator instruction rate (inst/s) +host_mem_usage 223860 # Number of bytes of host memory used +host_seconds 1844.83 # Real time elapsed on the host +host_tick_rate 1542694185 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4686862651 # Number of instructions simulated sim_seconds 2.846007 # Number of seconds simulated @@ -24,7 +24,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 4686862651 # Number of instructions executed system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses system.cpu.num_int_insts 4686862580 # number of integer instructions -system.cpu.num_int_register_reads 14008880122 # number of times the integer registers were read +system.cpu.num_int_register_reads 11558008181 # number of times the integer registers were read system.cpu.num_int_register_writes 4679057393 # number of times the integer registers were written system.cpu.num_load_insts 1239184749 # Number of load instructions system.cpu.num_mem_refs 1677713086 # number of memory refs diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout index 2ae184132..65c0a8840 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:12 +M5 compiled Feb 8 2011 00:58:32 +M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip +M5 started Feb 8 2011 00:58:34 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 21d2dce98..59534c87e 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 980837 # Simulator instruction rate (inst/s) -host_mem_usage 231100 # Number of bytes of host memory used -host_seconds 4778.43 # Real time elapsed on the host -host_tick_rate 1239642391 # Simulator tick rate (ticks/s) +host_inst_rate 1546064 # Simulator instruction rate (inst/s) +host_mem_usage 231584 # Number of bytes of host memory used +host_seconds 3031.48 # Real time elapsed on the host +host_tick_rate 1954011316 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4686862651 # Number of instructions simulated sim_seconds 5.923548 # Number of seconds simulated @@ -213,7 +213,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 4686862651 # Number of instructions executed system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses system.cpu.num_int_insts 4686862580 # number of integer instructions -system.cpu.num_int_register_reads 14008880122 # number of times the integer registers were read +system.cpu.num_int_register_reads 11558008181 # number of times the integer registers were read system.cpu.num_int_register_writes 4679057393 # number of times the integer registers were written system.cpu.num_load_insts 1239184749 # Number of load instructions system.cpu.num_mem_refs 1677713086 # number of memory refs diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout index 2bd9f8140..d80de6314 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:37 -M5 executing on burrito +M5 compiled Feb 18 2011 15:40:30 +M5 revision Unknown +M5 started Feb 18 2011 19:04:15 +M5 executing on m55-001.pool command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sav Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2 @@ -28,4 +28,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 40531473000 because halt instruction encountered +122 123 124 Exiting @ tick 40531279000 because target called exit() diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index bb16b8b96..b78683303 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,25 +1,25 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 25888 # Simulator instruction rate (inst/s) -host_mem_usage 1480704 # Number of bytes of host memory used -host_seconds 3550.03 # Real time elapsed on the host -host_tick_rate 11417230 # Simulator tick rate (ticks/s) +host_inst_rate 137731 # Simulator instruction rate (inst/s) +host_mem_usage 254052 # Number of bytes of host memory used +host_seconds 667.27 # Real time elapsed on the host +host_tick_rate 60742348 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 91903057 # Number of instructions simulated +sim_insts 91903056 # Number of instructions simulated sim_seconds 0.040531 # Number of seconds simulated -sim_ticks 40531473000 # Number of ticks simulated +sim_ticks 40531279000 # Number of ticks simulated system.cpu.AGEN-Unit.agens 27308571 # Number of Address Generations -system.cpu.Branch-Predictor.BTBHitPct 59.146475 # BTB Hit Percentage +system.cpu.Branch-Predictor.BTBHitPct 59.146483 # BTB Hit Percentage system.cpu.Branch-Predictor.BTBHits 4489525 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 7590520 # Number of BTB lookups +system.cpu.Branch-Predictor.BTBLookups 7590519 # Number of BTB lookups system.cpu.Branch-Predictor.RASInCorrect 138 # Number of incorrect RAS predictions. system.cpu.Branch-Predictor.condIncorrect 2806970 # Number of conditional branches incorrect system.cpu.Branch-Predictor.condPredicted 7883251 # Number of conditional branches predicted -system.cpu.Branch-Predictor.lookups 11539981 # Number of BP lookups +system.cpu.Branch-Predictor.lookups 11539980 # Number of BP lookups system.cpu.Branch-Predictor.predictedNotTaken 4913265 # Number of Branches Predicted As Not Taken (False). -system.cpu.Branch-Predictor.predictedTaken 6626716 # Number of Branches Predicted As Taken (True). +system.cpu.Branch-Predictor.predictedTaken 6626715 # Number of Branches Predicted As Taken (True). system.cpu.Branch-Predictor.usedRAS 1029619 # Number of times the RAS was used to get a target. -system.cpu.Execution-Unit.executions 66407277 # Number of Instructions Executed. +system.cpu.Execution-Unit.executions 57928840 # Number of Instructions Executed. system.cpu.Execution-Unit.mispredictPct 27.409983 # Percentage of Incorrect Branches Predicts system.cpu.Execution-Unit.mispredicted 2806970 # Number of Branches Incorrectly Predicted system.cpu.Execution-Unit.predicted 7433715 # Number of Branches Incorrectly Predicted @@ -27,43 +27,43 @@ system.cpu.Execution-Unit.predictedNotTakenIncorrect 1384945 system.cpu.Execution-Unit.predictedTakenIncorrect 1422025 # Number of Branches Incorrectly Predicted As Taken. system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed system.cpu.Mult-Div-Unit.multiplies 458252 # Number of Multipy Operations Executed -system.cpu.RegFile-Manager.regFileAccesses 152685933 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.RegFile-Manager.regFileReads 84258572 # Number of Reads from Register File +system.cpu.RegFile-Manager.regFileAccesses 152685930 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.RegFile-Manager.regFileReads 84258569 # Number of Reads from Register File system.cpu.RegFile-Manager.regFileWrites 68427361 # Number of Writes to Register File -system.cpu.RegFile-Manager.regForwards 38185925 # Number of Registers Read Through Forwarding Logic -system.cpu.activity 91.670105 # Percentage of cycles cpu is active +system.cpu.RegFile-Manager.regForwards 38185928 # Number of Registers Read Through Forwarding Logic +system.cpu.activity 91.670040 # Percentage of cycles cpu is active system.cpu.comBranches 10240685 # Number of Branches instructions committed system.cpu.comFloats 3775974 # Number of Floating Point instructions committed system.cpu.comInts 43665352 # Number of Integer instructions committed system.cpu.comLoads 19996198 # Number of Load instructions committed -system.cpu.comNonSpec 390 # Number of Non-Speculative instructions committed +system.cpu.comNonSpec 389 # Number of Non-Speculative instructions committed system.cpu.comNops 7723346 # Number of Nop instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed -system.cpu.committedInsts 91903057 # Number of Instructions Simulated (Per-Thread) -system.cpu.committedInsts_total 91903057 # Number of Instructions Simulated (Total) +system.cpu.committedInsts 91903056 # Number of Instructions Simulated (Per-Thread) +system.cpu.committedInsts_total 91903056 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 0.882048 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 0.882048 # CPI: Total CPI of All Threads +system.cpu.cpi 0.882044 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 0.882044 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 51751.953125 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48809.473684 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 51752.929688 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48810.526316 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 19995686 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 26497000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 26497500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 512 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 37 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 23184500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 23185000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55922.090261 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52793.478261 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 55921.258907 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52792.620137 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 6496893 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 235432000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 235428500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000648 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 4210 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 2462 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 92283000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 92281500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -75,31 +75,31 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 1373500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 55469.927997 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 51942.195232 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 55469.292673 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 51941.745389 # average overall mshr miss latency system.cpu.dcache.demand_hits 26492579 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 261929000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 261926000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000178 # miss rate for demand accesses system.cpu.dcache.demand_misses 4722 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 2499 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 115467500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 115466500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.351931 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 1441.507978 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 1441.508051 # Average occupied blocks per context system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 55469.927997 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 51942.195232 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 55469.292673 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 51941.745389 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 26492579 # number of overall hits -system.cpu.dcache.overall_miss_latency 261929000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 261926000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000178 # miss rate for overall accesses system.cpu.dcache.overall_misses 4722 # number of overall misses system.cpu.dcache.overall_mshr_hits 2499 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 115467500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 115466500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -107,7 +107,7 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1441.507978 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1441.508051 # Cycle average of tags in use system.cpu.dcache.total_refs 26492579 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 107 # number of writebacks @@ -127,51 +127,51 @@ system.cpu.dtb.write_accesses 6501126 # DT system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_hits 6501103 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses -system.cpu.icache.ReadReq_accesses 9759566 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26777.900606 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23139.891881 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 9749163 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 278570500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 9759564 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 26779.967317 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 23139.993880 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 9749161 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 278592000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.001066 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 10403 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 599 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 226863500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 226864500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.001005 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 9804 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 18409.090909 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 994.406671 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 994.406467 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 11 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 202500 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 9759566 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26777.900606 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23139.891881 # average overall mshr miss latency -system.cpu.icache.demand_hits 9749163 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 278570500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 9759564 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 26779.967317 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 23139.993880 # average overall mshr miss latency +system.cpu.icache.demand_hits 9749161 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 278592000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.001066 # miss rate for demand accesses system.cpu.icache.demand_misses 10403 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 599 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 226863500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 226864500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.001005 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 9804 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.occ_%::0 0.729171 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1493.341258 # Average occupied blocks per context -system.cpu.icache.overall_accesses 9759566 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26777.900606 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23139.891881 # average overall mshr miss latency +system.cpu.icache.occ_blocks::0 1493.341252 # Average occupied blocks per context +system.cpu.icache.overall_accesses 9759564 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 26779.967317 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 23139.993880 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 9749163 # number of overall hits -system.cpu.icache.overall_miss_latency 278570500 # number of overall miss cycles +system.cpu.icache.overall_hits 9749161 # number of overall hits +system.cpu.icache.overall_miss_latency 278592000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.001066 # miss rate for overall accesses system.cpu.icache.overall_misses 10403 # number of overall misses system.cpu.icache.overall_mshr_hits 599 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 226863500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 226864500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.001005 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 9804 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -179,20 +179,20 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 7919 # number of replacements system.cpu.icache.sampled_refs 9804 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1493.341258 # Cycle average of tags in use -system.cpu.icache.total_refs 9749163 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1493.341252 # Cycle average of tags in use +system.cpu.icache.total_refs 9749161 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 6752458 # Number of cycles cpu's stages were not processed -system.cpu.ipc 1.133725 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 1.133725 # IPC: Total IPC of All Threads +system.cpu.idleCycles 6752479 # Number of cycles cpu's stages were not processed +system.cpu.ipc 1.133730 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 1.133730 # IPC: Total IPC of All Threads system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 9759621 # ITB accesses +system.cpu.itb.fetch_accesses 9759619 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 9759574 # ITB hits +system.cpu.itb.fetch_hits 9759572 # ITB hits system.cpu.itb.fetch_misses 47 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations @@ -203,23 +203,23 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52356.562137 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52355.691057 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40114.401858 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_hits 26 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 90158000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 90156500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 0.985126 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 1722 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 69077000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985126 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 1722 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 10279 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52322.450249 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40125.777363 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52322.761194 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40125.621891 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 7063 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 168269000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 168270000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.312871 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 3216 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 129044500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 129044000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.312871 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 3216 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses) @@ -233,14 +233,14 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 12027 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52334.345889 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40121.810450 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52334.244633 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40121.709194 # average overall mshr miss latency system.cpu.l2cache.demand_hits 7089 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 258427000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 258426500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.410576 # miss rate for demand accesses system.cpu.l2cache.demand_misses 4938 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 198121500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 198121000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.410576 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 4938 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed @@ -248,18 +248,18 @@ system.cpu.l2cache.mshr_cap_events 0 # nu system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.occ_%::0 0.066327 # Average percentage of cache occupancy system.cpu.l2cache.occ_%::1 0.000542 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2173.408404 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 17.762794 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::0 2173.408531 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 17.762817 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 12027 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52334.345889 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40121.810450 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52334.244633 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40121.709194 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 7089 # number of overall hits -system.cpu.l2cache.overall_miss_latency 258427000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 258426500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.410576 # miss rate for overall accesses system.cpu.l2cache.overall_misses 4938 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 198121500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 198121000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.410576 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 4938 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -267,35 +267,35 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2191.171198 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2191.171348 # Cycle average of tags in use system.cpu.l2cache.total_refs 7072 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 81062947 # number of cpu cycles simulated +system.cpu.numCycles 81062559 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.runCycles 74310489 # Number of cycles cpu stages are processed. +system.cpu.runCycles 74310080 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 27951481 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 53111466 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 65.518795 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 33263015 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 47799932 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 58.966438 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 32674388 # Number of cycles 0 instructions are processed. -system.cpu.stage-2.runCycles 48388559 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 59.692573 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 63236669 # Number of cycles 0 instructions are processed. -system.cpu.stage-3.runCycles 17826278 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 21.990661 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 26883449 # Number of cycles 0 instructions are processed. -system.cpu.stage-4.runCycles 54179498 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 66.836329 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 80608290 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) -system.cpu.timesIdled 10787 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.stage-0.idleCycles 27951091 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.runCycles 53111468 # Number of cycles 1+ instructions are processed. +system.cpu.stage-0.utilization 65.519111 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 33262621 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.runCycles 47799938 # Number of cycles 1+ instructions are processed. +system.cpu.stage-1.utilization 58.966727 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 32674404 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.runCycles 48388155 # Number of cycles 1+ instructions are processed. +system.cpu.stage-2.utilization 59.692361 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 63236282 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.runCycles 17826277 # Number of cycles 1+ instructions are processed. +system.cpu.stage-3.utilization 21.990765 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 26883065 # Number of cycles 0 instructions are processed. +system.cpu.stage-4.runCycles 54179494 # Number of cycles 1+ instructions are processed. +system.cpu.stage-4.utilization 66.836644 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 80607865 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.timesIdled 10786 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini index 78a8cbd6c..f69fd4da6 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -488,7 +488,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing +cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout index e89403a2f..2ac976df6 100755 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout @@ -5,13 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:12 +M5 compiled Feb 12 2011 02:22:23 +M5 revision 5e76f9de6972 7961 default qtip tip x86branchdetectstats.patch +M5 started Feb 12 2011 02:22:27 M5 executing on burrito -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sav -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sv2 +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -29,4 +27,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 127560542500 because target called exit() +122 123 124 Exiting @ tick 108875474000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt index 58c1a1259..a77afc849 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 87424 # Simulator instruction rate (inst/s) -host_mem_usage 240332 # Number of bytes of host memory used -host_seconds 2532.06 # Real time elapsed on the host -host_tick_rate 50378144 # Simulator tick rate (ticks/s) +host_inst_rate 92938 # Simulator instruction rate (inst/s) +host_mem_usage 245208 # Number of bytes of host memory used +host_seconds 2381.84 # Real time elapsed on the host +host_tick_rate 45710653 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 221363017 # Number of instructions simulated -sim_seconds 0.127561 # Number of seconds simulated -sim_ticks 127560542500 # Number of ticks simulated +sim_seconds 0.108875 # Number of seconds simulated +sim_ticks 108875474000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 16939138 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 19067543 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 19725800 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 22620341 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 3582609 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 19223942 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 19223942 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 3050205 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 25317132 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 25317132 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 12326943 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 324452 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 2257656 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 243992167 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.907255 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.057266 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 193712128 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.142742 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.492040 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 97637775 40.02% 40.02% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 102801930 42.13% 82.15% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 24473335 10.03% 92.18% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 10688182 4.38% 96.56% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 6438517 2.64% 99.20% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 836047 0.34% 99.54% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 523551 0.21% 99.76% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 268378 0.11% 99.87% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 324452 0.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 76077426 39.27% 39.27% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 72463860 37.41% 76.68% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 18818378 9.71% 86.40% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 12600057 6.50% 92.90% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 5960288 3.08% 95.98% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 2688234 1.39% 97.37% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 1804943 0.93% 98.30% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 1041286 0.54% 98.83% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 2257656 1.17% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 243992167 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 193712128 # Number of insts commited each cycle system.cpu.commit.COM:count 221363017 # Number of instructions committed system.cpu.commit.COM:fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 0 # Number of function calls committed. @@ -44,423 +44,424 @@ system.cpu.commit.COM:loads 56649590 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 77165306 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 3582617 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 3050238 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 70151117 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 180173936 # The number of squashed insts skipped by commit system.cpu.committedInsts 221363017 # Number of Instructions Simulated system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated -system.cpu.cpi 1.152501 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.152501 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 51727133 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 34247.563353 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34193.055556 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 51726620 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 17569000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 513 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 153 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 12309500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 360 # number of ReadReq MSHR misses +system.cpu.cpi 0.983683 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.983683 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 50495037 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 33300.295858 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34031.250000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 50494361 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 22511000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 676 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 292 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 13068000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 384 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 26394.870828 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35294.285714 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 20510427 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 139972000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000258 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 5303 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 3728 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 55588500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000077 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1575 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 26250.708416 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35437.100894 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 20508672 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 185277500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000344 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 7058 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 5492 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 55494500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000076 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1566 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 37331.807235 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 36411.811795 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 72242863 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 27087.517194 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35089.405685 # average overall mshr miss latency -system.cpu.dcache.demand_hits 72237047 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 157541000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000081 # miss rate for demand accesses -system.cpu.dcache.demand_misses 5816 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 3881 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 67898000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_accesses 71010767 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 26866.886475 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35160.256410 # average overall mshr miss latency +system.cpu.dcache.demand_hits 71003033 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 207788500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000109 # miss rate for demand accesses +system.cpu.dcache.demand_misses 7734 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 5784 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 68562500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000027 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1935 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1950 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.336997 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 1380.340507 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 72242863 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 27087.517194 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35089.405685 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.340706 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 1395.531138 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 71010767 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 26866.886475 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35160.256410 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 72237047 # number of overall hits -system.cpu.dcache.overall_miss_latency 157541000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000081 # miss rate for overall accesses -system.cpu.dcache.overall_misses 5816 # number of overall misses -system.cpu.dcache.overall_mshr_hits 3881 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 67898000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_hits 71003033 # number of overall hits +system.cpu.dcache.overall_miss_latency 207788500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000109 # miss rate for overall accesses +system.cpu.dcache.overall_misses 7734 # number of overall misses +system.cpu.dcache.overall_mshr_hits 5784 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 68562500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1935 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 1950 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 46 # number of replacements -system.cpu.dcache.sampled_refs 1935 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 48 # number of replacements +system.cpu.dcache.sampled_refs 1950 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1380.340507 # Cycle average of tags in use -system.cpu.dcache.total_refs 72237047 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1395.531138 # Cycle average of tags in use +system.cpu.dcache.total_refs 71003033 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 9 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 5656231 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 309852988 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 53029625 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 184220573 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 11003980 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 1085738 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 19223942 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 20440935 # Number of cache lines fetched -system.cpu.fetch.Cycles 196264127 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 182297 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 184675827 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 11 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 4455378 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.075352 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 20440935 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 16939138 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.723875 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 254996147 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.239017 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.348981 # Number of instructions fetched each cycle (Total) +system.cpu.dcache.writebacks 10 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 58788191 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 426377378 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 67892396 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 61042516 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 23949638 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 5989025 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 25317132 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 27858568 # Number of cache lines fetched +system.cpu.fetch.Cycles 70494302 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 451015 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 267008364 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 3227425 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.116266 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 27858568 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 19725800 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.226210 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 217661766 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.006543 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.224025 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 66307953 26.00% 26.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 121646972 47.71% 73.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 37731127 14.80% 88.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 20479784 8.03% 96.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1948325 0.76% 97.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1108960 0.43% 97.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1062530 0.42% 98.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1340 0.00% 98.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4709156 1.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 148998369 68.45% 68.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3780164 1.74% 70.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3170889 1.46% 71.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4293321 1.97% 73.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4655999 2.14% 75.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4463846 2.05% 77.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5161555 2.37% 80.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3267808 1.50% 81.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 39869815 18.32% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 254996147 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 3212472 # number of floating regfile reads -system.cpu.fp_regfile_writes 2049220 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 20440935 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 25661.556820 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 22374.875175 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 20435488 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 139778500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000266 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 5447 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 440 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 112031000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000245 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 5007 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 217661766 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 3513078 # number of floating regfile reads +system.cpu.fp_regfile_writes 2177890 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses 27858568 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 25516.664059 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 22464.816190 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 27852177 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 163077000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000229 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 6391 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 1005 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 120995500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000193 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 5386 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4082.198961 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5171.217416 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 20440935 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 25661.556820 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 22374.875175 # average overall mshr miss latency -system.cpu.icache.demand_hits 20435488 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 139778500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000266 # miss rate for demand accesses -system.cpu.icache.demand_misses 5447 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 440 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 112031000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000245 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 5007 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 27858568 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 25516.664059 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 22464.816190 # average overall mshr miss latency +system.cpu.icache.demand_hits 27852177 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 163077000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000229 # miss rate for demand accesses +system.cpu.icache.demand_misses 6391 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 1005 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 120995500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000193 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 5386 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.746987 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1529.828433 # Average occupied blocks per context -system.cpu.icache.overall_accesses 20440935 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 25661.556820 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 22374.875175 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.783470 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1604.546925 # Average occupied blocks per context +system.cpu.icache.overall_accesses 27858568 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 25516.664059 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 22464.816190 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 20435488 # number of overall hits -system.cpu.icache.overall_miss_latency 139778500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000266 # miss rate for overall accesses -system.cpu.icache.overall_misses 5447 # number of overall misses -system.cpu.icache.overall_mshr_hits 440 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 112031000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000245 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 5007 # number of overall MSHR misses +system.cpu.icache.overall_hits 27852177 # number of overall hits +system.cpu.icache.overall_miss_latency 163077000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000229 # miss rate for overall accesses +system.cpu.icache.overall_misses 6391 # number of overall misses +system.cpu.icache.overall_mshr_hits 1005 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 120995500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000193 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 5386 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 3101 # number of replacements -system.cpu.icache.sampled_refs 5006 # Sample count of references to valid blocks. +system.cpu.icache.replacements 3428 # number of replacements +system.cpu.icache.sampled_refs 5386 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1529.828433 # Cycle average of tags in use -system.cpu.icache.total_refs 20435488 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1604.546925 # Cycle average of tags in use +system.cpu.icache.total_refs 27852177 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 124939 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 13366188 # Number of branches executed +system.cpu.idleCycles 89183 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 15799905 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.954963 # Inst execution rate -system.cpu.iew.EXEC:refs 84717237 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 21535662 # Number of stores executed +system.cpu.iew.EXEC:rate 1.276995 # Inst execution rate +system.cpu.iew.EXEC:refs 89573185 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 22888685 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 389337537 # num instructions consuming a value -system.cpu.iew.WB:count 241459353 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.499412 # average fanout of values written-back +system.cpu.iew.WB:consumers 372933305 # num instructions consuming a value +system.cpu.iew.WB:count 276026292 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.598611 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 194439848 # num instructions producing a value -system.cpu.iew.WB:rate 0.946450 # insts written-back per cycle -system.cpu.iew.WB:sent 242120517 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 3656523 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 214895 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 75869162 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 1275 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 2489008 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 25600521 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 291514094 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 63181575 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4005104 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 243631219 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 25200 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 223241922 # num instructions producing a value +system.cpu.iew.WB:rate 1.267624 # insts written-back per cycle +system.cpu.iew.WB:sent 277033647 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 3251135 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 619969 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 106923422 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 1424 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 171683 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 37463806 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 401512728 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 66684500 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3440679 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 278066855 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 560615 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 11003980 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 40028 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 30447 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 23949638 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 623802 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 11103688 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 71380 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 15985064 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 21414 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 879354 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 44904 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 19219572 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 5084805 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 879354 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 151398 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 3505125 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 614135119 # number of integer regfile reads -system.cpu.int_regfile_writes 252115460 # number of integer regfile writes -system.cpu.ipc 0.867678 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.867678 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 1180294 0.48% 0.48% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 158353329 63.95% 64.42% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 64.42% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 64.42% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 1520272 0.61% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 64587764 26.08% 91.12% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 21994664 8.88% 100.00% # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 187512 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 45117 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 50273832 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 16948090 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 187512 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 737658 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 2513477 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 514946932 # number of integer regfile reads +system.cpu.int_regfile_writes 284476955 # number of integer regfile writes +system.cpu.ipc 1.016588 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.016588 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 1195391 0.42% 0.42% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 187555358 66.63% 67.05% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 67.05% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.05% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 1589850 0.56% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 67998663 24.16% 91.77% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 23168272 8.23% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 247636323 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 40899 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.000165 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 281507534 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 2779468 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.009874 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 37912 92.70% 92.70% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 2987 7.30% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 58461 2.10% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 2334735 84.00% 86.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 386272 13.90% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 254996147 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.971138 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 0.960460 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 217661766 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.293326 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.357747 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 97493255 38.23% 38.23% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 86911390 34.08% 72.32% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 54912481 21.53% 93.85% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 12234045 4.80% 98.65% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 3109625 1.22% 99.87% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 255105 0.10% 99.97% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 77911 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 2335 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 75328501 34.61% 34.61% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 67045740 30.80% 65.41% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 37681009 17.31% 82.72% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 20059185 9.22% 91.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 11722195 5.39% 97.32% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 3737927 1.72% 99.04% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 1378220 0.63% 99.67% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 597426 0.27% 99.95% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 111563 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 7 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 254996147 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.970662 # Inst issue rate -system.cpu.iq.fp_alu_accesses 2542426 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 5084249 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 2387245 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 3193021 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 243954502 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 745226741 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 239072108 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 358869082 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 291512819 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 247636323 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 1275 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 69673728 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 1298 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 29 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 182988092 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 1575 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34364.012739 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31058.917197 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 5 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 53951500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.996825 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1570 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 48762500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996825 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1570 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 5367 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34265.528407 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31035.178098 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1970 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 116400000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.632942 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 3397 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 105426500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.632942 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 3397 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 9 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 9 # number of Writeback hits +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::total 217661766 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.292796 # Inst issue rate +system.cpu.iq.fp_alu_accesses 2630821 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 5219937 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 2526643 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 5714467 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 280460790 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 778290063 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 273499649 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 575780653 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 401511304 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 281507534 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 1424 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 179800569 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 53698 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 178 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 375388973 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 1566 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34512.500000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31347.756410 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 6 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 53839500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.996169 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1560 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 48902500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996169 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1560 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 5770 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34287.021858 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31043.032787 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 2110 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 125490500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.634315 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 3660 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 113617500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.634315 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 3660 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 10 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 10 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.579412 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.575873 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 6942 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34296.657942 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31042.681699 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1975 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 170351500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.715500 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 4967 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 7336 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34354.406130 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31134.099617 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 2116 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 179330000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.711559 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 5220 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 154189000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.715500 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 4967 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 162520000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.711559 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 5220 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.068086 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::0 0.074027 # Average percentage of cache occupancy system.cpu.l2cache.occ_%::1 0.000031 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2231.049035 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 1.015700 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 6942 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34296.657942 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31042.681699 # average overall mshr miss latency +system.cpu.l2cache.occ_blocks::0 2425.713909 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 1.014918 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 7336 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34354.406130 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31134.099617 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1975 # number of overall hits -system.cpu.l2cache.overall_miss_latency 170351500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.715500 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 4967 # number of overall misses +system.cpu.l2cache.overall_hits 2116 # number of overall hits +system.cpu.l2cache.overall_miss_latency 179330000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.711559 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 5220 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 154189000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.715500 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 4967 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 162520000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.711559 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 5220 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3400 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 3664 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2232.064735 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1970 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2426.728827 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2110 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 21807942 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4495847 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 75869162 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 25600521 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 125958118 # number of misc regfile reads +system.cpu.memDep0.conflictingLoads 95035235 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 32152607 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 106923422 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 37463806 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 144601816 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.numCycles 255121086 # number of cpu cycles simulated +system.cpu.numCycles 217750949 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 1303093 # Number of cycles rename is blocking +system.cpu.rename.RENAME:BlockCycles 18951054 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 234363409 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 2662460 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 57579297 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 975892 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 963293874 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 304077108 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 331962025 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 180705413 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 11003980 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 4387817 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 97598616 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 7191870 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 956102004 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 16547 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 1274 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 8156807 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 1279 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 535181849 # The number of ROB reads -system.cpu.rob.rob_writes 594057529 # The number of ROB writes -system.cpu.timesIdled 2349 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 22087788 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 75841753 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 16619805 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 9 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 1071149424 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 415976206 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 437655168 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 58179410 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 23949638 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 40717504 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 203291759 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 11132052 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 1060017372 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 22407 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 1440 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 84366850 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 1310 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 592991425 # The number of ROB reads +system.cpu.rob.rob_writes 827053987 # The number of ROB writes +system.cpu.timesIdled 1919 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 400 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout index 3569c883b..9f05df433 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout @@ -5,13 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:36:47 +M5 compiled Feb 8 2011 00:58:32 +M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip +M5 started Feb 8 2011 00:58:34 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt index da648dcbf..0c54c7d41 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 777141 # Simulator instruction rate (inst/s) -host_mem_usage 230844 # Number of bytes of host memory used -host_seconds 284.84 # Real time elapsed on the host -host_tick_rate 461282227 # Simulator tick rate (ticks/s) +host_inst_rate 1396551 # Simulator instruction rate (inst/s) +host_mem_usage 231332 # Number of bytes of host memory used +host_seconds 158.51 # Real time elapsed on the host +host_tick_rate 828940820 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 221363018 # Number of instructions simulated sim_seconds 0.131393 # Number of seconds simulated @@ -24,7 +24,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 221363018 # Number of instructions executed system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses system.cpu.num_int_insts 220339607 # number of integer instructions -system.cpu.num_int_register_reads 686620674 # number of times the integer registers were read +system.cpu.num_int_register_reads 567557364 # number of times the integer registers were read system.cpu.num_int_register_writes 232532006 # number of times the integer registers were written system.cpu.num_load_insts 56649590 # Number of load instructions system.cpu.num_mem_refs 77165306 # number of memory refs diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout index 31ab1843b..72c0f8f4d 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout @@ -5,13 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:24 +M5 compiled Feb 8 2011 00:58:32 +M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip +M5 started Feb 8 2011 00:58:34 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sav -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt index ebc389a3a..bbd74268b 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 446836 # Simulator instruction rate (inst/s) -host_mem_usage 238556 # Number of bytes of host memory used -host_seconds 495.40 # Real time elapsed on the host -host_tick_rate 506580174 # Simulator tick rate (ticks/s) +host_inst_rate 920852 # Simulator instruction rate (inst/s) +host_mem_usage 239052 # Number of bytes of host memory used +host_seconds 240.39 # Real time elapsed on the host +host_tick_rate 1043974445 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 221363018 # Number of instructions simulated sim_seconds 0.250961 # Number of seconds simulated @@ -213,7 +213,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 221363018 # Number of instructions executed system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses system.cpu.num_int_insts 220339607 # number of integer instructions -system.cpu.num_int_register_reads 686620674 # number of times the integer registers were read +system.cpu.num_int_register_reads 567557364 # number of times the integer registers were read system.cpu.num_int_register_writes 232532006 # number of times the integer registers were written system.cpu.num_load_insts 56649590 # Number of load instructions system.cpu.num_mem_refs 77165306 # number of memory refs diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout index 254c4b8b1..fa50fea55 100755 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:37 -M5 executing on burrito +M5 compiled Feb 18 2011 15:40:30 +M5 revision Unknown +M5 started Feb 18 2011 18:52:59 +M5 executing on m55-001.pool command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 22288500 because target called exit() +Exiting @ tick 22294500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 246665e32..bb298d30a 100644 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,37 +1,37 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 37548 # Simulator instruction rate (inst/s) -host_mem_usage 223436 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host -host_tick_rate 130476959 # Simulator tick rate (ticks/s) +host_inst_rate 97475 # Simulator instruction rate (inst/s) +host_mem_usage 190320 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 337940129 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 22288500 # Number of ticks simulated -system.cpu.AGEN-Unit.agens 2187 # Number of Address Generations +sim_ticks 22294500 # Number of ticks simulated +system.cpu.AGEN-Unit.agens 2186 # Number of Address Generations system.cpu.Branch-Predictor.BTBHitPct 23.015873 # BTB Hit Percentage system.cpu.Branch-Predictor.BTBHits 87 # Number of BTB hits system.cpu.Branch-Predictor.BTBLookups 378 # Number of BTB lookups system.cpu.Branch-Predictor.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.Branch-Predictor.condIncorrect 543 # Number of conditional branches incorrect +system.cpu.Branch-Predictor.condIncorrect 542 # Number of conditional branches incorrect system.cpu.Branch-Predictor.condPredicted 995 # Number of conditional branches predicted system.cpu.Branch-Predictor.lookups 1423 # Number of BP lookups system.cpu.Branch-Predictor.predictedNotTaken 1183 # Number of Branches Predicted As Not Taken (False). system.cpu.Branch-Predictor.predictedTaken 240 # Number of Branches Predicted As Taken (True). system.cpu.Branch-Predictor.usedRAS 125 # Number of times the RAS was used to get a target. -system.cpu.Execution-Unit.executions 4617 # Number of Instructions Executed. -system.cpu.Execution-Unit.mispredictPct 51.615970 # Percentage of Incorrect Branches Predicts -system.cpu.Execution-Unit.mispredicted 543 # Number of Branches Incorrectly Predicted +system.cpu.Execution-Unit.executions 4596 # Number of Instructions Executed. +system.cpu.Execution-Unit.mispredictPct 51.569933 # Percentage of Incorrect Branches Predicts +system.cpu.Execution-Unit.mispredicted 542 # Number of Branches Incorrectly Predicted system.cpu.Execution-Unit.predicted 509 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predictedNotTakenIncorrect 538 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.Execution-Unit.predictedNotTakenIncorrect 537 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.Execution-Unit.predictedTakenIncorrect 5 # Number of Branches Incorrectly Predicted As Taken. system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed system.cpu.Mult-Div-Unit.multiplies 1 # Number of Multipy Operations Executed -system.cpu.RegFile-Manager.regFileAccesses 10532 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.RegFile-Manager.regFileReads 5949 # Number of Reads from Register File +system.cpu.RegFile-Manager.regFileAccesses 10530 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.RegFile-Manager.regFileReads 5947 # Number of Reads from Register File system.cpu.RegFile-Manager.regFileWrites 4583 # Number of Writes to Register File system.cpu.RegFile-Manager.regForwards 2845 # Number of Registers Read Through Forwarding Logic -system.cpu.activity 16.048275 # Percentage of cycles cpu is active +system.cpu.activity 16.075353 # Percentage of cycles cpu is active system.cpu.comBranches 1051 # Number of Branches instructions committed system.cpu.comFloats 2 # Number of Floating Point instructions committed system.cpu.comInts 3265 # Number of Integer instructions committed @@ -42,17 +42,17 @@ system.cpu.comStores 865 # Nu system.cpu.committedInsts 6404 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 6404 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 6.960962 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 6.960962 # CPI: Total CPI of All Threads +system.cpu.cpi 6.962836 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 6.962836 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 56781.250000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53784.210526 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 56786.458333 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53789.473684 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 1089 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5451000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 5451500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.081013 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 96 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 5109500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 5110000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) @@ -75,31 +75,31 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 162000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 56661.157025 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53687.500000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 56663.223140 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53690.476190 # average overall mshr miss latency system.cpu.dcache.demand_hits 1808 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 13712000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 13712500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.118049 # miss rate for demand accesses system.cpu.dcache.demand_misses 242 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 74 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9019500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 9020000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.081951 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 168 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.024901 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 101.993452 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.024898 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 101.981030 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 56661.157025 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53687.500000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 56663.223140 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53690.476190 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1808 # number of overall hits -system.cpu.dcache.overall_miss_latency 13712000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 13712500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.118049 # miss rate for overall accesses system.cpu.dcache.overall_misses 242 # number of overall misses system.cpu.dcache.overall_mshr_hits 74 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9019500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 9020000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.081951 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -107,7 +107,7 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 101.993452 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 101.981030 # Cycle average of tags in use system.cpu.dcache.total_refs 1808 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -128,10 +128,10 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 865 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.icache.ReadReq_accesses 955 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55326.979472 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency 55322.580645 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53094.684385 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 614 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 18866500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 18865000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.357068 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 341 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 40 # number of ReadReq MSHR hits @@ -147,10 +147,10 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 955 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55326.979472 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency 55322.580645 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 53094.684385 # average overall mshr miss latency system.cpu.icache.demand_hits 614 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 18866500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 18865000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.357068 # miss rate for demand accesses system.cpu.icache.demand_misses 341 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 40 # number of demand (read+write) MSHR hits @@ -160,14 +160,14 @@ system.cpu.icache.demand_mshr_misses 301 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.066887 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 136.984147 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.066877 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 136.964505 # Average occupied blocks per context system.cpu.icache.overall_accesses 955 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55326.979472 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 55322.580645 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53094.684385 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 614 # number of overall hits -system.cpu.icache.overall_miss_latency 18866500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 18865000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.357068 # miss rate for overall accesses system.cpu.icache.overall_misses 341 # number of overall misses system.cpu.icache.overall_mshr_hits 40 # number of overall MSHR hits @@ -179,13 +179,13 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 300 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 136.984147 # Cycle average of tags in use +system.cpu.icache.tagsinuse 136.964505 # Cycle average of tags in use system.cpu.icache.total_refs 614 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 37424 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.143658 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.143658 # IPC: Total IPC of All Threads +system.cpu.idleCycles 37422 # Number of cycles cpu's stages were not processed +system.cpu.ipc 0.143620 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.143620 # IPC: Total IPC of All Threads system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits @@ -243,8 +243,8 @@ system.cpu.l2cache.demand_mshr_misses 468 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005889 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 192.975400 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.005888 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 192.950109 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 469 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52243.589744 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40087.606838 # average overall mshr miss latency @@ -262,34 +262,34 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 394 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 192.975400 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 192.950109 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 44578 # number of cpu cycles simulated +system.cpu.numCycles 44590 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.runCycles 7154 # Number of cycles cpu stages are processed. +system.cpu.runCycles 7168 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 39836 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 4742 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 10.637534 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 40747 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 3831 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 8.593925 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 40491 # Number of cycles 0 instructions are processed. -system.cpu.stage-2.runCycles 4087 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 9.168200 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 43168 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.idleCycles 39847 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.runCycles 4743 # Number of cycles 1+ instructions are processed. +system.cpu.stage-0.utilization 10.636914 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 40758 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.runCycles 3832 # Number of cycles 1+ instructions are processed. +system.cpu.stage-1.utilization 8.593855 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 40488 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.runCycles 4102 # Number of cycles 1+ instructions are processed. +system.cpu.stage-2.utilization 9.199372 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 43180 # Number of cycles 0 instructions are processed. system.cpu.stage-3.runCycles 1410 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 3.162995 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 40170 # Number of cycles 0 instructions are processed. -system.cpu.stage-4.runCycles 4408 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 9.888286 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 11304 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.stage-3.utilization 3.162144 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 40181 # Number of cycles 0 instructions are processed. +system.cpu.stage-4.runCycles 4409 # Number of cycles 1+ instructions are processed. +system.cpu.stage-4.utilization 9.887867 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 11319 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.timesIdled 425 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout index 2ad70ea48..41a76071a 100755 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:55:51 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:56:02 -M5 executing on burrito +M5 compiled Feb 18 2011 18:35:15 +M5 revision Unknown +M5 started Feb 18 2011 18:52:36 +M5 executing on m55-001.pool command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 21534000 because target called exit() +Exiting @ tick 21538000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt index 1e86aa862..ac0fe4aec 100644 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,37 +1,37 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 32668 # Simulator instruction rate (inst/s) -host_mem_usage 224608 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host -host_tick_rate 120542676 # Simulator tick rate (ticks/s) +host_inst_rate 94112 # Simulator instruction rate (inst/s) +host_mem_usage 191540 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 346291258 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5827 # Number of instructions simulated sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 21534000 # Number of ticks simulated +sim_ticks 21538000 # Number of ticks simulated system.cpu.AGEN-Unit.agens 2404 # Number of Address Generations system.cpu.Branch-Predictor.BTBHitPct 14.054054 # BTB Hit Percentage system.cpu.Branch-Predictor.BTBHits 26 # Number of BTB hits system.cpu.Branch-Predictor.BTBLookups 185 # Number of BTB lookups system.cpu.Branch-Predictor.RASInCorrect 30 # Number of incorrect RAS predictions. -system.cpu.Branch-Predictor.condIncorrect 845 # Number of conditional branches incorrect +system.cpu.Branch-Predictor.condIncorrect 844 # Number of conditional branches incorrect system.cpu.Branch-Predictor.condPredicted 778 # Number of conditional branches predicted system.cpu.Branch-Predictor.lookups 1066 # Number of BP lookups system.cpu.Branch-Predictor.predictedNotTaken 949 # Number of Branches Predicted As Not Taken (False). system.cpu.Branch-Predictor.predictedTaken 117 # Number of Branches Predicted As Taken (True). system.cpu.Branch-Predictor.usedRAS 86 # Number of times the RAS was used to get a target. -system.cpu.Execution-Unit.executions 3963 # Number of Instructions Executed. -system.cpu.Execution-Unit.mispredictPct 92.148310 # Percentage of Incorrect Branches Predicts -system.cpu.Execution-Unit.mispredicted 845 # Number of Branches Incorrectly Predicted +system.cpu.Execution-Unit.executions 3261 # Number of Instructions Executed. +system.cpu.Execution-Unit.mispredictPct 92.139738 # Percentage of Incorrect Branches Predicts +system.cpu.Execution-Unit.mispredicted 844 # Number of Branches Incorrectly Predicted system.cpu.Execution-Unit.predicted 72 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predictedNotTakenIncorrect 813 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.Execution-Unit.predictedNotTakenIncorrect 812 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.Execution-Unit.predictedTakenIncorrect 32 # Number of Branches Incorrectly Predicted As Taken. system.cpu.Mult-Div-Unit.divides 1 # Number of Divide Operations Executed system.cpu.Mult-Div-Unit.multiplies 3 # Number of Multipy Operations Executed -system.cpu.RegFile-Manager.regFileAccesses 10006 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.RegFile-Manager.regFileReads 6596 # Number of Reads from Register File +system.cpu.RegFile-Manager.regFileAccesses 10004 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.RegFile-Manager.regFileReads 6594 # Number of Reads from Register File system.cpu.RegFile-Manager.regFileWrites 3410 # Number of Writes to Register File system.cpu.RegFile-Manager.regForwards 1378 # Number of Registers Read Through Forwarding Logic -system.cpu.activity 13.935777 # Percentage of cycles cpu is active +system.cpu.activity 13.954082 # Percentage of cycles cpu is active system.cpu.comBranches 916 # Number of Branches instructions committed system.cpu.comFloats 0 # Number of Floating Point instructions committed system.cpu.comInts 2155 # Number of Integer instructions committed @@ -42,17 +42,17 @@ system.cpu.comStores 925 # Nu system.cpu.committedInsts 5827 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 5827 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 7.391282 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 7.391282 # CPI: Total CPI of All Threads +system.cpu.cpi 7.392655 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 7.392655 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 56681.818182 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53683.908046 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 56676.136364 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53678.160920 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 1076 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4988000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 4987500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.075601 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 88 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 4670500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 4670000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) @@ -75,31 +75,31 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 265500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 56298.342541 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53666.666667 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 56295.580110 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53663.043478 # average overall mshr miss latency system.cpu.dcache.demand_hits 1908 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10190000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 10189500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.086644 # miss rate for demand accesses system.cpu.dcache.demand_misses 181 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 43 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 7406000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 7405500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.066060 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.021745 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 89.066455 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 89.067186 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 56298.342541 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53666.666667 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 56295.580110 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53663.043478 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1908 # number of overall hits -system.cpu.dcache.overall_miss_latency 10190000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 10189500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.086644 # miss rate for overall accesses system.cpu.dcache.overall_misses 181 # number of overall misses system.cpu.dcache.overall_mshr_hits 43 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 7406000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 7405500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.066060 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -107,7 +107,7 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 89.066455 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 89.067186 # Cycle average of tags in use system.cpu.dcache.total_refs 1908 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -121,14 +121,14 @@ system.cpu.dtb.write_accesses 0 # DT system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.icache.ReadReq_accesses 853 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55526.246719 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53153.605016 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 55527.559055 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53156.739812 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 472 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 21155500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 21156000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.446659 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 381 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 62 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 16956000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 16957000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.373974 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 319 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -140,31 +140,31 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 62000 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 853 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55526.246719 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53153.605016 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 55527.559055 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53156.739812 # average overall mshr miss latency system.cpu.icache.demand_hits 472 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 21155500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 21156000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.446659 # miss rate for demand accesses system.cpu.icache.demand_misses 381 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 62 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 16956000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 16957000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.373974 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 319 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.070944 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 145.293265 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.070945 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 145.295903 # Average occupied blocks per context system.cpu.icache.overall_accesses 853 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55526.246719 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53153.605016 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 55527.559055 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53156.739812 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 472 # number of overall hits -system.cpu.icache.overall_miss_latency 21155500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 21156000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.446659 # miss rate for overall accesses system.cpu.icache.overall_misses 381 # number of overall misses system.cpu.icache.overall_mshr_hits 62 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 16956000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 16957000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.373974 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -172,13 +172,13 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 13 # number of replacements system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 145.293265 # Cycle average of tags in use +system.cpu.icache.tagsinuse 145.295903 # Cycle average of tags in use system.cpu.icache.total_refs 472 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 37067 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.135295 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.135295 # IPC: Total IPC of All Threads +system.cpu.idleCycles 37066 # Number of cycles cpu's stages were not processed +system.cpu.ipc 0.135269 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.135269 # IPC: Total IPC of All Threads system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses @@ -198,13 +198,13 @@ system.cpu.l2cache.ReadExReq_mshr_miss_latency 2052000 system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 406 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52355.198020 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40152.227723 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52357.673267 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40153.465347 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 21151500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 21152500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.995074 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 404 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 16221500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 16222000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995074 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 404 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -216,31 +216,31 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 457 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52368.131868 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40161.538462 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52370.329670 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40162.637363 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 23827500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 23828500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.995624 # miss rate for demand accesses system.cpu.l2cache.demand_misses 455 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 18273500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 18274000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.995624 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 455 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.occ_%::0 0.006169 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 202.148379 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::0 202.151439 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 457 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52368.131868 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40161.538462 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52370.329670 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40162.637363 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 23827500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 23828500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.995624 # miss rate for overall accesses system.cpu.l2cache.overall_misses 455 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 18273500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 18274000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.995624 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 455 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -248,34 +248,34 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 202.148379 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 202.151439 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 43069 # number of cpu cycles simulated +system.cpu.numCycles 43077 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.runCycles 6002 # Number of cycles cpu stages are processed. +system.cpu.runCycles 6011 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 39196 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 3873 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 8.992547 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 40152 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 2917 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 6.772853 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 40243 # Number of cycles 0 instructions are processed. -system.cpu.stage-2.runCycles 2826 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 6.561564 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 41749 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.idleCycles 39203 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.runCycles 3874 # Number of cycles 1+ instructions are processed. +system.cpu.stage-0.utilization 8.993198 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 40159 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.runCycles 2918 # Number of cycles 1+ instructions are processed. +system.cpu.stage-1.utilization 6.773916 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 40245 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.runCycles 2832 # Number of cycles 1+ instructions are processed. +system.cpu.stage-2.utilization 6.574274 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 41757 # Number of cycles 0 instructions are processed. system.cpu.stage-3.runCycles 1320 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 3.064849 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 39866 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.utilization 3.064280 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 39874 # Number of cycles 0 instructions are processed. system.cpu.stage-4.runCycles 3203 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 7.436904 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 10184 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.stage-4.utilization 7.435522 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 10193 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.timesIdled 427 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 8 # Number of system calls diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout index 0767b9777..1943466e8 100755 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout @@ -5,12 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:13 +M5 compiled Feb 12 2011 02:22:23 +M5 revision 5e76f9de6972 7961 default qtip tip x86branchdetectstats.patch +M5 started Feb 12 2011 02:22:27 M5 executing on burrito -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. Hello world! -Exiting @ tick 13766000 because target called exit() +Exiting @ tick 11421500 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt index 182e72d25..c2dfaa3ff 100644 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 47133 # Simulator instruction rate (inst/s) -host_mem_usage 227692 # Number of bytes of host memory used +host_inst_rate 47598 # Simulator instruction rate (inst/s) +host_mem_usage 231896 # Number of bytes of host memory used host_seconds 0.21 # Real time elapsed on the host -host_tick_rate 66053082 # Simulator tick rate (ticks/s) +host_tick_rate 55349277 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9809 # Number of instructions simulated -sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 13766000 # Number of ticks simulated +sim_seconds 0.000011 # Number of seconds simulated +sim_ticks 11421500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 772 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1892 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 944 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 2550 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 458 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1920 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 1920 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 485 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 2777 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2777 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 1214 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 37 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 139 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 15124 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.648572 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.100130 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 11906 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.823870 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.588166 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 9612 63.55% 63.55% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 3088 20.42% 83.97% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 1220 8.07% 92.04% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 836 5.53% 97.57% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 232 1.53% 99.10% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 57 0.38% 99.48% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 30 0.20% 99.68% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 12 0.08% 99.76% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 37 0.24% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 8274 69.49% 69.49% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 1230 10.33% 79.83% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 588 4.94% 84.76% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 963 8.09% 92.85% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 395 3.32% 96.17% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 136 1.14% 97.31% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 125 1.05% 98.36% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 56 0.47% 98.83% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 139 1.17% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 15124 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 11906 # Number of insts commited each cycle system.cpu.commit.COM:count 9809 # Number of instructions committed system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 0 # Number of function calls committed. @@ -44,415 +44,417 @@ system.cpu.commit.COM:loads 1056 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 1990 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 462 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 485 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 9809 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 3832 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9374 # The number of squashed insts skipped by commit system.cpu.committedInsts 9809 # Number of Instructions Simulated system.cpu.committedInsts_total 9809 # Number of Instructions Simulated -system.cpu.cpi 2.806912 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.806912 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1244 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 37105.263158 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35048.387097 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1168 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2820000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.061093 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 76 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2173000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.049839 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 62 # number of ReadReq MSHR misses +system.cpu.cpi 2.328882 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.328882 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1541 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 34473.684211 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35119.402985 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1427 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3930000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.073978 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 114 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 47 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2353000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.043478 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 67 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 33138.977636 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35775.641026 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 34089.456869 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36012.987013 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 621 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 10372500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 10670000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.335118 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 313 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 235 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2790500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.083512 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 78 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_hits 236 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2773000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.082441 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 77 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 12.870504 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 14.321678 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2178 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 33913.881748 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35453.571429 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1789 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 13192500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.178604 # miss rate for demand accesses -system.cpu.dcache.demand_misses 389 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 249 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4963500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.064279 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 140 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 2475 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 34192.037471 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35597.222222 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 14600000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.172525 # miss rate for demand accesses +system.cpu.dcache.demand_misses 427 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 283 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 5126000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.058182 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 144 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.020744 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 84.965644 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 2178 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 33913.881748 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35453.571429 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.020970 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 85.892970 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 2475 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 34192.037471 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35597.222222 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1789 # number of overall hits -system.cpu.dcache.overall_miss_latency 13192500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.178604 # miss rate for overall accesses -system.cpu.dcache.overall_misses 389 # number of overall misses -system.cpu.dcache.overall_mshr_hits 249 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4963500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.064279 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 140 # number of overall MSHR misses +system.cpu.dcache.overall_hits 2048 # number of overall hits +system.cpu.dcache.overall_miss_latency 14600000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.172525 # miss rate for overall accesses +system.cpu.dcache.overall_misses 427 # number of overall misses +system.cpu.dcache.overall_mshr_hits 283 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 5126000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.058182 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 144 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 139 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 143 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 84.965644 # Cycle average of tags in use -system.cpu.dcache.total_refs 1789 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 85.892970 # Cycle average of tags in use +system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 464 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 15304 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 6233 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 8371 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 721 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 56 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 1920 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1255 # Number of cache lines fetched -system.cpu.fetch.Cycles 9031 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 117 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 8830 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 8 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 469 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.069735 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1255 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 772 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.320706 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 15845 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.002083 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.178869 # Number of instructions fetched each cycle (Total) +system.cpu.decode.DECODE:BlockedCycles 1367 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 22275 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 7155 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 3308 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1504 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 76 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 2777 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1732 # Number of cache lines fetched +system.cpu.fetch.Cycles 3623 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 245 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 12976 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 508 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.121564 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1732 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 944 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.568027 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 13410 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.734526 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.109133 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 7129 44.99% 44.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4489 28.33% 73.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1878 11.85% 85.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2046 12.91% 98.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 57 0.36% 98.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 227 1.43% 99.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6 0.04% 99.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8 0.05% 99.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 5 0.03% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9877 73.65% 73.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 162 1.21% 74.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 123 0.92% 75.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 227 1.69% 77.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 192 1.43% 78.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 174 1.30% 80.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 266 1.98% 82.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 175 1.30% 83.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2214 16.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15845 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 2 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 1255 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 37417.543860 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35040.697674 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 970 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 10664000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.227092 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 285 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 9040500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.205578 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 258 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 13410 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 4 # number of floating regfile reads +system.cpu.icache.ReadReq_accesses 1732 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 36454.794521 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35105.084746 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1367 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 13306000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.210739 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 365 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 70 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 10356000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.170323 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 295 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.759690 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.633898 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1255 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 37417.543860 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35040.697674 # average overall mshr miss latency -system.cpu.icache.demand_hits 970 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 10664000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.227092 # miss rate for demand accesses -system.cpu.icache.demand_misses 285 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 27 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 9040500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.205578 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 258 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 1732 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 36454.794521 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35105.084746 # average overall mshr miss latency +system.cpu.icache.demand_hits 1367 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 13306000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.210739 # miss rate for demand accesses +system.cpu.icache.demand_misses 365 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 70 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 10356000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.170323 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 295 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.061525 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 126.002915 # Average occupied blocks per context -system.cpu.icache.overall_accesses 1255 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 37417.543860 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35040.697674 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.070726 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 144.846093 # Average occupied blocks per context +system.cpu.icache.overall_accesses 1732 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 36454.794521 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35105.084746 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 970 # number of overall hits -system.cpu.icache.overall_miss_latency 10664000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.227092 # miss rate for overall accesses -system.cpu.icache.overall_misses 285 # number of overall misses -system.cpu.icache.overall_mshr_hits 27 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 9040500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.205578 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 258 # number of overall MSHR misses +system.cpu.icache.overall_hits 1367 # number of overall hits +system.cpu.icache.overall_miss_latency 13306000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.210739 # miss rate for overall accesses +system.cpu.icache.overall_misses 365 # number of overall misses +system.cpu.icache.overall_mshr_hits 70 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 10356000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.170323 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 295 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 258 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 295 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 126.002915 # Cycle average of tags in use -system.cpu.icache.total_refs 970 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 144.846093 # Cycle average of tags in use +system.cpu.icache.total_refs 1367 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 11688 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1318 # Number of branches executed +system.cpu.idleCycles 9434 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1551 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.434678 # Inst execution rate -system.cpu.iew.EXEC:refs 2353 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1060 # Number of stores executed +system.cpu.iew.EXEC:rate 0.676151 # Inst execution rate +system.cpu.iew.EXEC:refs 2971 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1306 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 10358 # num instructions consuming a value -system.cpu.iew.WB:count 11818 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.702935 # average fanout of values written-back +system.cpu.iew.WB:consumers 14704 # num instructions consuming a value +system.cpu.iew.WB:count 15138 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.679747 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 7281 # num instructions producing a value -system.cpu.iew.WB:rate 0.429230 # insts written-back per cycle -system.cpu.iew.WB:sent 11866 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 487 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 58 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 1535 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 17 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 418 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1238 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 13635 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1293 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 536 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 11968 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 9995 # num instructions producing a value +system.cpu.iew.WB:rate 0.662669 # insts written-back per cycle +system.cpu.iew.WB:sent 15263 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 565 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 187 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2105 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 207 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1639 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 19184 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1665 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 710 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 15446 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 721 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1504 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 21 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 68 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 479 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 304 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 390 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 25083 # number of integer regfile reads -system.cpu.int_regfile_writes 11189 # number of integer regfile writes -system.cpu.ipc 0.356263 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.356263 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 10018 80.12% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 1360 10.88% 91.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1123 8.98% 100.00% # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 31 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1049 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 705 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 31 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 496 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 23051 # number of integer regfile reads +system.cpu.int_regfile_writes 14062 # number of integer regfile writes +system.cpu.ipc 0.429391 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.429391 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 12967 80.26% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 1786 11.05% 91.34% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1399 8.66% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 12504 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 4 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.000320 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 16156 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 142 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.008789 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 3 75.00% 75.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 1 25.00% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 97 68.31% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 26 18.31% 86.62% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 19 13.38% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 15845 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.789145 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 0.977935 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 13410 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.204773 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.912582 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 8160 51.50% 51.50% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 4079 25.74% 77.24% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 2594 16.37% 93.61% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 834 5.26% 98.88% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 157 0.99% 99.87% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 19 0.12% 99.99% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 2 0.01% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 8282 61.76% 61.76% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 1307 9.75% 71.51% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 986 7.35% 78.86% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 745 5.56% 84.41% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 787 5.87% 90.28% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 588 4.38% 94.67% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 498 3.71% 98.38% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 170 1.27% 99.65% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 47 0.35% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 15845 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.454146 # Inst issue rate -system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 12501 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 40849 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 11816 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 16975 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 13618 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 12504 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 17 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3342 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 5066 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 78 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34493.589744 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31326.923077 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2690500 # number of ReadExReq miss cycles +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::total 13410 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.707232 # Inst issue rate +system.cpu.iq.fp_alu_accesses 5 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 9 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 16289 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 45908 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 15134 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 27963 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 19154 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 16156 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 8758 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 11067 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 77 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34616.883117 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31389.610390 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2665500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 78 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2443500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 77 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2417000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 78 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 320 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34188.679245 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.716981 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_misses 77 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 362 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34245.833333 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31040.277778 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 10872000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.993750 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 318 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 9859500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.993750 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 318 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 12328500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.994475 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 360 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 11174500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994475 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 360 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.006309 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.005571 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 398 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34248.737374 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31068.181818 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 439 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34311.212815 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31101.830664 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 13562500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.994975 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 396 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 14994000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995444 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 437 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 12303000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.994975 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 396 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 13591500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.995444 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 437 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.004816 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 157.820330 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 398 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34248.737374 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31068.181818 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.005436 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 178.138745 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 439 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34311.212815 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31101.830664 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 13562500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.994975 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 396 # number of overall misses +system.cpu.l2cache.overall_miss_latency 14994000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995444 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 437 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 12303000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.994975 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 396 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 13591500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.995444 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 437 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 317 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 157.820330 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 178.138745 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 1535 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1238 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 5334 # number of misc regfile reads -system.cpu.numCycles 27533 # number of cpu cycles simulated +system.cpu.memDep0.conflictingLoads 24 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 2105 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1639 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 6857 # number of misc regfile reads +system.cpu.numCycles 22844 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 105 # Number of cycles rename is blocking +system.cpu.rename.RENAME:BlockCycles 565 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 9368 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 6603 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 15 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 38664 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 14745 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 13787 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 8027 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 721 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 108 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4419 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:IQFullEvents 51 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 7399 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 247 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 44700 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 21187 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 19905 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 3124 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1504 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 378 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 10537 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:fp_rename_lookups 16 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 38648 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 281 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 20 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 169 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 17 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 28728 # The number of ROB reads -system.cpu.rob.rob_writes 28005 # The number of ROB writes -system.cpu.timesIdled 208 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:int_rename_lookups 44684 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 440 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 32 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 1476 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 31 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 30950 # The number of ROB reads +system.cpu.rob.rob_writes 39896 # The number of ROB writes +system.cpu.timesIdled 184 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout index 09f4d0b50..8fb08388b 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:13 +M5 compiled Feb 8 2011 00:58:32 +M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip +M5 started Feb 8 2011 00:58:34 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt index 1dca11ec5..cddb4c7b6 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 180423 # Simulator instruction rate (inst/s) -host_mem_usage 219128 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 103433649 # Simulator tick rate (ticks/s) +host_inst_rate 992012 # Simulator instruction rate (inst/s) +host_mem_usage 219616 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 556721453 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9810 # Number of instructions simulated sim_seconds 0.000006 # Number of seconds simulated @@ -24,7 +24,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 9810 # Number of instructions executed system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses system.cpu.num_int_insts 9715 # number of integer instructions -system.cpu.num_int_register_reads 26194 # number of times the integer registers were read +system.cpu.num_int_register_reads 21313 # number of times the integer registers were read system.cpu.num_int_register_writes 9368 # number of times the integer registers were written system.cpu.num_load_insts 1056 # Number of load instructions system.cpu.num_mem_refs 1990 # number of memory refs diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats index a12716c02..569662936 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Feb/07/2011 02:32:13 +Real time: Feb/08/2011 00:58:34 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.35 -Virtual_time_in_minutes: 0.00583333 -Virtual_time_in_hours: 9.72222e-05 -Virtual_time_in_days: 4.05093e-06 +Virtual_time_in_seconds: 0.26 +Virtual_time_in_minutes: 0.00433333 +Virtual_time_in_hours: 7.22222e-05 +Virtual_time_in_days: 3.00926e-06 Ruby_current_time: 276484 Ruby_start_time: 0 Ruby_cycles: 276484 -mbytes_resident: 38.6094 -mbytes_total: 231.508 -resident_ratio: 0.16679 +mbytes_resident: 38.6797 +mbytes_total: 231.98 +resident_ratio: 0.166754 ruby_cycles_executed: [ 276485 ] @@ -125,7 +125,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 10950 +page_reclaims: 11003 page_faults: 0 swaps: 0 block_inputs: 0 diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout index 877c8d9b9..ab908eedc 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:13 +M5 compiled Feb 8 2011 00:58:32 +M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip +M5 started Feb 8 2011 00:58:34 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index b88df01c5..491eaf1d1 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 32378 # Simulator instruction rate (inst/s) -host_mem_usage 237068 # Number of bytes of host memory used -host_seconds 0.30 # Real time elapsed on the host -host_tick_rate 911908 # Simulator tick rate (ticks/s) +host_inst_rate 81703 # Simulator instruction rate (inst/s) +host_mem_usage 237552 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host +host_tick_rate 2292859 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 9810 # Number of instructions simulated sim_seconds 0.000276 # Number of seconds simulated @@ -24,7 +24,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 9810 # Number of instructions executed system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses system.cpu.num_int_insts 9715 # number of integer instructions -system.cpu.num_int_register_reads 26194 # number of times the integer registers were read +system.cpu.num_int_register_reads 21313 # number of times the integer registers were read system.cpu.num_int_register_writes 9368 # number of times the integer registers were written system.cpu.num_load_insts 1056 # Number of load instructions system.cpu.num_mem_refs 1990 # number of memory refs diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout index d6afbecf0..43766d7be 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:24 +M5 compiled Feb 8 2011 00:58:32 +M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip +M5 started Feb 8 2011 00:58:34 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt index 0c21882f5..fc7acffe1 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 594010 # Simulator instruction rate (inst/s) -host_mem_usage 226844 # Number of bytes of host memory used +host_inst_rate 525864 # Simulator instruction rate (inst/s) +host_mem_usage 227336 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 1712507148 # Simulator tick rate (ticks/s) +host_tick_rate 1518719132 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9810 # Number of instructions simulated sim_seconds 0.000029 # Number of seconds simulated @@ -208,7 +208,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 9810 # Number of instructions executed system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses system.cpu.num_int_insts 9715 # number of integer instructions -system.cpu.num_int_register_reads 26194 # number of times the integer registers were read +system.cpu.num_int_register_reads 21313 # number of times the integer registers were read system.cpu.num_int_register_writes 9368 # number of times the integer registers were written system.cpu.num_load_insts 1056 # Number of load instructions system.cpu.num_mem_refs 1990 # number of memory refs diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index 79021a958..859778cbe 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -7,11 +7,11 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem -children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus +children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver boot_cpu_frequency=500 boot_osflags=earlyprintk mem=128MB console=ttyAMA0 lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm +kernel=/chips/pd/randd/dist/binaries/vmlinux.arm load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic @@ -167,7 +167,7 @@ type=ExeTracer [system.diskmem] type=PhysicalMemory -file=/dist/m5/system/disks/ael-arm.ext2 +file=/chips/pd/randd/dist/disks/ael-arm.ext2 latency=30000 latency_var=0 null=false @@ -187,7 +187,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side system.realview.clcd.dma +port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.realview.cf0_fake.pio system.iocache.cpu_side system.realview.clcd.dma [system.iocache] type=BaseCache @@ -217,7 +217,7 @@ tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.iobus.port[24] +cpu_side=system.iobus.port[25] mem_side=system.membus.port[5] [system.l2c] @@ -291,7 +291,7 @@ port=system.membus.port[1] [system.realview] type=RealView -children=aaci_fake clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=aaci_fake cf0_fake clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake intrctrl=system.intrctrl system=system @@ -305,6 +305,22 @@ platform=system.realview system=system pio=system.iobus.port[20] +[system.realview.cf0_fake] +type=IsaFake +pio_addr=402653184 +pio_latency=1000 +pio_size=4095 +platform=system.realview +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[24] + [system.realview.clcd] type=Pl111 amba_id=1315089 @@ -317,7 +333,8 @@ pio_addr=268566528 pio_latency=10000 platform=system.realview system=system -dma=system.iobus.port[25] +vnc=system.vncserver +dma=system.iobus.port[26] pio=system.iobus.port[5] [system.realview.dmac_fake] @@ -391,24 +408,28 @@ pio=system.iobus.port[17] type=Pl050 amba_id=1314896 gic=system.realview.gic -int_delay=100000 +int_delay=1000000 int_num=52 +is_mouse=false pio_addr=268460032 pio_latency=1000 platform=system.realview system=system +vnc=system.vncserver pio=system.iobus.port[6] [system.realview.kmi1] type=Pl050 amba_id=1314896 gic=system.realview.gic -int_delay=100000 +int_delay=1000000 int_num=53 +is_mouse=true pio_addr=268464128 pio_latency=1000 platform=system.realview system=system +vnc=system.vncserver pio=system.iobus.port[7] [system.realview.l2x0_fake] @@ -594,3 +615,8 @@ use_default_range=false width=64 port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.vncserver] +type=VncServer +number=0 +port=5900 + diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr index 122561307..63ac398c9 100755 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr @@ -1,3 +1,5 @@ +warn: Sockets disabled, not accepting vnc client connections +For more information see: http://www.m5sim.org/warn/af6a84f6 warn: Sockets disabled, not accepting terminal connections For more information see: http://www.m5sim.org/warn/8742226b warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout index ba4c6742c..180619cc1 100755 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:53:13 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:53:26 -M5 executing on burrito +M5 compiled Feb 11 2011 17:53:57 +M5 revision 6c65f7ee86c1 7949 default qtip tip ext/vnc_stats_updates.patch +M5 started Feb 11 2011 17:54:00 +M5 executing on u200439-lin.austin.arm.com command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm +info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 25821310500 because m5_exit instruction encountered +Exiting @ tick 26073617500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 0a7542a7c..9854d94df 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,63 +1,63 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 739167 # Simulator instruction rate (inst/s) -host_mem_usage 360776 # Number of bytes of host memory used -host_seconds 68.93 # Real time elapsed on the host -host_tick_rate 374609475 # Simulator tick rate (ticks/s) +host_inst_rate 2481190 # Simulator instruction rate (inst/s) +host_mem_usage 374936 # Number of bytes of host memory used +host_seconds 20.74 # Real time elapsed on the host +host_tick_rate 1257294139 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 50949504 # Number of instructions simulated -sim_seconds 0.025821 # Number of seconds simulated -sim_ticks 25821310500 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses::0 96794 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 96794 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits::0 91895 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 91895 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.050613 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 4899 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 4899 # number of LoadLockedReq misses -system.cpu.dcache.ReadReq_accesses::0 7714516 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 7714516 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_hits::0 7482193 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7482193 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_rate::0 0.030115 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 232323 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 232323 # number of ReadReq misses -system.cpu.dcache.StoreCondReq_accesses::0 96793 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 96793 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::0 96793 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 96793 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::0 6604860 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6604860 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_hits::0 6433311 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6433311 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_rate::0 0.025973 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 171549 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 171549 # number of WriteReq misses +sim_insts 51454118 # Number of instructions simulated +sim_seconds 0.026074 # Number of seconds simulated +sim_ticks 26073617500 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses::0 100454 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 100454 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits::0 95292 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 95292 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.051387 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 5162 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 5162 # number of LoadLockedReq misses +system.cpu.dcache.ReadReq_accesses::0 7830681 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 7830681 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::0 7594158 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7594158 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_rate::0 0.030205 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 236523 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 236523 # number of ReadReq misses +system.cpu.dcache.StoreCondReq_accesses::0 100453 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 100453 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::0 100453 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 100453 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses::0 6676067 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6676067 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_hits::0 6503881 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6503881 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_rate::0 0.025792 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 172186 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 172186 # number of WriteReq misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 34.663994 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 34.695419 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 14319376 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 14506748 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 14319376 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 14506748 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 13915504 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::0 14098039 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13915504 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 14098039 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.028205 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::0 0.028174 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 403872 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 408709 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 403872 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 408709 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses @@ -67,26 +67,26 @@ system.cpu.dcache.demand_mshr_misses 0 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999475 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 511.731250 # Average occupied blocks per context -system.cpu.dcache.overall_accesses::0 14319376 # number of overall (read+write) accesses +system.cpu.dcache.occ_%::0 0.999480 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 511.733850 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 14506748 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 14319376 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 14506748 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 13915504 # number of overall hits +system.cpu.dcache.overall_hits::0 14098039 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 13915504 # number of overall hits +system.cpu.dcache.overall_hits::total 14098039 # number of overall hits system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.028205 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.028174 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 403872 # number of overall misses +system.cpu.dcache.overall_misses::0 408709 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 403872 # number of overall misses +system.cpu.dcache.overall_misses::total 408709 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses @@ -95,66 +95,66 @@ system.cpu.dcache.overall_mshr_miss_rate::total no_value system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 406424 # number of replacements -system.cpu.dcache.sampled_refs 406936 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 411520 # number of replacements +system.cpu.dcache.sampled_refs 412032 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.731250 # Cycle average of tags in use -system.cpu.dcache.total_refs 14106027 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 511.733850 # Cycle average of tags in use +system.cpu.dcache.total_refs 14295623 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 21760000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 379025 # number of writebacks -system.cpu.dtb.accesses 15336291 # DTB accesses +system.cpu.dcache.writebacks 381867 # number of writebacks +system.cpu.dtb.accesses 15531286 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 2242 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 2267 # Number of entries that have been flushed from TLB system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 15330762 # DTB hits +system.cpu.dtb.hits 15525735 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 5529 # DTB misses +system.cpu.dtb.misses 5551 # DTB misses system.cpu.dtb.perms_faults 255 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 768 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 8622893 # DTB read accesses -system.cpu.dtb.read_hits 8618361 # DTB read hits -system.cpu.dtb.read_misses 4532 # DTB read misses -system.cpu.dtb.write_accesses 6713398 # DTB write accesses -system.cpu.dtb.write_hits 6712401 # DTB write hits -system.cpu.dtb.write_misses 997 # DTB write misses -system.cpu.icache.ReadReq_accesses::0 41172623 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 41172623 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_hits::0 40741841 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 40741841 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_rate::0 0.010463 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 430782 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 430782 # number of ReadReq misses +system.cpu.dtb.prefetch_faults 775 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 8743013 # DTB read accesses +system.cpu.dtb.read_hits 8738461 # DTB read hits +system.cpu.dtb.read_misses 4552 # DTB read misses +system.cpu.dtb.write_accesses 6788273 # DTB write accesses +system.cpu.dtb.write_hits 6787274 # DTB write hits +system.cpu.dtb.write_misses 999 # DTB write misses +system.cpu.icache.ReadReq_accesses::0 41564629 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 41564629 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_hits::0 41131432 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 41131432 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_rate::0 0.010422 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 433197 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 433197 # number of ReadReq misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 94.576690 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 94.948781 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 41172623 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 41564629 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 41172623 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 41564629 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.icache.demand_hits::0 40741841 # number of demand (read+write) hits +system.cpu.icache.demand_hits::0 41131432 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 40741841 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 41131432 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.010463 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::0 0.010422 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 430782 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 433197 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 430782 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 433197 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses @@ -164,26 +164,26 @@ system.cpu.icache.demand_mshr_misses 0 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.929162 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 475.731149 # Average occupied blocks per context -system.cpu.icache.overall_accesses::0 41172623 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.930040 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 476.180679 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 41564629 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 41172623 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 41564629 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 40741841 # number of overall hits +system.cpu.icache.overall_hits::0 41131432 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 40741841 # number of overall hits +system.cpu.icache.overall_hits::total 41131432 # number of overall hits system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.010463 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.010422 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 430782 # number of overall misses +system.cpu.icache.overall_misses::0 433197 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 430782 # number of overall misses +system.cpu.icache.overall_misses::total 433197 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses @@ -192,15 +192,15 @@ system.cpu.icache.overall_mshr_miss_rate::total no_value system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 430269 # number of replacements -system.cpu.icache.sampled_refs 430781 # Sample count of references to valid blocks. +system.cpu.icache.replacements 432684 # number of replacements +system.cpu.icache.sampled_refs 433196 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 475.731149 # Cycle average of tags in use -system.cpu.icache.total_refs 40741841 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 476.180679 # Cycle average of tags in use +system.cpu.icache.total_refs 41131432 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 4544230000 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 33727 # number of writebacks +system.cpu.icache.writebacks 33708 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 41173750 # DTB accesses +system.cpu.itb.accesses 41565756 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.flush_entries 1478 # Number of entries that have been flushed from TLB @@ -208,9 +208,9 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 41170928 # DTB hits -system.cpu.itb.inst_accesses 41173750 # ITB inst accesses -system.cpu.itb.inst_hits 41170928 # ITB inst hits +system.cpu.itb.hits 41562934 # DTB hits +system.cpu.itb.inst_accesses 41565756 # ITB inst accesses +system.cpu.itb.inst_hits 41562934 # ITB inst hits system.cpu.itb.inst_misses 2822 # ITB inst misses system.cpu.itb.misses 2822 # DTB misses system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions @@ -224,10 +224,10 @@ system.cpu.itb.write_misses 0 # DT system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 51642622 # number of cpu cycles simulated +system.cpu.numCycles 52147236 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 51642622 # Number of busy cycles +system.cpu.num_busy_cycles 52147236 # Number of busy cycles system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 6059 # Number of float alu accesses system.cpu.num_fp_insts 6059 # number of float instructions @@ -235,14 +235,14 @@ system.cpu.num_fp_register_reads 4227 # nu system.cpu.num_fp_register_writes 1834 # number of times the floating registers were written system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 50949504 # Number of instructions executed -system.cpu.num_int_alu_accesses 41395090 # Number of integer alu accesses -system.cpu.num_int_insts 41395090 # number of integer instructions -system.cpu.num_int_register_reads 128438705 # number of times the integer registers were read -system.cpu.num_int_register_writes 33973128 # number of times the integer registers were written -system.cpu.num_load_insts 9082722 # Number of load instructions -system.cpu.num_mem_refs 16092645 # number of memory refs -system.cpu.num_store_insts 7009923 # Number of store instructions +system.cpu.num_insts 51454118 # Number of instructions executed +system.cpu.num_int_alu_accesses 41848094 # Number of integer alu accesses +system.cpu.num_int_insts 41848094 # number of integer instructions +system.cpu.num_int_register_reads 129780130 # number of times the integer registers were read +system.cpu.num_int_register_writes 34330061 # number of times the integer registers were written +system.cpu.num_load_insts 9213901 # Number of load instructions +system.cpu.num_mem_refs 16300106 # number of memory refs +system.cpu.num_store_insts 7086205 # Number of store instructions system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs no_value # Average number of references to valid blocks. @@ -310,61 +310,61 @@ system.iocache.tagsinuse 0 # Cy system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.writebacks 0 # number of writebacks -system.l2c.ReadExReq_accesses::0 169714 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 169714 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_hits::0 60310 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 60310 # number of ReadExReq hits -system.l2c.ReadExReq_miss_rate::0 0.644637 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 109404 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 109404 # number of ReadExReq misses -system.l2c.ReadReq_accesses::0 665898 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 6073 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 671971 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits::0 648226 # number of ReadReq hits -system.l2c.ReadReq_hits::1 6049 # number of ReadReq hits -system.l2c.ReadReq_hits::total 654275 # number of ReadReq hits -system.l2c.ReadReq_miss_rate::0 0.026539 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.003952 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.030491 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 17672 # number of ReadReq misses -system.l2c.ReadReq_misses::1 24 # number of ReadReq misses -system.l2c.ReadReq_misses::total 17696 # number of ReadReq misses -system.l2c.UpgradeReq_accesses::0 1835 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1835 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 170347 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 170347 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_hits::0 60613 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 60613 # number of ReadExReq hits +system.l2c.ReadExReq_miss_rate::0 0.644179 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 109734 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 109734 # number of ReadExReq misses +system.l2c.ReadReq_accesses::0 672769 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 6110 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 678879 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits::0 651602 # number of ReadReq hits +system.l2c.ReadReq_hits::1 6087 # number of ReadReq hits +system.l2c.ReadReq_hits::total 657689 # number of ReadReq hits +system.l2c.ReadReq_miss_rate::0 0.031463 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.003764 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.035227 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 21167 # number of ReadReq misses +system.l2c.ReadReq_misses::1 23 # number of ReadReq misses +system.l2c.ReadReq_misses::total 21190 # number of ReadReq misses +system.l2c.UpgradeReq_accesses::0 1839 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1839 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_hits::0 17 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 17 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_rate::0 0.990736 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 1818 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1818 # number of UpgradeReq misses -system.l2c.Writeback_accesses::0 412752 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 412752 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 412752 # number of Writeback hits -system.l2c.Writeback_hits::total 412752 # number of Writeback hits +system.l2c.UpgradeReq_miss_rate::0 0.990756 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 1822 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1822 # number of UpgradeReq misses +system.l2c.Writeback_accesses::0 415575 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 415575 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 415575 # number of Writeback hits +system.l2c.Writeback_hits::total 415575 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 6.885433 # Average number of references to valid blocks. +system.l2c.avg_refs 6.741439 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 835612 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 6073 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 841685 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 843116 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 6110 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 849226 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.demand_hits::0 708536 # number of demand (read+write) hits -system.l2c.demand_hits::1 6049 # number of demand (read+write) hits -system.l2c.demand_hits::total 714585 # number of demand (read+write) hits +system.l2c.demand_hits::0 712215 # number of demand (read+write) hits +system.l2c.demand_hits::1 6087 # number of demand (read+write) hits +system.l2c.demand_hits::total 718302 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.152075 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.003952 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.156027 # miss rate for demand accesses -system.l2c.demand_misses::0 127076 # number of demand (read+write) misses -system.l2c.demand_misses::1 24 # number of demand (read+write) misses -system.l2c.demand_misses::total 127100 # number of demand (read+write) misses +system.l2c.demand_miss_rate::0 0.155259 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.003764 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.159023 # miss rate for demand accesses +system.l2c.demand_misses::0 130901 # number of demand (read+write) misses +system.l2c.demand_misses::1 23 # number of demand (read+write) misses +system.l2c.demand_misses::total 130924 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses @@ -374,28 +374,28 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.072507 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.478199 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 4751.792305 # Average occupied blocks per context -system.l2c.occ_blocks::1 31339.221407 # Average occupied blocks per context -system.l2c.overall_accesses::0 835612 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 6073 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 841685 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.076407 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.476934 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 5007.401793 # Average occupied blocks per context +system.l2c.occ_blocks::1 31256.365097 # Average occupied blocks per context +system.l2c.overall_accesses::0 843116 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 6110 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 849226 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits::0 708536 # number of overall hits -system.l2c.overall_hits::1 6049 # number of overall hits -system.l2c.overall_hits::total 714585 # number of overall hits +system.l2c.overall_hits::0 712215 # number of overall hits +system.l2c.overall_hits::1 6087 # number of overall hits +system.l2c.overall_hits::total 718302 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.152075 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.003952 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.156027 # miss rate for overall accesses -system.l2c.overall_misses::0 127076 # number of overall misses -system.l2c.overall_misses::1 24 # number of overall misses -system.l2c.overall_misses::total 127100 # number of overall misses +system.l2c.overall_miss_rate::0 0.155259 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.003764 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.159023 # miss rate for overall accesses +system.l2c.overall_misses::0 130901 # number of overall misses +system.l2c.overall_misses::1 23 # number of overall misses +system.l2c.overall_misses::total 130924 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses @@ -404,12 +404,12 @@ system.l2c.overall_mshr_miss_rate::total 0 # ms system.l2c.overall_mshr_misses 0 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 95922 # number of replacements -system.l2c.sampled_refs 125830 # Sample count of references to valid blocks. +system.l2c.replacements 97028 # number of replacements +system.l2c.sampled_refs 129660 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 36091.013712 # Cycle average of tags in use -system.l2c.total_refs 866394 # Total number of references to valid blocks. +system.l2c.tagsinuse 36263.766890 # Cycle average of tags in use +system.l2c.total_refs 874095 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 90126 # number of writebacks +system.l2c.writebacks 90970 # number of writebacks ---------- End Simulation Statistics ---------- diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index 4fad32362..49b04d190 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -7,11 +7,11 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem -children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus +children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver boot_cpu_frequency=500 boot_osflags=earlyprintk mem=128MB console=ttyAMA0 lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm +kernel=/chips/pd/randd/dist/binaries/vmlinux.arm load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -164,7 +164,7 @@ type=ExeTracer [system.diskmem] type=PhysicalMemory -file=/dist/m5/system/disks/ael-arm.ext2 +file=/chips/pd/randd/dist/disks/ael-arm.ext2 latency=30000 latency_var=0 null=false @@ -184,7 +184,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side system.realview.clcd.dma +port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.realview.cf0_fake.pio system.iocache.cpu_side system.realview.clcd.dma [system.iocache] type=BaseCache @@ -214,7 +214,7 @@ tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.iobus.port[24] +cpu_side=system.iobus.port[25] mem_side=system.membus.port[5] [system.l2c] @@ -288,7 +288,7 @@ port=system.membus.port[1] [system.realview] type=RealView -children=aaci_fake clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=aaci_fake cf0_fake clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake intrctrl=system.intrctrl system=system @@ -302,6 +302,22 @@ platform=system.realview system=system pio=system.iobus.port[20] +[system.realview.cf0_fake] +type=IsaFake +pio_addr=402653184 +pio_latency=1000 +pio_size=4095 +platform=system.realview +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[24] + [system.realview.clcd] type=Pl111 amba_id=1315089 @@ -314,7 +330,8 @@ pio_addr=268566528 pio_latency=10000 platform=system.realview system=system -dma=system.iobus.port[25] +vnc=system.vncserver +dma=system.iobus.port[26] pio=system.iobus.port[5] [system.realview.dmac_fake] @@ -388,24 +405,28 @@ pio=system.iobus.port[17] type=Pl050 amba_id=1314896 gic=system.realview.gic -int_delay=100000 +int_delay=1000000 int_num=52 +is_mouse=false pio_addr=268460032 pio_latency=1000 platform=system.realview system=system +vnc=system.vncserver pio=system.iobus.port[6] [system.realview.kmi1] type=Pl050 amba_id=1314896 gic=system.realview.gic -int_delay=100000 +int_delay=1000000 int_num=53 +is_mouse=true pio_addr=268464128 pio_latency=1000 platform=system.realview system=system +vnc=system.vncserver pio=system.iobus.port[7] [system.realview.l2x0_fake] @@ -591,3 +612,8 @@ use_default_range=false width=64 port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.vncserver] +type=VncServer +number=0 +port=5900 + diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr index e76a50eec..1cff4671c 100755 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr @@ -1,3 +1,5 @@ +warn: Sockets disabled, not accepting vnc client connections +For more information see: http://www.m5sim.org/warn/af6a84f6 warn: Sockets disabled, not accepting terminal connections For more information see: http://www.m5sim.org/warn/8742226b warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index 994dfb6a2..2a456e7be 100755 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:53:13 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:53:26 -M5 executing on burrito +M5 compiled Feb 11 2011 17:53:57 +M5 revision 6c65f7ee86c1 7949 default qtip tip ext/vnc_stats_updates.patch +M5 started Feb 11 2011 17:54:00 +M5 executing on u200439-lin.austin.arm.com command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm +info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 114721074000 because m5_exit instruction encountered +Exiting @ tick 114726567000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 85fb99220..c96422cfa 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,254 +1,254 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 433208 # Simulator instruction rate (inst/s) -host_mem_usage 360908 # Number of bytes of host memory used -host_seconds 116.74 # Real time elapsed on the host -host_tick_rate 982709659 # Simulator tick rate (ticks/s) +host_inst_rate 1425483 # Simulator instruction rate (inst/s) +host_mem_usage 374960 # Number of bytes of host memory used +host_seconds 35.49 # Real time elapsed on the host +host_tick_rate 3232752918 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 50572425 # Number of instructions simulated -sim_seconds 0.114721 # Number of seconds simulated -sim_ticks 114721074000 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses::0 100214 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 100214 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15147.115385 # average LoadLockedReq miss latency +sim_insts 50588397 # Number of instructions simulated +sim_seconds 0.114727 # Number of seconds simulated +sim_ticks 114726567000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses::0 100290 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 100290 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14562.978560 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 12147.115385 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11562.978560 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency -system.cpu.dcache.LoadLockedReq_hits::0 95014 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 95014 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 78765000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.051889 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 5200 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 5200 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 63165000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.051889 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_hits::0 95066 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 95066 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 76077000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.052089 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 5224 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 5224 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 60405000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.052089 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 5200 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_uncacheable_latency 310267000 # number of LoadLockedReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_accesses::0 7824780 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 7824780 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 15798.342892 # average ReadReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses 5224 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_uncacheable_latency 310532000 # number of LoadLockedReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_accesses::0 7828656 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 7828656 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 15679.539912 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12798.015358 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12679.195749 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 7588163 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7588163 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3738156500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.030239 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 236617 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 236617 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3028228000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030239 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_hits::0 7590397 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7590397 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3735791500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.030434 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 238259 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 238259 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3020932500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030434 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 236617 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38190415500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses::0 100213 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 100213 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::0 100213 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 100213 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::0 6671860 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6671860 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 40836.063764 # average WriteReq miss latency +system.cpu.dcache.ReadReq_mshr_misses 238259 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38191771500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses::0 100289 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 100289 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::0 100289 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 100289 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses::0 6674369 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6674369 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 40728.962545 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37835.781907 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37728.712808 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 6499787 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6499787 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 7026784000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.025791 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 172073 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 172073 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 6510516500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025791 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_hits::0 6502188 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6502188 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 7012753500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.025797 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 172181 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 172181 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 6496167500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025797 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 172073 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 926046500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_misses 172181 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 927436000 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 34.660375 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 34.529769 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 14496640 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 14503025 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 14496640 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 26340.112310 # average overall miss latency +system.cpu.dcache.demand_accesses::total 14503025 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 26187.859370 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23339.804008 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 14087950 # number of demand (read+write) hits +system.cpu.dcache.demand_avg_mshr_miss_latency 23187.554819 # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 14092585 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 14087950 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10764940500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.028192 # miss rate for demand accesses +system.cpu.dcache.demand_hits::total 14092585 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 10748545000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.028300 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 408690 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 410440 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 408690 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 410440 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9538744500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.028192 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency 9517100000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.028300 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 408690 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 410440 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.994530 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 509.199113 # Average occupied blocks per context -system.cpu.dcache.overall_accesses::0 14496640 # number of overall (read+write) accesses +system.cpu.dcache.occ_blocks::0 509.199247 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 14503025 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 14496640 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 26340.112310 # average overall miss latency +system.cpu.dcache.overall_accesses::total 14503025 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 26187.859370 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23339.804008 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23187.554819 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 14087950 # number of overall hits +system.cpu.dcache.overall_hits::0 14092585 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 14087950 # number of overall hits -system.cpu.dcache.overall_miss_latency 10764940500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.028192 # miss rate for overall accesses +system.cpu.dcache.overall_hits::total 14092585 # number of overall hits +system.cpu.dcache.overall_miss_latency 10748545000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.028300 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 408690 # number of overall misses +system.cpu.dcache.overall_misses::0 410440 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 408690 # number of overall misses +system.cpu.dcache.overall_misses::total 410440 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9538744500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.028192 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency 9517100000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.028300 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 408690 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 39116462000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_misses 410440 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 39119207500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 411628 # number of replacements -system.cpu.dcache.sampled_refs 412140 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 413327 # number of replacements +system.cpu.dcache.sampled_refs 413839 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 509.199113 # Cycle average of tags in use -system.cpu.dcache.total_refs 14284927 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 509.199247 # Cycle average of tags in use +system.cpu.dcache.total_refs 14289765 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 658097000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 382676 # number of writebacks -system.cpu.dtb.accesses 15524935 # DTB accesses +system.cpu.dcache.writebacks 381698 # number of writebacks +system.cpu.dtb.accesses 15531532 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 2199 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 2220 # Number of entries that have been flushed from TLB system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 15519414 # DTB hits +system.cpu.dtb.hits 15525999 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 5521 # DTB misses +system.cpu.dtb.misses 5533 # DTB misses system.cpu.dtb.perms_faults 255 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 756 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 8740303 # DTB read accesses -system.cpu.dtb.read_hits 8735762 # DTB read hits -system.cpu.dtb.read_misses 4541 # DTB read misses -system.cpu.dtb.write_accesses 6784632 # DTB write accesses -system.cpu.dtb.write_hits 6783652 # DTB write hits -system.cpu.dtb.write_misses 980 # DTB write misses -system.cpu.icache.ReadReq_accesses::0 41543801 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 41543801 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 14800.791885 # average ReadReq miss latency +system.cpu.dtb.prefetch_faults 757 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 8744287 # DTB read accesses +system.cpu.dtb.read_hits 8739733 # DTB read hits +system.cpu.dtb.read_misses 4554 # DTB read misses +system.cpu.dtb.write_accesses 6787245 # DTB write accesses +system.cpu.dtb.write_hits 6786266 # DTB write hits +system.cpu.dtb.write_misses 979 # DTB write misses +system.cpu.icache.ReadReq_accesses::0 41555414 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 41555414 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14790.398445 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11799.492843 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11789.103925 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_hits::0 41110405 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 41110405 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 6414604000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.010432 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 433396 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 433396 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 5113853000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.010432 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_hits::0 41121276 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 41121276 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 6421074000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.010447 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 434138 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 434138 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 5118098000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.010447 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 433396 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 434138 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable_latency 349111000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 94.856667 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 94.719366 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 41543801 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 41555414 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 41543801 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 14800.791885 # average overall miss latency +system.cpu.icache.demand_accesses::total 41555414 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14790.398445 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11799.492843 # average overall mshr miss latency -system.cpu.icache.demand_hits::0 41110405 # number of demand (read+write) hits +system.cpu.icache.demand_avg_mshr_miss_latency 11789.103925 # average overall mshr miss latency +system.cpu.icache.demand_hits::0 41121276 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 41110405 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 6414604000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.010432 # miss rate for demand accesses +system.cpu.icache.demand_hits::total 41121276 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 6421074000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.010447 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 433396 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 434138 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 433396 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 434138 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 5113853000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.010432 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency 5118098000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.010447 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 433396 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 434138 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.945788 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 484.243503 # Average occupied blocks per context -system.cpu.icache.overall_accesses::0 41543801 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.946115 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 484.411008 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 41555414 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 41543801 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 14800.791885 # average overall miss latency +system.cpu.icache.overall_accesses::total 41555414 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14790.398445 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11799.492843 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11789.103925 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 41110405 # number of overall hits +system.cpu.icache.overall_hits::0 41121276 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 41110405 # number of overall hits -system.cpu.icache.overall_miss_latency 6414604000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.010432 # miss rate for overall accesses +system.cpu.icache.overall_hits::total 41121276 # number of overall hits +system.cpu.icache.overall_miss_latency 6421074000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.010447 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 433396 # number of overall misses +system.cpu.icache.overall_misses::0 434138 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 433396 # number of overall misses +system.cpu.icache.overall_misses::total 434138 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 5113853000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.010432 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency 5118098000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.010447 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 433396 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 434138 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 349111000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 432883 # number of replacements -system.cpu.icache.sampled_refs 433395 # Sample count of references to valid blocks. +system.cpu.icache.replacements 433626 # number of replacements +system.cpu.icache.sampled_refs 434138 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 484.243503 # Cycle average of tags in use -system.cpu.icache.total_refs 41110405 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 484.411008 # Cycle average of tags in use +system.cpu.icache.total_refs 41121276 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 14253306000 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 33555 # number of writebacks +system.cpu.icache.writebacks 34007 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 41546620 # DTB accesses +system.cpu.itb.accesses 41558233 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.flush_entries 1478 # Number of entries that have been flushed from TLB @@ -256,9 +256,9 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 41543801 # DTB hits -system.cpu.itb.inst_accesses 41546620 # ITB inst accesses -system.cpu.itb.inst_hits 41543801 # ITB inst hits +system.cpu.itb.hits 41555414 # DTB hits +system.cpu.itb.inst_accesses 41558233 # ITB inst accesses +system.cpu.itb.inst_hits 41555414 # ITB inst hits system.cpu.itb.inst_misses 2819 # ITB inst misses system.cpu.itb.misses 2819 # DTB misses system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions @@ -272,10 +272,10 @@ system.cpu.itb.write_misses 0 # DT system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 229442148 # number of cpu cycles simulated +system.cpu.numCycles 229453134 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 229442148 # Number of busy cycles +system.cpu.num_busy_cycles 229453134 # Number of busy cycles system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 6058 # Number of float alu accesses system.cpu.num_fp_insts 6058 # number of float instructions @@ -283,14 +283,14 @@ system.cpu.num_fp_register_reads 4226 # nu system.cpu.num_fp_register_writes 1834 # number of times the floating registers were written system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 50572425 # Number of instructions executed -system.cpu.num_int_alu_accesses 41827211 # Number of integer alu accesses -system.cpu.num_int_insts 41827211 # number of integer instructions -system.cpu.num_int_register_reads 137988684 # number of times the integer registers were read -system.cpu.num_int_register_writes 34313952 # number of times the integer registers were written -system.cpu.num_load_insts 9208240 # Number of load instructions -system.cpu.num_mem_refs 16289993 # number of memory refs -system.cpu.num_store_insts 7081753 # Number of store instructions +system.cpu.num_insts 50588397 # Number of instructions executed +system.cpu.num_int_alu_accesses 41841366 # Number of integer alu accesses +system.cpu.num_int_insts 41841366 # number of integer instructions +system.cpu.num_int_register_reads 138034734 # number of times the integer registers were read +system.cpu.num_int_register_writes 34325875 # number of times the integer registers were written +system.cpu.num_load_insts 9211791 # Number of load instructions +system.cpu.num_mem_refs 16296219 # number of memory refs +system.cpu.num_store_insts 7084428 # Number of store instructions system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs no_value # Average number of references to valid blocks. @@ -359,141 +359,141 @@ system.iocache.total_refs 0 # To system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.writebacks 0 # number of writebacks system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency -system.l2c.LoadLockedReq_mshr_uncacheable_latency 234160000 # number of LoadLockedReq MSHR uncacheable cycles -system.l2c.ReadExReq_accesses::0 170323 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 170323 # number of ReadExReq accesses(hits+misses) +system.l2c.LoadLockedReq_mshr_uncacheable_latency 234360000 # number of LoadLockedReq MSHR uncacheable cycles +system.l2c.ReadExReq_accesses::0 170356 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 170356 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_avg_miss_latency::0 52000 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 62071 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 62071 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 5629104000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.635569 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 108252 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 108252 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 4330080000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 0.635569 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_hits::0 62546 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 62546 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 5606120000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.632851 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 107810 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 107810 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 4312400000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 0.632851 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 108252 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 673101 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 5652 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 678753 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52096.523258 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 28127657.142857 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 28179753.666115 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 107810 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 675489 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 5600 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 681089 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52080.437900 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 33725803.571429 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 33777884.009328 # average ReadReq miss latency system.l2c.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 654204 # number of ReadReq hits -system.l2c.ReadReq_hits::1 5617 # number of ReadReq hits -system.l2c.ReadReq_hits::total 659821 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 984468000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.028075 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.006192 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.034267 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 18897 # number of ReadReq misses -system.l2c.ReadReq_misses::1 35 # number of ReadReq misses -system.l2c.ReadReq_misses::total 18932 # number of ReadReq misses -system.l2c.ReadReq_mshr_miss_latency 757280000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.028127 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 3.349611 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 3.377737 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 18932 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 29199338000 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses::0 1750 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1750 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 660.126947 # average UpgradeReq miss latency +system.l2c.ReadReq_hits::0 657357 # number of ReadReq hits +system.l2c.ReadReq_hits::1 5572 # number of ReadReq hits +system.l2c.ReadReq_hits::total 662929 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 944322500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.026843 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.005000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.031843 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 18132 # number of ReadReq misses +system.l2c.ReadReq_misses::1 28 # number of ReadReq misses +system.l2c.ReadReq_misses::total 18160 # number of ReadReq misses +system.l2c.ReadReq_mshr_miss_latency 726400000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.026884 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 3.242857 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 3.269741 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 18160 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 29200446000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses::0 1825 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1825 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 489.208633 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_hits::0 17 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 17 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_latency 1144000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 0.990286 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 1733 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1733 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 69320000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 0.990286 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_hits::0 18 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 18 # number of UpgradeReq hits +system.l2c.UpgradeReq_miss_latency 884000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate::0 0.990137 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 1807 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1807 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 72280000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 0.990137 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 1733 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 1807 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 739844000 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 416231 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 416231 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 416231 # number of Writeback hits -system.l2c.Writeback_hits::total 416231 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 740884000 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 415705 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 415705 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 415705 # number of Writeback hits +system.l2c.Writeback_hits::total 415705 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 6.975292 # Average number of references to valid blocks. +system.l2c.avg_refs 7.060757 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 843424 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 5652 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 849076 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 52014.345374 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 188959200 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 189011214.345374 # average overall miss latency +system.l2c.demand_accesses::0 845845 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 5600 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 851445 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52011.580728 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 233944375 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 233996386.580728 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.l2c.demand_hits::0 716275 # number of demand (read+write) hits -system.l2c.demand_hits::1 5617 # number of demand (read+write) hits -system.l2c.demand_hits::total 721892 # number of demand (read+write) hits -system.l2c.demand_miss_latency 6613572000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.150753 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.006192 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.156946 # miss rate for demand accesses -system.l2c.demand_misses::0 127149 # number of demand (read+write) misses -system.l2c.demand_misses::1 35 # number of demand (read+write) misses -system.l2c.demand_misses::total 127184 # number of demand (read+write) misses +system.l2c.demand_hits::0 719903 # number of demand (read+write) hits +system.l2c.demand_hits::1 5572 # number of demand (read+write) hits +system.l2c.demand_hits::total 725475 # number of demand (read+write) hits +system.l2c.demand_miss_latency 6550442500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.148895 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.005000 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.153895 # miss rate for demand accesses +system.l2c.demand_misses::0 125942 # number of demand (read+write) misses +system.l2c.demand_misses::1 28 # number of demand (read+write) misses +system.l2c.demand_misses::total 125970 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 5087360000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.150795 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 22.502477 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 22.653272 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 127184 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_miss_latency 5038800000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.148928 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 22.494643 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 22.643571 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 125970 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.086431 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.477933 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 5664.361976 # Average occupied blocks per context -system.l2c.occ_blocks::1 31321.847814 # Average occupied blocks per context -system.l2c.overall_accesses::0 843424 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 5652 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 849076 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 52014.345374 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 188959200 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 189011214.345374 # average overall miss latency +system.l2c.occ_%::0 0.081481 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.477898 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 5339.953820 # Average occupied blocks per context +system.l2c.occ_blocks::1 31319.548737 # Average occupied blocks per context +system.l2c.overall_accesses::0 845845 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 5600 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 851445 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52011.580728 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 233944375 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 233996386.580728 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 716275 # number of overall hits -system.l2c.overall_hits::1 5617 # number of overall hits -system.l2c.overall_hits::total 721892 # number of overall hits -system.l2c.overall_miss_latency 6613572000 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.150753 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.006192 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.156946 # miss rate for overall accesses -system.l2c.overall_misses::0 127149 # number of overall misses -system.l2c.overall_misses::1 35 # number of overall misses -system.l2c.overall_misses::total 127184 # number of overall misses +system.l2c.overall_hits::0 719903 # number of overall hits +system.l2c.overall_hits::1 5572 # number of overall hits +system.l2c.overall_hits::total 725475 # number of overall hits +system.l2c.overall_miss_latency 6550442500 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.148895 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.005000 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.153895 # miss rate for overall accesses +system.l2c.overall_misses::0 125942 # number of overall misses +system.l2c.overall_misses::1 28 # number of overall misses +system.l2c.overall_misses::total 125970 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 5087360000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.150795 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 22.502477 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 22.653272 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 127184 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 29939182000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency 5038800000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.148928 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 22.494643 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 22.643571 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 125970 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 29941330000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 94170 # number of replacements -system.l2c.sampled_refs 125831 # Sample count of references to valid blocks. +system.l2c.replacements 93233 # number of replacements +system.l2c.sampled_refs 124676 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 36986.209790 # Cycle average of tags in use -system.l2c.total_refs 877708 # Total number of references to valid blocks. +system.l2c.tagsinuse 36659.502556 # Cycle average of tags in use +system.l2c.total_refs 880307 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 87626 # number of writebacks +system.l2c.writebacks 87349 # number of writebacks ---------- End Simulation Statistics ---------- diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal Binary files differindex f3053783c..3921585df 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal |