summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2014-04-01cpu: Fix case where o3 lsq could print out uninitialized dataMitch Hayenga
In the O3 LSQ, data read/written is printed out in DPRINTFs. However, the data field is treated as a character string with a null terminated. However the data field is not encoded this way. This patch removes that possibility by removing the data part of the print.
2014-04-01mem: Don't print out the data of a cache blockMitch Hayenga
This never actually worked since it was printing out only a word of the cache block and not the entire thing and doubly didn't work csprintf overrides the %#x specifier and assumes a char* array is actually a string.
2014-04-23arm: Don't use a stack allocated mnemonicMitchell Hayenga
FailUnimplemented passed a stack created mnemonic as a const char * which causes some grief when the stack goes away.
2014-04-23cpu: Add O3 CPU width checksDam Sunwoo
O3CPU has a compile-time maximum width set in o3/impl.hh, but checking the configuration against this limit was not implemented anywhere except for fetch. Configuring a wider pipe than the limit can silently cause various issues during the simulation. This patch adds the proper checking in the constructor of the various pipeline stages.
2014-04-23base: explicitly suggest potential use of 'All' debug flagsCurtis Dunham
Without this declaration, new clangs will complain about this value being unused. It has no explicit use in the codebase, but it can be useful to turn on all debugging flags while in a debugger to greatly increase simulator verbosity.
2014-04-23arch: remove 'null update' check in isa-parserCurtis Dunham
SCons already does this for all build steps.
2014-02-10stats: better error message for uninitialized statisticCurtis Dunham
As suggested by Nathan Binkert in 2008: http://permalink.gmane.org/gmane.comp.emulators.m5.users/2676
2014-04-22stats: updates for pc-switcheroo-full due to o3 smt fixAndreas Hansson
2014-04-19stats: updates due to o3 smt fixNilay Vaish
+ changes to one ruby regression config.ini file.
2014-04-19ruby: slicc: remove old documentationNilay Vaish
Has not been maintained at all. Since there is alternate documentation available on gem5.org, no need to have this separately.
2014-04-19ruby: slicc: slight change to rule for transitionsNilay Vaish
It had an unnecessary pairs token which is being removed.
2014-04-19o3: Fix occupancy checks for SMTFaissal Sleiman
A number of calls to isEmpty() and numFreeEntries() should be thread-specific. In cpu.cc, the fact that tid is /*commented*/ out is a bug. Say the rob has instructions from thread 0 (isEmpty() returns false), and none from thread 1. If we are trying to squash all of thread 1, then readTailInst(thread 1) will be called because rob->isEmpty() returns false. The result is end_it is not in the list and the while statement loops indefinitely back over the cpu's instList. In iew_impl.hh, all threads are told they have the entire remaining IQ, when each thread actually has a certain allocation. The result is extra stalls at the iew dispatch stage which the rename stage usually takes care of. In commit_impl.hh, rob->readHeadInst(thread 1) can be called if the rob only contains instructions from thread 0. This returns a dummyInst (which may work since we are trying to squash all instructions, but hardly seems like the right way to do it). In rob_impl.hh this fix skips the rest of the function more frequently and is more efficient. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-04-19ruby: recorder: Fix (de-)serializing with different cache block-sizesMarco Elver
Upon aggregating records, serialize system's cache-block size, as the cache-block size can be different when restoring from a checkpoint. This way, we can correctly read all records when restoring from a checkpoints, even if the cache-block size is different. Note, that it is only possible to restore from a checkpoint if the desired cache-block size is smaller or equal to the cache-block size when the checkpoint was taken; we can split one larger request into multiple small ones, but it is not reliable to do the opposite. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-04-19config: ruby: remove memory controller from network testNilay Vaish
It is not in use and not required as such.
2014-04-14arm: set default kernels for VExpress_EMM and VExpress_EMM64Anthony Gutierrez
2014-04-13scons: Fix python-config parsing by adding strip()Andreas Hansson
This patch fixes an issue with the way the python-config path is parsed, as it caused issues on systems where a newline ended up being included in the path.
2014-04-10config: add num-work-ids command line optionGedare Bloom
Adds the parameter --num-work-ids to Options.py and reads the parameter into the System params in Simulation.py. This parameter enables setting the number of possible work items to different than 16. Support for this parameter already exists in src/sim/System.py, so this changeset only affects the Python config files. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-04-10scons: compile on systems where python2 and python3 co-existStian Hvatum
Compile gem5 on systems where python2 and python3 co-exists without any changes in path. python2-config is chosen over python-config if it exists. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-04-09kvm, x86: Add initial support for multicore simulationAndreas Sandberg
Simulating a SMP or multicore requires devices to be shared between multiple KVM vCPUs. This means that locking is required when accessing devices. This changeset adds the necessary locking to allow devices to execute correctly. It is implemented by temporarily migrating the KVM CPU to the VM's (and devices) event queue when handling MMIO. Similarly, the VM migrates to the interrupt controller's event queue when delivering an interrupt. The support for fast-forwarding of multicore simulations added by this changeset assumes that all devices in a system are simulated in the same thread and each vCPU has its own thread. Special care must be taken to ensure that devices living under the CPU in the object hierarchy (e.g., the interrupt controller) do not inherit the parent CPUs thread and are assigned to device thread. The KvmVM object is assumed to live in the same thread as the other devices in the system.
2014-04-09dev: Protect PollEvent processing when running in parallel modeAndreas Sandberg
The calling thread is undefined when the PollQueue services events. This implies that PollEvents need to handle the case where they are processed from a different thread than the thread that created the event. This changeset adds temporary event queue migrations to the VNC server, the ethernet tap device, and the terminal to protect them from inter-thread calls.
2014-04-08ruby: slicc: change enqueue statementNilay Vaish
As of now, the enqueue statement can take in any number of 'pairs' as argument. But we only use the pair in which latency is the key. This latency is allowed to be either a fixed integer or a member variable of controller in which the expression appears. This patch drops the use of pairs in an enqueue statement. Instead, an expression is allowed which will be interpreted to be the latency of the enqueue. This expression can anything allowed by slicc including a constant integer or a member variable.
2014-04-08ruby: coherence protocols: drop the phrase IntraChipNilay Vaish
The phrase is no longer valid since we do not distinguish between inter and intra chip communication.
2014-04-03sim: Add the ability to lock and migrate between event queuesAndreas Sandberg
We need the ability to lock event queues to enable device accesses across threads. The serviceOne() method now takes a service lock prior to handling a new event. By locking an event queue, a different thread/eq can effectively execute in the context of the locked event queue. To simplify temporary event queue migrations, this changeset introduces the EventQueue::ScopedMigration class that unlocks the current event queue, locks a new event queue, and updates the current event queue variable. In order to prevent deadlocks, event queues need to be released when waiting on barriers. This is implemented using the EventQueue::ScopedRelease class. An instance of this class is, for example, used in the BaseGlobalEvent class to release the event queue when waiting on the synchronization barrier. The intended use for this functionality is when devices need to be accessed across thread boundaries. For example, when fast-forwarding, it might be useful to run devices and CPUs in separate threads. In such a case, the CPU locks the device queue whenever it needs to perform IO. This functionality is primarily intended for KVM. Note: Migrating between event queues can lead to non-deterministic timing. Use with extreme care! --HG-- extra : rebase_source : 23e3a741a1fd73861d1339782dbbe1bc76285315
2014-04-01ext: add McPAT sourceAnthony Gutierrez
this patch adds the source for mcpat, a power, area, and timing modeling framework.
2014-04-01arm: fix typos in makefile for ARM m5 util and link staticallyAnthony Gutierrez
1) fixes a typo for clean target libgemOpJni.so -> libgem5OpJni.so 2) addes jni_gem5Op.h to clean since it is added during make 3) links the m5 utility statically since it won't work on some images otherwise
2014-04-01configs: use SimpleMemory when using ruby in se modeNilay Vaish
A recent changeset altered the default memory class to DRAMCtrl. In se mode, ruby uses the physical memory to check if a given address is within the bounds of the physical memory. SimpleMemory is enough for this. Moreover, SimpleMemory does not check whether it is connected or not, something which DRAMCtrl does.
2014-03-25cpu: o3: lsq: Fix TSO implementationMarco Elver
This patch fixes violation of TSO in the O3CPU, as all loads must be ordered with all other loads. In the LQ, if a snoop is observed, all subsequent loads need to be squashed if the system is TSO. Prior to this patch, the following case could be violated: P0 | P1 ; MOV [x],mail=/usr/spool/mail/nilay | MOV EAX,[y] ; MOV [y],mail=/usr/spool/mail/nilay | MOV EBX,[x] ; exists (1:EAX=1 /\ 1:EBX=0) [is a violation] The problem was found using litmus [http://diy.inria.fr]. Committed by: Nilay Vaish <nilay@cs.wisc.edu
2014-03-23stats: Update stats for DRAM changesAndreas Hansson
This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23mem: Track DRAM read/write switching and add hysteresisAndreas Hansson
This patch adds stats for tracking the number of reads/writes per bus turn around, and also adds hysteresis to the write-to-read switching to ensure that the queue does not oscilate around the low threshold.
2014-03-23mem: Rename SimpleDRAM to a more suitable DRAMCtrlAndreas Hansson
This patch renames the not-so-simple SimpleDRAM to a more suitable DRAMCtrl. The name change is intended to ensure that we do not send the wrong message (although the "simple" in SimpleDRAM was originally intended as in cleverly simple, or elegant). As the DRAM controller modelling work is being presented at ISPASS'14 our hope is that a broader audience will use the model in the future. --HG-- rename : src/mem/SimpleDRAM.py => src/mem/DRAMCtrl.py rename : src/mem/simple_dram.cc => src/mem/dram_ctrl.cc rename : src/mem/simple_dram.hh => src/mem/dram_ctrl.hh
2014-03-23mem: Change memory defaults to be more representativeAndreas Hansson
Make the default memory type DDR3-1600 x64, and use the open-adaptive page policy. This change is aiming to ensure that users by default are using a realistic memory system.
2014-03-23mem: Add close adaptive paging policy to DRAM controller modelWendy Elsasser
This patch adds a second adaptive page policy to the DRAM controller, closing the page unless there are already queued accesses to the open page.
2014-03-23mem: DRAM controller tidying upAndreas Hansson
Minor tidying up and removing of redundant code, including the printing of queue state every million accesses.
2014-03-23mem: Fix bug in DRAM bytes per activateAndreas Hansson
This patch ensures that we do not sample the bytes per activate when the row has already been closed.
2014-03-23mem: Limit the accesses to a page before forcing a prechargeAndreas Hansson
This patch adds a basic starvation-prevention mechanism where a DRAM page is forced to close after a certain number of accesses. The limit is combined with the open and open-adaptive page policy and if reached causes an auto-precharge.
2014-03-23mem: Make DRAM write queue draining more aggressiveAndreas Hansson
This patch changes the triggering condition for the write draining such that we grab the opportunity to issue writes if there are no reads waiting (as opposed to waiting for the writes to reach the high threshold). As a result, we potentially drain some of the writes in read idle periods (if any). A low threshold is added to be able to control how many write bursts are kept in the memory controller queue (acting as on-chip storage). The high and low thresholds are updated to sensible values for a 32/64 size write buffer. Note that the thresholds should be adjusted along with the queue sizes. This patch also adds some basic initialisation sanity checks and moves part of the initialisation to the constructor.
2014-03-23config: Add a DRAM efficiency-sweep scriptAndreas Hansson
This patch adds a configuration that simplifies evaluation of DRAM controller configurations by automating a sweep of stride size and bank parallelism. It works in a rather unconventional way, as it needs to print the traffic generator stimuli based on the memory organisation. Hence, it starts by configuring the memory, then it prints a traffic-generator config file, and loads it. The resulting stats have one period per data point, identified by the stride size, and the number of banks being used.
2014-03-23cpu: DRAM Traffic GeneratorNeha Agarwal
This patch enables a new 'DRAM' mode to the existing traffic generator, catered to generate specific requests to DRAM based on required hit length (stride size) and bank utilization. It is an add on to the Random mode. The basic idea is to control how many successive packets target the same page, and how many banks are being used in parallel. This gives a two-dimensional space that stresses different aspects of the DRAM timing. The configuration file needed to use this patch has to be changed as follow: (reference to Random Mode, LPDDR3 memory type) 'STATE 0 10000000000 RANDOM 50 0 134217728 64 3004 5002 0' -> 'STATE 0 10000000000 DRAM 50 0 134217728 32 3004 5002 0 96 1024 8 6 1' The last 4 parameters to be added are: <stride size (bytes), page size(bytes), number of banks available in DRAM, number of banks to be utilized, address mapping scheme> The address mapping information is used to get the stride address stream of the specified size and to know where to find the bank bits. The configuration file has a parameter where '0'-> RoCoRaBaCh, '1'-> RoRaBaCoCh/RoRaBaChCo address-mapping schemes. Note that the generator currently assumes a single channel and a single rank. This is to avoid overwhelming the traffic generator with information about the memory organisation.
2014-03-23mem: DDR3 config for comparing with DRAMSim2Neha Agarwal
This patch adds a new DDR3 configuration to match with the parameters that are specified in one of the DDR3 configs used in DRAMSim2.
2014-03-23mem: More descriptive address-mapping scheme namesAndreas Hansson
This patch adds the row bits to the name of the address mapping schemes to make it more clear that all the current schemes places the row bits as the most significant bits.
2014-03-23scons: Shush sconsCurtis Dunham
make 'scons -s' actually silent.
2014-03-23misc: Fix -q (quiet) flagStan Czerniawski
Check the right flag.
2014-03-23ruby: Move Ruby debug flags to ruby dir and remove stale optionsAndreas Hansson
This patch moves the Ruby-related debug flags to the ruby sub-directory, and also removes the state SConsopts that add the no-longer-used NO_VECTOR_BOUNDS_CHECK.
2014-03-23util: Add support for detection of gzipped packet tracesAndreas Hansson
This patch adds support for automatically detecting a gzipped packet trace, thus accepting either a compressed or uncompressed trace.
2014-03-23mem: Include the DRAMSim2 wrapper in NULL buildAndreas Hansson
This patch makes sure DRAMSim2 is included in a build of the NULL ISA.
2014-03-23ext: Fix typo in DRAMSim2 SConscriptAndreas Hansson
This patch fixes a typo in the SConscript which caused the DRAMSim2 sources to be built without the appropriate flags.
2014-03-23mem: CommMonitor trace warn on non-timing modeSascha Bischoff
Add a warning to the CommMonitor which will alert the user if they try and record a trace when the system is not in timing mode.
2014-03-23cpu: Add basic check to TrafficGen initial stateStan Czerniawski
Prevent incomplete configuration of TrafficGen class from causing segmentation faults. If an 'INIT' line is not present in the configuration file then the currState variable will remain uninitialized which may result in a crash.
2014-03-23dev: Fix IsaFake's cxx_header settingAndrew Bardsley
cxx_header was set incorrectly on IsaFake
2014-03-23arm: m5ops readfile64 args broken, offset coming through garbageEric Van Hensbergen
There were several sections of the m5ops code which were essentially copy/pasted versions of the 32-bit code. The problem is that some of these didn't account fo4 64-bit registers leading to arguments being in the wrong registers. This patch addresses the args for readfile64, writefile64, and addsymbol64 -- all of which seemed to suffer from a similar set of problems when moving to 64-bit.