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2018-04-17ps2: Add proper touchscreen command handlingAndreas Sandberg
The touchscreen model used ad-hoc mechanisms to enable/disable the device. Use standard PS/2 commands to activate/deactivate the device. Add proper TouchKit command handling. Change-Id: I0c5a2e2b47639f36ab3ee07e3e559f11afa54b9d Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9768 Reviewed-by: Gabe Black <gabeblack@google.com>
2018-04-17ps2: Implement the keyboard reset commandAndreas Sandberg
Linux tries to reset the PS/2 keyboard at boot. Change-Id: I727fbf6138b654885d82d85be9d964ee3d3365ef Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9766 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-04-17ps2: Unify device data bufferingAndreas Sandberg
All PS/2 device currently implement various ad-hoc mechanisms to handle multi-byte commands. This is error-prone and makes it hard to implement new devices. Create a buffering mechanism in the base class to avoid this. Change-Id: If5638b0ab68decea8de7631ecead0a9ebad1547b Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9765 Reviewed-by: Gabe Black <gabeblack@google.com>
2018-04-17ps2: Add a simple touchscreen modelAndreas Sandberg
Add a touchscreen model that is compatible with Linux's TouchKit driver. This model is based on the model in the Arm PL050 KMI model. Change-Id: Id4d88a21a26bb42c455e4d778cd89875f650ac57 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9764 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-04-17ps2: Add VNC support to the keyboard modelAndreas Sandberg
Add support for keyboard input from the VNC server in the PS/2 keyboard model. The introduced code is based on the functionality in the Arm PL050 KMI model. Change-Id: If04a9713e5a15e2149d1a7471b999e3060d8ee7d Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9763 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-04-17ps2: Factor out PS/2 devices into their own subsystemAndreas Sandberg
PS/2 devices are currently emulated both in the i8042 model and the Arm KMI model. This is undesirable since it leads to code duplication. This change introduces a common PS/2 device interface and factor out the x86 keyboard and mouse model. A subsequent commit will implement support for this interface in the Arm KMI model. Change-Id: I440e83517fd9dce362fdc1676db477cc6eee5211 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9762 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-04-17mem: Add a helper function to get a word of variable lengthAndreas Sandberg
There are many devices that need to handle reads/writes of different word sizes. A common pattern is a switch statement that check for the size of a packet and then calls the corresponding Packet::(get|set)<uintXX_t> methods. Simplify this by implementing Packet::(get|set)UintX helper functions. The getter reads a word of the size specified in the packet and the specified endianness. The word is then zero-extended to 64 bits. Conversely, the setter truncates the word down to the size required in the packet and then byte-swaps it to the desired endianness. Change-Id: I2f0c27fe3903abf3859bea13b07c7f5f0fb0809f Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9761 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-13ruby,gpu-compute: bugfix for GPU_VIPER* protocolsBrandon Potter
12db50c895 changed how directory mapping works, but it seems to have broken the VIPER variants of the GPU protocols. The fix involves declaring the function in the related '.sm' files. Change-Id: I116980d42a4aa648369058b529c9f8d9693eb894 Reviewed-on: https://gem5-review.googlesource.com/8521 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-04-13ruby: bugfix for MESI_Three_Level protocolBrandon Potter
Since a3177645, the MESI_Three_Level protocol does not build. This changeset addresses the problem by adding the L0Cache machine type to the static machine type declaration in Ruby's export file. Change-Id: I6327547fcb34595619caeb73932c0032f5f65c9f Reviewed-on: https://gem5-review.googlesource.com/8383 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-04-13mem-ruby: fix more style issues in AMD licensesTony Gutierrez
Change-Id: I6585c5664d966989991f61303548aed634cf298a Reviewed-on: https://gem5-review.googlesource.com/9841 Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-04-13mem-cache: Add MoveToTail to FALRUDaniel R. Carvalho
FALRU was missing MoveToTail functionality within its invalidate function, and MoveToHead was doing unnecessary passes when the moved block was the head already. Besides, added some comments to make the code understandable. Change-Id: I2430d82b5d53c88b102a62610ea38b46d6e03a55 Reviewed-on: https://gem5-review.googlesource.com/9541 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-12configs, mem-ruby: fix issues with style in AMD licenseTony Gutierrez
fixes line length and white space issues. Change-Id: Ia04a91ec68cae2bcdabeb93bb1a0f74e8e5486c3 Reviewed-on: https://gem5-review.googlesource.com/9801 Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com> Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
2018-04-10arch-arm: Fix mrc,mcr to cop14 disassembleGiacomo Travaglini
This patch fixes the disassemble for AArch32 mcr/mrc p14 instructions. Change-Id: If5d7c2d7c726f040ae20053bf1d70f4405b34d0e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9681 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-10dev: arm: SetScaling commands don't send parameter bytes.Gabe Black
These are single byte commands which change the mode of the mouse. They don't take any additional parameters like the SetRate or SetResolution. Change-Id: I29194916cfed5d3f4893947ef6d6cc636aee2419 Reviewed-on: https://gem5-review.googlesource.com/9701 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-06arch: alpha: Fix an 8 year old bug from the transition to pc objects.Gabe Black
When we transitioned from having PCs and nextPCs stored as individual items in the ThreadContext and went to having PC objects with abstracted components (micro PCs, delay slots, variable instruction lengths, etc.), a small mistake was made when translating the alpha StackTrace code. Change-Id: Ib5dd65c53a26920e66899f421902607efd139e71 Reviewed-on: https://gem5-review.googlesource.com/9702 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-04-06util,arch-arm: Update gen_arm_fs_files.py to use new kernel reposPau Cabre
Now it is using the kernels on https://gem5.googlesource.com/arm Change-Id: I765f2b8ee48cfd7175e5b17a65db3bf612570c68 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/9481 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-06arch-arm: Add support for Tarmac trace generationGiacomo Travaglini
This patch introduces the TarmacTracer: an instruction tracer which allows to dump a gem5 execution trace in Tarmac format [1]. The new tracer is supporting either Tarmac and TarmacV8 format specifications. Not every traceable information has been implemented: Implemented Trace Type: Instruction Trace Register Trace Processor Memory Access Trace Unimplemented Trace Type: Program Flow Trace Event Trace Memory Bus Trace [1]: https://developer.arm.com/docs/dui0845/f/tarmac-trace-file-format Change-Id: I8799d8e5852e868673f728971db3fe8c63961f5e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9382 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-06arch-arm: Add support for Tarmac trace-based simulationGiacomo Travaglini
A new InstTracer (TarmacParser) has been implemented. This tracer is parsing a pre-existing Tarmac trace file [1] while gem5 is running; it is comparing execution data together with trace data and it is dumping differences. This allows to use Tarmac format as a glue between heterogeneous simuators speaking the same Tarmac language. Kudos to Giacomo Gabrielli for writing the original tracer. [1]: https://developer.arm.com/docs/dui0845/f/tarmac-trace-file-format Change-Id: I9b92204a149813166166adba4a7c61a248bdcac3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9381 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-06arch-arm: Fix AArch32 branch instructions disassembleGiacomo Travaglini
This patch adds the generateDisassembly method for BranchReg, BranchImm and BranchRegReg Base classes used by AArch32 branch instructions. Change-Id: I6de015cc213335556d5187df3d4fcd765876262c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9503 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-06arch-arm: Fix secure write of SCTLR when EL3 is AArch64Giacomo Travaglini
MiscRegisters are not banked between secure and non-secure mode if EL3 is not implemented or if EL3 is using AArch64 (highestELIs64). In this scenario a unique register is used and it is mapped to the NS version (see snsBankedIndex implementation), so that a secure world read/write should access the non secure storage. Change-Id: Ica4182e3cdf4021d2bd1db23e477ce2bbf055926 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9502 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-06arch-arm: Correct mcrr,mrrc disassembleGiacomo Travaglini
This patch is fixing AArch32 mcrr,mrrc instruction disassemble by printing the correct source/destination registers Change-Id: I3fcffa0349aeee466e7c60ba4d1244824fb65d91 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9501 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-06mem: Remove unused 'using namespace'Daniel R. Carvalho
Removal of unused/barely used 'using namespace' from C++ files. Change-Id: I66dc548c04506db2e41180b9ea7ab5abd7d5375a Reviewed-on: https://gem5-review.googlesource.com/9601 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-06mem-cache: Move insertBlock functionality in FALRUDaniel R. Carvalho
Block insertion is being done in the getCandidates function, while the insertBlock function does not do anything. Besides, BaseTags' stats weren't being updated. Change-Id: Iadab9c1ea61519214f66fa24c4b91c4fc95604c0 Reviewed-on: https://gem5-review.googlesource.com/8882 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-06mem-cache: Create LIP Replacement PolicyDaniel R. Carvalho
Implementation of a LRU Insertion Policy replacement policy. Change-Id: I1a9aa0091ff2cdc1b1652c1d5ec7a3b33fba5b44 Reviewed-on: https://gem5-review.googlesource.com/9002 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-06mem-cache: Create BIP Replacement PolicyDaniel R. Carvalho
Implementation of a Bimodal Insertion Policy replacement policy. Change-Id: Ife058d0d4310dbcb35858348006189f0b2bf7c37 Reviewed-on: https://gem5-review.googlesource.com/9003 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-05mem-cache: Use Packet functions to write data blocksDaniel R. Carvalho
Instead of using raw memcpy, use the proper writer functions from the Packet class in Cache. Fixed typos in comments of these functions. Change-Id: I156a00989c6cbaa73763349006a37a18243d6ed4 Reviewed-on: https://gem5-review.googlesource.com/9661 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-05dev: Make sure the EtherTap device uses the right event queue.Gabe Black
The EtherTap device may be called into from an event on the PollQueue when some event queue other than its own is active. This change ensures that it switches event queues if necessary before doing anything that may cause more events to be scheduled. Change-Id: If8666542d7664780c0b371230e1e5fba93fbc1c0 Reviewed-on: https://gem5-review.googlesource.com/9521 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-30base: Make bitunion output functions static/inline.Gabe Black
The specializations need to be online only and not static, but the template itself is static and inline. Originally they were in an anonymous namespace, but that causes warnings when building on clang or with certain versions of gcc because the functions may not be used in every .cc. Change-Id: Iff127337f7bf0c18755de07a49d6e7a9ce6f2f0a Reviewed-on: https://gem5-review.googlesource.com/9581 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-03-30mem-cache: Remove unused return value from the recvTimingReq funcNikos Nikoleris
The recvTimingReq function in the cache always returns true. This changeset removes the return value. Change-Id: I00dddca65ee7224ecfa579ea5195c841dac02972 Reviewed-on: https://gem5-review.googlesource.com/8289 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2018-03-30mem-cache: Fix FALRU data block seg faultDaniel R. Carvalho
FALRU didn't initialize the blocks' data, causing seg faults. This patch does not make FALRU functional yet. Change-Id: I10cbcf5afc3f8bc357eeb8b7cb46789dec47ba8b Reviewed-on: https://gem5-review.googlesource.com/9302 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-30mem-cache: Create LFU replacement policyDaniel R. Carvalho
Implementation of a Least Frequently Used replacement policy. Change-Id: I772afccd3a7955777e53d59341e922718db44e5c Reviewed-on: https://gem5-review.googlesource.com/8890 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-30mem-cache: Create RRIP Replacement PolicyDaniel R. Carvalho
Implementation of a Re-Reference Interval Prediction replacement policy. Change-Id: Iba716eb5df2bf2be156e765f889d94f6ad00c91b Reviewed-on: https://gem5-review.googlesource.com/8981 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-03-30mem-cache: Create BRRIP replacement policyDaniel R. Carvalho
Implementation of a Bimodal Re-Reference Interval Prediction replacement policy. Change-Id: I25d4a59a60ef7ac496c66852e394fd6cbaf50912 Reviewed-on: https://gem5-review.googlesource.com/8891 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-28base: Add a default output function for bitunion types.Gabe Black
This way printing bitunions with, for instance, DPRINTF actually prints something useful. More specialized overloads will still allow printing particular bitunion types in ways that might make more sense for that particular type. Change-Id: I92beb0ce07683ba8b318cf25aa73e0057e4a60ef Reviewed-on: https://gem5-review.googlesource.com/9461 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-27dev: sparc: Get rid of the TheISA namespace in the SPARC devices.Gabe Black
It's not used, and so doesn't need to be brought in with a "using" statement. Change-Id: Iff4f7c66dbf1ee18e2e1a7d3e73bbae8cc4bf8eb Reviewed-on: https://gem5-review.googlesource.com/9406 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-27dev: Remove a bunch of Alpha code from MIPS, and unnecessary TheISAs.Gabe Black
There was a bunch of commented out code in the MIPS malta implementation which originally came from Alpha. That code is now deleted. Also, the MIPS code pulled in the TheISA namespace which it didn't use. Change-Id: I8470cc2fecb302f4399e52de4de9daf79c00a711 Reviewed-on: https://gem5-review.googlesource.com/9405 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-27cpu: Remove ExtMachInst typedefs from the O3 CPU model.Gabe Black
These typedefs aren't used, and they expose ISA specific types outside the ISA implementations. Change-Id: I64b9cec18d6f92765eebbdf8c8f1de15c0deba34 Reviewed-on: https://gem5-review.googlesource.com/9404 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-27arch: cpu: Make the ExtMachInst type a template argument in InstMap.Gabe Black
This doesn't completely hide the ISA specific ExtMachInst type inside the ISAs since it still gets applied in arch/generic, but it at least pulls it into the arch directory. Change-Id: Ic2188d59696530d7ecafdff0785d71867182701d Reviewed-on: https://gem5-review.googlesource.com/9403 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-27sparc: Add some missing M5_FALLTHROUGHs and breaks.Gabe Black
These fix what I believe are some bugs, and also some gcc warnings. Change-Id: I5fb2a1b2f0ef3643b25aaf0c29c096996ef98ec0 Reviewed-on: https://gem5-review.googlesource.com/9402 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-27cpu: Stop extracting inst_flags from the machInst.Gabe Black
The instruction representation is already encoded in the trace protobuf, so there's no reason to encode a part of it again. This is especially true since this supposedly generic code is extracting the first 8 bits of the machInst, a totally arbitrary set of bits for most ISAs. If certain bits within a machine instruction are actually relevant, the consumer of the trace should be able to interpret the instruction bytes which are already there and extract the same bits within the context of whatever ISA they're appropriate for. Change-Id: Idaebe6a110d7d4812c3d7c434582d5a9470bcec1 Reviewed-on: https://gem5-review.googlesource.com/9401 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-26cpu: Proposed fix for backwards compatibility in proto/inst.proto.Gabe Black
I haven't tested this at all, but this may fix backwards compatibility in inst.proto by removing the oneof construct. Change-Id: Iba19744791c2c577c3b442402f8cc6dcef8550bd Reviewed-on: https://gem5-review.googlesource.com/9361 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-26scons: Re-enable override based warnings on gcc.Gabe Black
These warnings have been fixed. Change-Id: I28ee5f4ae21412121849fcb9d273939d8e462842 Reviewed-on: https://gem5-review.googlesource.com/9344 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-26arch: Fix all override related warnings.Gabe Black
Clang has started(?) reporting override related warnings, something gcc apparently did before, but was disabled in the SConstruct. Rather than disable the warnings in for clang as well, this change fixes the warnings. A future change will re-enable the warnings for gcc. Change-Id: I3cc79e45749b2ae0f9bebb1acadc56a3d3a942da Reviewed-on: https://gem5-review.googlesource.com/9343 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-26cpu: Use the new asBytes function in the protobuf inst tracer.Gabe Black
Use this function to get the binary representation of the instruction rather than referencing the ExtMachInst typed machInst member of the StaticInst directly. ExtMachInst is an ISA specific type and can't always be straightforwardly squished into a 32 bit integer. Change-Id: Ic1f74d6d86eb779016677ae45c022939ce3e2b9f Reviewed-on: https://gem5-review.googlesource.com/7563 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-26arch: Add a virtual asBytes function to the StaticInst class.Gabe Black
This function takes a pointer to a buffer and the current size of the buffer as a pass by reference argument. If the size of the buffer is sufficient, the function stores a binary representation of itself (generally the ISA defined instruction encoding) in the buffer, and sets the size argument to how much space it used. This could be used by ISAs which have two instruction sizes (ARM and thumb, for example). If the buffer size isn't sufficient, then the size parameter should be set to what size is required, and then the function should return without modifying the buffer. The buffer itself should be aligned to the same standard as memory returned by new, specifically "The pointer returned shall be suitably aligned so that it can be converted to a pointer of any complete object type and then used to access the object or array in the storage allocated...". This will avoid having to memcpy buffers to avoid unaligned accesses. To standardize the representation of the data, it should be stored in the buffer as little endian. Since most hosts (including ARM and x86 hosts) will be little endian, this will almost always be a no-op. Change-Id: I2f31aa0b4f9c0126b44f47a881c2901243279bd6 Reviewed-on: https://gem5-review.googlesource.com/7562 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-23mem-cache: fix missing overrides in repl policiesJason Lowe-Power
Change-Id: I67759a4532e8a46c1643d4c3a9c546ad6b565b81 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/9321 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-23ruby: Make sure addresses print in hexJason Lowe-Power
Added fix in the invalid transition panic and various places in ruby random tester. Change-Id: I879264da58369faf7de49d1a28b2da1cb935ef0a Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/8941 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-23learning_gem5: Add a simple config for MI_exampleJason Lowe-Power
Adds a new config script to configure the MI_example protocol. This script closely follows the script used for MSI, but instead supports the MI_example protocol. This script works with the simple_ruby runscript and can be included instead of msi_caches. Change-Id: I8be0be67bf51369763ba103a5f101cfc01ad8859 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/8945 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-23learning_gem5: Ruby random tester files for MSIJason Lowe-Power
Adds a pair of scripts to run the Ruby random tester with the MSI protocol. This code follows Learning gem5 Part 3. http://learning.gem5.org/book/part3/index.html Change-Id: I15550a36618546f0354163b0216cf771f434ed84 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/8944 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-23learning_gem5: Add config files for MSI protocolJason Lowe-Power
Adds the required configuration files to run the MSI protocol. These config files are much simpler than the current Ruby examples and follow the pattern in the other Learning gem5 run scripts. By default, this script runs with two CPUs and runs the recently added thread test binary. Currently, only SE mode is supported. This code follows Learning gem5 Part 3. http://learning.gem5.org/book/part3/index.html Change-Id: I813a3153d49e47198444c38a6af30269bd1310cd Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/8943 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
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