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AgeCommit message (Expand)Author
2017-08-12dev: Fix an IDE error check.Gabe Black
2017-08-08mem-cache: Delete squashed HWPrefetchesPau Cabre
2017-08-03configs, arm: Fix incorrect use of mem_range in bL exampleAndreas Sandberg
2017-08-03arm, config: Fix CPU names in ARM example configsAndreas Sandberg
2017-08-02base: Give more information when setting up asynchronous IO fails.Gabe Black
2017-08-01misc: git ignore file udpatedÉder F. Zulian
2017-08-01style: Add shared gem5 headers to the style checkerAndreas Sandberg
2017-08-01util: Move m5op.h to the shared include directoryAndreas Sandberg
2017-08-01util, m5: Use consistent naming for m5op C symbolsAndreas Sandberg
2017-08-01arch-arm: Use named constants for m5op instructionsAndreas Sandberg
2017-08-01sim: Use named constants for pseudo opsAndreas Sandberg
2017-08-01util: Move the m5ops.h file to a shared directoryAndreas Sandberg
2017-08-01kvm, arm: Switch to the device EQ when accessing ISA devicesAndreas Sandberg
2017-08-01kvm: Add a helper method to access device event queuesAndreas Sandberg
2017-08-01cpu, kvm: Fix deadlock issue when resuming a drained systemAndreas Sandberg
2017-08-01arch-arm: Switch to DTOnly as the default machine typeAndreas Sandberg
2017-07-28config: Discover CPU timing models based on target ISAAndreas Sandberg
2017-07-27config, arm: SE configuration for the ARM starter kitGabor Dozsa
2017-07-27config, arm: FS configuration for the ARM starter kitGabor Dozsa
2017-07-27config, arm: Add a high-performance in order timing modelAshkan Tousi
2017-07-27config: Change mem_range attribute naming in ARM SimpleSystemGabor Dozsa
2017-07-25tests: Fix path for module imports in ARM system configsNikos Nikoleris
2017-07-25configs,sim-se: fix se.py multi-cpu multi-cmd issuePau Cabre
2017-07-20sim: Prevent segfault in the wakeCpu m5op if id is invalidJose Marinho
2017-07-19cpu: Add missing rename of vector registers in the O3 CPURekai Gonzalez-Alberquilla
2017-07-17cpu,o3: Fixed checkpointing bug occuring in the o3 CPUAnouk Van Laer
2017-07-17tests: Don't treat new stats as a cause for failuresAndreas Sandberg
2017-07-17sim, x86: Make clone a virtual functionSean Wilson
2017-07-17x86: Add stats to X86 TLBSwapnil Haria
2017-07-17riscv: Define register index constants using literalsAlec Roelke
2017-07-14riscv: Disambiguate between the C and C++ versions of isnan and isinf.Gabe Black
2017-07-14tests: Upate RISC-V binaries and resultsAlec Roelke
2017-07-14riscv: Fix bugs with RISC-V decoder and detailed CPUsAlec Roelke
2017-07-14riscv: Add unused attribute to some registers.hh constantsAlec Roelke
2017-07-13arch-arm: fix ldm of pc interswitching branchGedare Bloom
2017-07-12ruby: Refactor some Event subclasses to lambdasSean Wilson
2017-07-12arm: Refactor some Event subclasses to lambdasSean Wilson
2017-07-12dev: Refactor some Event subclasses to lambdasSean Wilson
2017-07-12net: Refactor some Event subclasses to lambdasSean Wilson
2017-07-12testers: Refactor some Event subclasses to lambdasSean Wilson
2017-07-12kvm, mem: Refactor some Event subclasses into lambdasSean Wilson
2017-07-12cpu: Refactor some Event subclasses to lambdasSean Wilson
2017-07-12gpu-compute: Refactor some Event subclasses to lambdasSean Wilson
2017-07-12sim, gdb: Refactor some Event subclasses into lambdasSean Wilson
2017-07-12mips, x86: Refactor some Event subclasses into lambdasSean Wilson
2017-07-12util,arch-arm: Added python script to generate ARM FS binariesPau Cabre
2017-07-12cpu, sim: Add param to force CPUs to wait for GDBJose Marinho
2017-07-11arch-riscv,tests: Add insttests for RV64CAlec Roelke
2017-07-11arch-riscv: Add support for compressed extension RV64CAlec Roelke
2017-07-11arch-riscv: Restructure ISA descriptionAlec Roelke