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Author
2007-11-13
Add in files from merge-bare-iron, get them compiling in FS and SE mode
Korey Sewell
2007-11-03
Checkpoint: Use checkpoint_dir, if that is not set use outdir (-d), and if th...
Ali Saidi
2007-10-25
Checkpoints: Change Simulation.py to not go crazy if the simulation ends befo...
Ali Saidi
2007-10-08
Configuration: Move iocache outside of processors loop so it works for MP sys...
Ali Saidi
2007-10-07
X86: Adjust the config scripts for x86 fs.
Gabe Black
2007-09-12
Checkpointing: Fix directory regex
Ali Saidi
2007-09-12
Checkpointing: Force drain/resume when switching a CPU
Ali Saidi
2007-09-05
Configuration: Fix example script to only create one L2 if --l2cache and -nX ...
Ali Saidi
2007-08-16
PCI: Move PCI Configuration data into devices now that we can inherit paramet...
Ali Saidi
2007-08-16
Devices: Make EtherInts connect in the same way memory ports currently do.
Ali Saidi
2007-08-12
Regression: fix configuration for SPARC_FS
Ali Saidi
2007-08-08
Added fastmem option.
Vincentius Robby
2007-08-10
DMA: Add IOCache and fix bus bridge to optionally only send requests one
Ali Saidi
2007-08-03
merge from head
Steve Reinhardt
2007-08-02
merge, no manual changes
Ali Saidi
2007-08-01
Fix how the "cmd" parameter is set in se.py and remove hack in x86 process in...
Gabe Black
2007-08-01
Configuration: Update the drive systems kernel as well as the testsys kernel ...
Ali Saidi
2007-07-15
Fix up a bunch of multilevel coherence issues.
Steve Reinhardt
2007-07-15
Fix problem with unset max_loads in memtest.
Steve Reinhardt
2007-07-15
Punt on old -n/-c memtest args.
Steve Reinhardt
2007-07-15
Add --force-bus option to memtest.py.
Steve Reinhardt
2007-07-14
New tree-based algorithm for creating more complex cache hierarchies.
Steve Reinhardt
2007-06-30
Get rid of remaining traces of obsolete CoherenceProtocol object.
Steve Reinhardt
2007-06-27
Get rid of coherence protocol object.
Steve Reinhardt
2007-06-21
Getting closer...
Steve Reinhardt
2007-06-17
Merge vm1.(none):/home/stever/bk/newmem-head
Steve Reinhardt
2007-06-17
More major reorg of cache. Seems to work for atomic mode now,
Steve Reinhardt
2007-06-10
the cmd argument is supposed to be an array of parameters, not one string
Nathan Binkert
2007-06-09
More realistic parameters
Nathan Binkert
2007-06-04
fix SPARC....
Ali Saidi
2007-05-27
Move SimObject python files alongside the C++ and fix
Nathan Binkert
2007-05-22
memtest.py:
Steve Reinhardt
2007-05-19
PhysicalMemory has vector of uniform ports instead of one special one.
Steve Reinhardt
2007-05-15
add an l2 cache option to se example config
Ali Saidi
2007-05-15
hopefully the final hacky change to make the bus bridge work ok
Ali Saidi
2007-05-14
couple more bug fixes for intel nic
Ali Saidi
2007-05-10
remove hit_latency and make latency do the right thing
Ali Saidi
2007-05-07
fix partial writes with a functional memory hack
Ali Saidi
2007-04-30
add a udp stream benchmark and a udp loopback benchmark
Ali Saidi
2007-04-30
make ping actually end
Ali Saidi
2007-04-26
Fix mutex test script for latest disk image.
Kevin Lim
2007-04-23
Fix the splash2 run script
Ron Dreslinski
2007-04-20
spec-surge-client.rcS:
Lisa Hsu
2007-03-22
Fix mcf benchmark object so it gets the arguments it expects.
Gabe Black
2007-03-06
Move all of the parameters of the Root SimObject so they are
Nathan Binkert
2007-03-03
Merge zizzer:/bk/newmem
Ali Saidi
2007-03-03
Add Iob and remove the fake device
Ali Saidi
2007-03-03
Implement Niagara I/O interface and rework interrupts
Ali Saidi
2007-03-03
Keep around which input set was used for a benchmark, and make vortex work wi...
Gabe Black
2007-02-21
Get rid of the ConsoleListener SimObject and just fold the
Nathan Binkert
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