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2019-02-26configs: Fix Python 3 iterator and exec compatibility issuesAndreas Sandberg
Python 2.7 used to return lists for operations such as map and range, this has changed in Python 3. To make the configs Python 3 compliant, add explicit conversions from iterators to lists where needed, replace xrange with range, and fix changes to exec syntax. This change doesn't fix import paths since that might require us to restructure the configs slightly. Change-Id: Idcea8482b286779fc98b4e144ca8f54069c08024 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16002 Reviewed-by: Gabe Black <gabeblack@google.com>
2019-02-25systemc: Update the sc_main.py config to use m5.systemc.Gabe Black
Change-Id: I386970b5cf7ee1262b259abfb3b5e902ccea9991 Reviewed-on: https://gem5-review.googlesource.com/c/16568 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-13configs: simpoint-profile usable with NonCachingCPUs onlyGiacomo Travaglini
NonCachingCPU is replacing the Atomic+fastmem option. Change-Id: I66f5c8a880d1b3fd1331871d89e8d6a229938e57 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15935 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-12systemc: config: Don't inject a custom argv[0] in sc_main.py.Gabe Black
argv[0] is already part of sys.argv, so we don't need to add an additional argument in front of sys.argv. The argv[0] which is used in gem5 config scripts is the name of the config script itself. While it might seem a little odd for the name of a systemc program to end in .py, it's as arbitrary as any other name, and generally shouldn't cause a problem. If some other more sophisticated mechanism for setting argv[0] is necessary, then the user can write a very slightly more complicated version of this script with additional logic. Change-Id: Ifd5d8a02d3cd5db76054151ed6c7a7b1f8495fa8 Reviewed-on: https://gem5-review.googlesource.com/c/16342 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-02-11systemc: configs: Add a very simple config which just runs sc_main.Gabe Black
This config will just run the sc_main function (which must have been provided in c++ somehow), passing through any of the scripts command line arguments to sc_main. Needing to do this sort of thing is common enough that there should be a canned config which supports it. Change-Id: I8f88ba4776b9ec919dd8145a58cd856e11ac4e77 Reviewed-on: https://gem5-review.googlesource.com/c/16287 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-07configs, arch-arm: Using AddrRange for Realview mem_regionsGiacomo Travaglini
Physical memory ranges are now saved in Realview objects as pairs of addresses (start address and size). This patch is substituting them with a single AddrRange object. Change-Id: I02d25d557c5c54d062f0dccef8ede45744d0ce6b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16206 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-07configs: Unifiy interpretation of Realview mem_regionsGiacomo Travaglini
In every arm platform which is making use of them, mem_regions are interpreted as a pair of start address and size. However arm SimpleSystem, which is using VExpress_GEM5_V1, is interpreting them as start address and end address. This patch is fixing this mismatch. Change-Id: I0b2a2193cd07fbc5430f233438269a9c7c353df9 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16205 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-30configs: Enable DTB autogeneration in starter_fs.pyGiacomo Travaglini
This patch is removing hardcoded default DTBs in favour of common DTB autogeneration. Change-Id: I68fdc2a169bfa8e8657c9ed4e4e127957a08cca1 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15959 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-30arch-arm, configs: Create single instance of DTB autogenerationGiacomo Travaglini
This patch is rewriting the DTB autogeneration functions available in fs_bigLITTLE.py and fs.py as a single method in the GenericArmSystem so that other configuration scripts can make use of it. Change-Id: I492bbf77e6b0ac5c5fbdbc75c0eecba29bd63bda Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15958 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-25configs: fs.py remove --generate-dtb and enable it by defaultCiro Santilli
The option is now enabled if neither --bare-metal nor --dtb-filename are given. This is what fs_bigLITTLE.py already did before this patch. Change-Id: I9179f8c9fa18edbd1e0f1a65ea2c1de0a26b7921 Reviewed-on: https://gem5-review.googlesource.com/c/15899 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-01-25configs, arch-arm: don't search for default DTB and kernelCiro Santilli
Before this commit, there were default magic DTB and kernel filenames for some platforms. This was inelegant and error prone, as it refered to out-of-tree files, and set defaults which users almost always want to customize with explicit command line options. One result of this is that a wrong exception could be thrown if --kernel was given but not --machine-type, since the default machine type VExpress_EMM had a default kernel, and the code would always search for the default filename even though --kernel was given: IOError: Can't find file 'vmlinux.aarch32.ll_20131205.0-gem5' on path. The defaults existed only for older machine types, and not for the usually recommended VExpress_GEM5_V1, which suggests that this deprecation should not affect many users. Change-Id: Ia49298304f658701ea0800bd79e08db404a655c3 Reviewed-on: https://gem5-review.googlesource.com/c/15898 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-01-10dev-arm: Add a VExpress_GEM5_V2 platform with GICv3 supportJairo Balart
Change-Id: I6fd14138d94654e8e60cde08239ea9a50fc19eb7 Reviewed-on: https://gem5-review.googlesource.com/c/14255 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-11-17configs: Added an option for choosing branch predictor typePau Cabre
Added the parameter "--bp-type" to set the branch predictor type Added the parameter "--list-bp-types" to list all the available branch predictor types Change-Id: Ia6aae90c784aef359b6d8233c8383cd7a871aca1 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14015 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-09configs: Revamp ruby mem test to align with MemTestNikos Nikoleris
The test script was broken as it was based on an older version of MemTest, this changes revamps the creation of MemTest and removes parameters that are not any longer valid. Change-Id: Ib87369c1e4717c2da23e8108c72eec871e56f6ed Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13596 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-08configs: Add missing path to ruby importsDaniel R. Carvalho
Add missing addToPath to ruby files, so that import modules from previous folder are visible. Change-Id: I912d78a2f709974f72fe768e73abac1617126f46 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13995 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-19config: add --param to fs.py, se.py and fs_bigLITTLE.pyCiro Santilli
The option allows to set SimObject params from the CLI. The existing config scripts have a large number of options that simply set a single SimObject parameter, and many still are not exposed. This commit allows users to pass arbitrary parameters from the command line to prevent the need for this kind of trivial option. Change-Id: Ic4bd36948aca4998d2eaf6369c85d3668efa3944 Reviewed-on: https://gem5-review.googlesource.com/c/12985 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-09configs: Fix CPUClass typo in se.pyDaniel R. Carvalho
Change 719eb033fe435133abf15501c249eec10d1c861f added a typo to se.py that breaks simpoint simulation, which generates the following error: Traceback (most recent call last): File "<string>", line 1, in <module> File "/home/daniel/gem5/src/python/m5/main.py", line 435, in main exec filecode in scope File "./configs/example/se.py", line 217, in <module> if not CpuConfig.is_atomic_cpu(TestCPUClass): NameError: name 'TestCPUClass' is not defined Change-Id: Ideede8c96a40ee16af733c3d57b02b64f1a18d12 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13267 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-08dev, arm: remove the RealViewEB platformCiro Santilli
This is an old platform, and we haven't had official Linux kernel configs for it in a while, so we've decided to deprecate it. Furthermore, trying to use it fails with: object 'RealViewEB' has no attribute 'pci_host' and the last commit in the class happened two years ago, which indicates that no one has been using it. Change-Id: Icc674b00b152eb3246e05141dbaf2624cc720f21 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/12471 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-17config, arm, power: Example to report the power for the L2 CacheSherif Elhabbal
This patch add an example to demonstrate how to report the power for the L2 Cache of the big cluster separately ,it decouples the L2 contributions from the CPU power equation Signed-off-by: Sherif Elhabbal <elhabbalsherif@gmail.com> Change-Id: Idde43c8bcb10df9d44d20282eaf21ce87a9d3f58 Reviewed-on: https://gem5-review.googlesource.com/12684 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-09-12config, dev-arm: Fix UART handling baremetal modeCiro Santilli
fs.py in baremetal mode currently fails for the VExpress_GEM5_V1 platform due to inconsistent UART naming with error message: AttributeError: object 'VExpress_GEM5_V1' has no attribute 'uart' Consistently name keep all UARTs in the Arm platforms in a vector named 'uart' or as a single device named 'uart'. Update the configuration scripts to reflect the fact that 'uart' can be a vector. Change-Id: I20b8dbac794d6a9be19b6ce8c335a097872132fb Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12473 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-12cpu: Replace the fastmem with a new CPU modelAndreas Sandberg
The AtomicSimpleCPU used to be able to access memory directly to speed up simulation if no caches are used. This is fine as long as no switching between CPU models is required. In order to switch to a new CPU model that requires caches, we currently need to checkpoint the system and restore it into a new configuration. The new 'atomic_noncaching' memory mode provides a solution that avoids this issue since caches are bypassed in this mode. This changeset removes the old fastmem option from the AtomicSimpleCPU and introduces a new CPU, NonCachingSimpleCPU, which derives from the AtomicSimpleCPU. The NonCachingSimpleCPU uses the same mechanism as the AtomicSimpleCPU used to use when accessing memory in when fastmem was enabled. This changeset also introduces a new switcheroo test that tests switching between a NonCachingSimpleCPU and a TimingSimpleCPU with caches. Change-Id: If01893f9b37528b14f530c11ce6f53c097582c21 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12419 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-09-10configs: Use the same address ranges for dir and mem_ctrlsNikos Nikoleris
In Ruby, for every directory we create one memory controller for every range in the memory ranges. Previously the memory controllers and the directories created their address ranges independently and as a result a mismatch was possible. In fact, we assinged an interleaved address range with hasing for the memory controllers while the corresponding directories would be assigned the same interleaved address range without hashing. This change uses the address range of the memory controllers to populate the list of address ranges for the corresponding directory and avoid bugs due to code duplication. Change-Id: I1e321c81a254199e5aaa9f3b81f4a4642c60a67a Reviewed-on: https://gem5-review.googlesource.com/12318 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-09-03config: Move KVM CPU checking to CpuConfig helper moduleAndreas Sandberg
Both se.py and fs.py need to check if a CPU is a KVM CPU. This is somewhat involved since CPUs can be disabled at compile time. Enable better code reuse by moving it to the CpuConfig module. Change-Id: I47b1512ecb62e757399a407a0e41be83b9f83be3 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12418 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-08-17configs: Always exit with code 0Jason Lowe-Power
Update simulation.py to always exit with code 0 assuming the simulation exits normally. If the running application has a return code that is non zero, then print the return code before exiting. Change-Id: I1983985d50311627574d4364b32ee961ae88e003 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/4880
2018-07-13configs: Update the DRAM sweep script to use PyTrafficGenAndreas Sandberg
Instead of generating a text configuration, use the new Python-based traffic generator. Change-Id: I6fb88ec45b74bb87470aa265af18b5a2ff24c314 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11519 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-05-31mem-cache: Add a non-coherent cacheNikos Nikoleris
The class re-uses the existing MSHR and write queue. At the moment every single access is handled by the cache, even uncacheable accesses, and nothing is forwarded. This is a modified version of a changeset put together by Andreas Hansson <andreas.hansson@arm.com> Change-Id: I41f7f9c2b8c7fa5ec23712a4446e8adb1c9a336a Reviewed-on: https://gem5-review.googlesource.com/8291 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2018-05-16style: fix amd license and style issuesTony Gutierrez
Change-Id: I26136fb49f743c4a597f8021cfd27f78897267b5 Reviewed-on: https://gem5-review.googlesource.com/10463 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-04-12configs, mem-ruby: fix issues with style in AMD licenseTony Gutierrez
fixes line length and white space issues. Change-Id: Ia04a91ec68cae2bcdabeb93bb1a0f74e8e5486c3 Reviewed-on: https://gem5-review.googlesource.com/9801 Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com> Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
2018-03-23learning_gem5: Add a simple config for MI_exampleJason Lowe-Power
Adds a new config script to configure the MI_example protocol. This script closely follows the script used for MSI, but instead supports the MI_example protocol. This script works with the simple_ruby runscript and can be included instead of msi_caches. Change-Id: I8be0be67bf51369763ba103a5f101cfc01ad8859 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/8945 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-23learning_gem5: Ruby random tester files for MSIJason Lowe-Power
Adds a pair of scripts to run the Ruby random tester with the MSI protocol. This code follows Learning gem5 Part 3. http://learning.gem5.org/book/part3/index.html Change-Id: I15550a36618546f0354163b0216cf771f434ed84 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/8944 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-23learning_gem5: Add config files for MSI protocolJason Lowe-Power
Adds the required configuration files to run the MSI protocol. These config files are much simpler than the current Ruby examples and follow the pattern in the other Learning gem5 run scripts. By default, this script runs with two CPUs and runs the recently added thread test binary. Currently, only SE mode is supported. This code follows Learning gem5 Part 3. http://learning.gem5.org/book/part3/index.html Change-Id: I813a3153d49e47198444c38a6af30269bd1310cd Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/8943 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-22mem-cache: Split array indexing and replacement policies.Daniel R. Carvalho
Replacement policies (LRU, Random) are currently considered as array indexing methods, but have completely different functionalities: - Array indexers determine the possible locations for block allocation. This information is used to generate replacement candidates when conflicts happen. - Replacement policies determine which of the replacement candidates should be evicted to make room for new allocations. For this reason, they were split into different classes. Advantages: - Easier and more straightforward to implement other replacement policies (RRIP, LFU, ARC, ...) - Allow easier future implementation of cache organization schemes As now we can't assure the use of sets, the previous way to create a true LRU is not viable. Now a timestamp_bits parameter controls how many bits are dedicated for the timestamp, and a true LRU can be achieved through an infinite number of bits (although a few bits suffice in practice). Change-Id: I23750db121f1474d17831137e6ff618beb2b3eda Reviewed-on: https://gem5-review.googlesource.com/8501 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-20arch-arm, configs: Treat the bootloader rom as cacheable memoryNikos Nikoleris
Prior to this changeset the bootloader rom (instantiated as a SimpleMemory) in ruby Arm systems was treated as an IO device and it was fronted by a DMA controller. This changeset moves the bootloader rom and adds it to the system as another memory with a dedicated directory controller. Change-Id: I094fed031cdef7f77a939d94f948d967b349b7e0 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8741 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-03-13learning_gem5: Update README for Learning gem5Jason Lowe-Power
Change-Id: I94485e401bc77207cab68c1e24ef7a6ed83bd43d Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/8946 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2018-03-06config: Switch from the print statement to the print function.Gabe Black
Change-Id: I701fa58cfcfa2767ce9ad24da314a053889878d0 Reviewed-on: https://gem5-review.googlesource.com/8762 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-02configs: Fix L3Cache instantiation in lat_mem_rd.pyNikos Nikoleris
This changeset updates the lat_mem_rd.py to configure the L3Cache using the split tag_latency, data_latency parameters. Change-Id: I8bc41d5f7664111bdda0972356d1a17762aa77e5 Reviewed-on: https://gem5-review.googlesource.com/8288 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2018-02-05config: remove dead code in fs.pyNayan Deshmukh
We have not added the --generate-dtb option for non-ARM systems and hence this case becomes dead code. It also leads to error on non-ARM systems as is tries to access a non existent field. Change-Id: Ia926bd0c61efa275bc5e3864b8a9c3ffb7aa3cb5 Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/7801 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-01-29config, arm: enable device tree autogeneration for bigLITTLECurtis Dunham
Change-Id: Iaa5eeb3504b3ff9e46b6f592a06d6b833c830d83 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5969 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-29config: Embed Device Tree generation in fs.py configGlenn Bergmans
Equips the fs.py config routine with an extra commandline option --generate-dtb that will generate a dtb file automatically before running the simulation. Only works with ARM systems and gives a warning if the simulated system is not of --machine-type VExpress_GEM5_V1. Change-Id: I7766e5459fd9bec2245de83cef103091ebaf7229 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5968 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-10configs: Fill in the cpu.isa field in etrace_replay.py since no default are ↵Chen Zou
provided now Change-Id: I5f337b9969820bd74ed67e576e2d1a8e4666ecdb Reviewed-on: https://gem5-review.googlesource.com/7021 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-01-08gpu-compute: call createThreads() on cpu objs in apu_se.pyTony Gutierrez
commit 8ad26e2688b8736f9290086bb4026cc7500429e9 cpu: Don't override ISA if provided by user removed the default ISA from the BaseCPU, and instead relies on createThreads() to initiate a default ISA if none is specified. the apu_se.py script, however does not call creatThreads() leading to a fatal when constructing CPU objects. this patch adds the appropriate calls to createThreads() inside apu_se.py. Change-Id: I16a5929454c59d68a3f1b7b3858c48a70cb76412 Reviewed-on: https://gem5-review.googlesource.com/7101 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-01-02config: Handle NULL simobject parameters in read_config.py.Gabe Black
Change-Id: If0f87e8ee37099be4d0f3567db4fc34f8467e409 Reviewed-on: https://gem5-review.googlesource.com/6943 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-01-02config: Fix parsing AddrRange parameters in read_config.py.Gabe Black
The format of AddrRange parameters was changed, but config/example/read_config.py wasn't updated for the new format. Change-Id: Ie0da7aaa47c827bacc2b4f7f44929efd868b8794 Reviewed-on: https://gem5-review.googlesource.com/6942 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-01-02config: Add a --checkpoint-dir argument to read_config.py.Gabe Black
This argument lets the user restore a checkpoint after loading simulator state from config.ini. Change-Id: I6e0630d75b798a1d2536e2408660843f57f46c4b Reviewed-on: https://gem5-review.googlesource.com/6941 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-12-15mem-ruby: Support atomic_noncaching acceses in rubySwapnil Haria
Ruby has no support for atomic_noncaching accesses, which prevents using it with kvm-cpu. This patch fixes this by directly forwarding atomic requests from the ruby port/sequencer to the corresponding directory based on the destination address of the packet. Change-Id: I0b4928bfda44fd9e5e48583c51d1ea422800da2d Reviewed-on: https://gem5-review.googlesource.com/5601 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
2017-12-12config: Fix need to set ISA of switch cpus.Austin Harris
Since BaseCPU.createThreads() no longer overrides the BaseCPU.isa parameter, switch_cpus should have the ISA copied. This fixes a fatal error in BaseCPU when restoring from a checkpoint. Change-Id: I4fdcacb76da46bdbe1ce37dcf05c5a6a8a9e5237 Signed-off-by: Austin Harris <austinharris@utexas.edu> Reviewed-on: https://gem5-review.googlesource.com/6241 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-12-05config, mem, hmc: fix HMC test scriptÉder F. Zulian
This patch keeps the logic behind the HMC model implementation untouched. Additional changes: - simple hello world script using HMC (SE simulation) Usage examples: ./build/ARM/gem5.opt configs/example/hmctest.py ./build/ARM/gem5.opt configs/example/hmctest.py --enable-global-monitor --enable-link-monitor --arch=same ./build/ARM/gem5.opt configs/example/hmctest.py --enable-global-monitor --enable-link-monitor --arch=mixed ./build/ARM/gem5.opt configs/example/hmc_hello.py ./build/ARM/gem5.opt configs/example/hmc_hello.py --enable-global-monitor --enable-link-monitor Change-Id: I64eb6c9abb45376b6ed72722926acddd50765394 Reviewed-on: https://gem5-review.googlesource.com/6061 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-12-05learning_gem5: Adding code for SimpleCacheJason Lowe-Power
This is the rest of the code for part 2. See http://learning.gem5.org/book/part2/simplecache.html Change-Id: I5db099266a1196914656be3858fdd5fb4f8eab48 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/5023 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2017-12-05learning_gem5: Adds the simple MemObject codeJason Lowe-Power
Adding more code from Learning gem5 Part II See http://learning.gem5.org/book/part2/memoryobject.html Change-Id: Iaa9480c5cdbe4090364f02e81dc1d0a0ddac392a Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/5022 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2017-12-05learning_gem5: Add code for hello-goodbye exampleJason Lowe-Power
Adding more code from Learning gem5 Part II See http://learning.gem5.org/book/part2/parameters.html Change-Id: I9fe5655239e011c718c5cf5fd62bebcda66ea966 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/5021 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-27 15:04:23 +0000