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AgeCommit message (Expand)Author
2007-10-25Checkpoints: Change Simulation.py to not go crazy if the simulation ends befo...Ali Saidi
2007-10-08Configuration: Move iocache outside of processors loop so it works for MP sys...Ali Saidi
2007-10-07X86: Adjust the config scripts for x86 fs.Gabe Black
2007-09-12Checkpointing: Fix directory regexAli Saidi
2007-09-12Checkpointing: Force drain/resume when switching a CPUAli Saidi
2007-09-05Configuration: Fix example script to only create one L2 if --l2cache and -nX ...Ali Saidi
2007-08-16PCI: Move PCI Configuration data into devices now that we can inherit paramet...Ali Saidi
2007-08-16Devices: Make EtherInts connect in the same way memory ports currently do.Ali Saidi
2007-08-12Regression: fix configuration for SPARC_FSAli Saidi
2007-08-08Added fastmem option.Vincentius Robby
2007-08-10DMA: Add IOCache and fix bus bridge to optionally only send requests oneAli Saidi
2007-08-03merge from headSteve Reinhardt
2007-08-02merge, no manual changesAli Saidi
2007-08-01Fix how the "cmd" parameter is set in se.py and remove hack in x86 process in...Gabe Black
2007-08-01Configuration: Update the drive systems kernel as well as the testsys kernel ...Ali Saidi
2007-07-15Fix up a bunch of multilevel coherence issues.Steve Reinhardt
2007-07-15Fix problem with unset max_loads in memtest.Steve Reinhardt
2007-07-15Punt on old -n/-c memtest args.Steve Reinhardt
2007-07-15Add --force-bus option to memtest.py.Steve Reinhardt
2007-07-14New tree-based algorithm for creating more complex cache hierarchies.Steve Reinhardt
2007-06-30Get rid of remaining traces of obsolete CoherenceProtocol object.Steve Reinhardt
2007-06-27Get rid of coherence protocol object.Steve Reinhardt
2007-06-21Getting closer...Steve Reinhardt
2007-06-17Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
2007-06-17More major reorg of cache. Seems to work for atomic mode now,Steve Reinhardt
2007-06-10the cmd argument is supposed to be an array of parameters, not one stringNathan Binkert
2007-06-09More realistic parametersNathan Binkert
2007-06-04fix SPARC....Ali Saidi
2007-05-27Move SimObject python files alongside the C++ and fixNathan Binkert
2007-05-22memtest.py:Steve Reinhardt
2007-05-19PhysicalMemory has vector of uniform ports instead of one special one.Steve Reinhardt
2007-05-15add an l2 cache option to se example configAli Saidi
2007-05-15hopefully the final hacky change to make the bus bridge work okAli Saidi
2007-05-14couple more bug fixes for intel nicAli Saidi
2007-05-10remove hit_latency and make latency do the right thingAli Saidi
2007-05-07fix partial writes with a functional memory hackAli Saidi
2007-04-30add a udp stream benchmark and a udp loopback benchmarkAli Saidi
2007-04-30make ping actually endAli Saidi
2007-04-26Fix mutex test script for latest disk image.Kevin Lim
2007-04-23Fix the splash2 run scriptRon Dreslinski
2007-04-20spec-surge-client.rcS:Lisa Hsu
2007-03-22Fix mcf benchmark object so it gets the arguments it expects.Gabe Black
2007-03-06Move all of the parameters of the Root SimObject so they areNathan Binkert
2007-03-03Merge zizzer:/bk/newmemAli Saidi
2007-03-03Add Iob and remove the fake deviceAli Saidi
2007-03-03Implement Niagara I/O interface and rework interruptsAli Saidi
2007-03-03Keep around which input set was used for a benchmark, and make vortex work wi...Gabe Black
2007-02-21Get rid of the ConsoleListener SimObject and just fold theNathan Binkert
2007-01-30fix some checkpointing annoyancesAli Saidi
2007-01-22Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
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