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2011-08-19ARM: Add some MP regressions and clean up the disk images and kernels a bitAli Saidi
2011-08-19ARM: Add VExpress_E support with PCIe to gem5Ali Saidi
2011-08-19ARM: Add support for Versatile Express boardsAli Saidi
2011-08-02Scons: Drop RUBY as compile time option.Nilay Vaish
This patch drops RUBY as a compile time option. Instead the PROTOCOL option is used to figure out whether or not to build Ruby. If the specified protocol is 'None', then Ruby is not compiled.
2011-07-26Ruby: Fix instantiations of DMA controller and sequencerNilay Vaish
The patch on Ruby functional accesses made changes to the process of instantiating controllers and sequencers. The DMA controller and sequencer was not updated, hence this patch.
2011-07-25Ruby: Fix dma controller configs/ruby/MI_example.pyNilay Vaish
The dma controller in configs/ruby/MI_example.py was not being set correctly. This patch fixes it.
2011-07-11se.py: Fixes the way ruby's options are addedNilay Vaish
2011-07-03Network_test: Conform it with functional access changes in RubyNilay Vaish
Addition of functional access support to Ruby necessitated some changes to the way coherence protocols are written. I had forgotten to update the Network_test protocol. This patch makes those updates.
2011-06-30config: removed unnecessary slashesBrad Beckmann
This patch removes unnecessary slashes from a couple of python scripts.
2011-06-30Ruby: Add support for functional accessesBrad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
This patch rpovides functional access support in Ruby. Currently only the M5Port of RubyPort supports functional accesses. The support for functional through the PioPort will be added as a separate patch.
2011-06-17ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.Gedare Bloom
2011-05-23config: revamp x86 config to avoid appending to SimObjectVectorsSteve Reinhardt
A significant contributor to the need for adoptOrphanParams() is the practice of appending to SimObjectVectors which have already been assigned as children. This practice sidesteps the assignment operation for those appended SimObjects, which is where parent/child relationships are typically established. This patch reworks the config scripts that use append() on SimObjectVectors, which all happen to be in the x86 system configuration. At some point in the future, I hope to make SimObjectVectors immutable (by deriving from tuple rather than list), at which time this patch will be necessary for correct operation. For now, it just avoids some of the warning messages that get printed in adoptOrphanParams().
2011-05-23config: tweak ruby configs to clean up hierarchySteve Reinhardt
Re-enabling implicit parenting (see previous patch) causes current Ruby config scripts to create some strange hierarchies and generate several warnings. This patch makes three general changes to address these issues. 1. The order of object creation in the ruby config files makes the L1 caches children of the sequencer rather than the controller; these config ciles are rewritten to assign the L1 caches to the controller first. 2. The assignment of the sequencer list to system.ruby.cpu_ruby_ports causes the sequencers to be children of system.ruby, generating warnings because they are already parented to their respective controllers. Changing this attribute to _cpu_ruby_ports fixes this because the leading underscore means this is now treated as a plain Python attribute rather than a child assignment. As a result, the configuration hierarchy changes such that, e.g., system.ruby.cpu_ruby_ports0 becomes system.l1_cntrl0.sequencer. 3. In the topology classes, the routers become children of some random internal link node rather than direct children of the topology. The topology classes are rewritten to assign the routers to the topology object first.
2011-05-23configs: missed spot progress-interval changeKorey Sewell
2011-05-21configs: remove -p from ruby_network_test.pyTushar Krishna
A recent patch broke the ruby network tester by adding -p inside Options.py which conflicts with the -p inside ruby_network_test.py. Have removed -p from ruby_network_test.py
2011-05-20configs: cleanup redundant/unused optionsKorey Sewell
maxinsts & max_inst redundant prog_intvl and profile seem redundant, but profile looks to be unused add -p option for progress intervals
2011-05-07NetworkTest: added sim_cycles parameter to the network tester.Tushar Krishna
The network tester terminates after injecting for sim_cycles (default=1000), instead of having to explicitly pass --maxticks from the command line as before. If fixed_pkts is enabled, the tester only injects maxpackets number of packets, else it keeps injecting till sim_cycles. The tester also works with zero command line arguments now.
2011-05-04ARM: Configure bootloader parametersAli Saidi
2011-04-28network: basic link bw for garnet and simple networksBrad Beckmann
This patch ensures that both Garnet and the simple networks use the bw value specified in the topology. To do so, the patch generalizes the specification of bw for basic links. This value is then translated to the specific value used by the simple and Garnet networks. Since Garent does not support non-uniformed link bandwidth, the patch also adds a check to ensure all bws are equal. --HG-- rename : src/mem/ruby/network/BasicLink.cc => src/mem/ruby/network/simple/SimpleLink.cc rename : src/mem/ruby/network/BasicLink.hh => src/mem/ruby/network/simple/SimpleLink.hh rename : src/mem/ruby/network/BasicLink.py => src/mem/ruby/network/simple/SimpleLink.py
2011-04-28network: convert links & switches to first class C++ SimObjectsBrad Beckmann
This patch converts links and switches from second class simobjects that were virtually ignored by the networks (both simple and Garnet) to first class simobjects that directly correspond to c++ ojbects manipulated by the topology and network classes. This is especially true for Garnet, where the links and switches directly correspond to specific C++ objects. By making this change, many aspects of the Topology class were simplified. --HG-- rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/BasicLink.cc rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/BasicLink.hh rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.cc rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.hh rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.cc rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.hh rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py
2011-04-20python: fix another bug from changes to main.pyNathan Binkert
2011-04-04ARM: Include IDE/CF controller by default in PBX model.Ali Saidi
Frame buffer and boot linux: ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxFrameBuf --kernel=vmlinux.touchkit Linux from a CF card: ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.touchkit Run Android ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmAndroid --kernel=vmlinux.android Run MP ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.mp-2.6.38
2011-04-04Sim: Fix Simulation.py to allow more than 1 core for standard switching.Anthony Gutierrez
This patch moves the assignment of testsys.switch_cpus, testsys.switch_cpus_1, switch_cpu_list, and switch_cpu_list1 outside of the for loop so they are assigned only once, after switch_cpus and switch_cpus_1 are constructed.
2011-03-28This patch supports cache flushing in MOESI_hammerSomayeh Sardashti
2011-03-28Config: Import math in MI_example.pyNilay Vaish
2011-03-25ruby: fixed cache index settingBrad Beckmann
2011-03-21This patch adds the network tester for simple and garnet networks.Tushar Krishna
The tester code is in testers/networktest. The tester can be invoked by configs/example/ruby_network_test.py. A dummy coherence protocol called Network_test is also addded for network-only simulations and testing. The protocol takes in messages from the tester and just pushes them into the network in the appropriate vnet, without storing any state.
2011-03-19configs: combine ruby_se.py and se.py to avoid all that code duplicationLisa Hsu
2011-03-19enable x86 workloads on se.pyLisa Hsu
2011-03-19se.py: Modify script to make multiprogramming much easier.Lisa Hsu
Now, instead of --bench benchname, you can do --bench bench1-bench2-bench3 and it will set up a simulation that instantiates those three workloads. Only caveat is that now, for sanity checking, your -n X must match the number of benches in the list.
2011-03-17ARM: Bare metal system should have 256MB of RAM.Ali Saidi
2011-03-17Mem: Fix issue with dirty block being lost when entire block transferred to ↵Ali Saidi
non-cache. This change fixes the problem for all the cases we actively use. If you want to try more creative I/O device attachments (E.g. sharing an L2), this won't work. You would need another level of caching between the I/O device and the cache (which you actually need anyway with our current code to make sure writes propagate). This is required so that you can mark the cache in between as top level and it won't try to send ownership of a block to the I/O device. Asserts have been added that should catch any issues.
2011-02-24Configs: Explicitly import env in Benchmarks.pyGabe Black
env was being implicitly imported into Benchmarks.py through SysPaths.py. This change brings it in explicitly in the file where it's used.
2011-02-23ARM: Clarifies creation of Linux and baremetal ARM systems.Ali Saidi
makeArmSystem creates both bare-metal and Linux systems more cleanly. machine_type was never optional though listed as an optional argument; a system such as "RealView_PBX" must now be explicitly specified. Now that it is a required argument, the placement of the arguments has changed slightly requiring some changes to calls that create ARM systems.
2011-02-23configs: cache: add cache line size optionKorey Sewell
2011-02-23configs: set default cache paramsKorey Sewell
It's confusing (especially to new users), when you are setting some standard parameters (as defined in Options.py) and they aren't reflected in the simulations so we might as well link the settings in CacheConfig.py to those in Options.py
2011-02-11VNC: Add VNC server to M5Ali Saidi
2011-02-08memtest: due to contention increase, increased deadlock thresholdBrad Beckmann
2011-02-08config: fixed minor bug connecting dma devices to rubyBrad Beckmann
2011-02-07X86, Config: Move the setting of work count options to a separate function.Gabe Black
This way things that don't care about work count options and/or aren't called by something that has those command line options set up doesn't have to build a fake object to carry in inert values.
2011-02-06boot: script that creates a checkpoint after Linux boot upBrad Beckmann
2011-02-06ruby: numa bit fix for sparse memoryBrad Beckmann
2011-02-06m5: added work completed monitoring supportBrad Beckmann
2011-02-06ruby: x86 fs config supportBrad Beckmann
2011-02-06MOESI_hammer: Added full-bit directory supportBrad Beckmann
2011-02-03Mem,X86: Make the IO bridge pass APIC messages back towards the CPU.Gabe Black
2011-02-03Config: Keep track of uncached and cached ports separately.Gabe Black
This makes sure that the address ranges requested for caches and uncached ports don't conflict with each other, and that accesses which are always uncached (message signaled interrupts for instance) don't waste time passing through caches.
2011-02-02X86: Change how the default disk image gets set up.Gabe Black
The disk image to use was always being forced to a particular value. This change changes what disk image is selected as the default based on the architecture being built. In the future, a more sophisticated system might be used that selected a path based on certain rules instead of relying on one off file names.
2011-02-01X86: Add L1 caches for the TLB walkers.Gabe Black
Small L1 caches are connected to the TLB walkers when caches are used. This allows them to participate in the coherence protocol properly.
2011-01-19Time: Add a mechanism to prevent M5 from running faster than real time.Gabe Black
M5 skips over any simulated time where it doesn't have any work to do. When the simulation is active, the time skipped is short and the work done at any point in time is relatively substantial. If the time between events is long and/or the work to do at each event is small, it's possible for simulated time to pass faster than real time. When running a benchmark that can be good because it means the simulation will finish sooner in real time. When interacting with the real world through, for instance, a serial terminal or bridge to a real network, this can be a problem. Human or network response time could be greatly exagerated from the perspective of the simulation and make simulated events happen "too soon" from an external perspective. This change adds the capability to force the simulation to run no faster than real time. It does so by scheduling a periodic event that checks to see if its simulated period is shorter than its real period. If it is, it stalls the simulation until they're equal. This is called time syncing. A future change could add pseudo instructions which turn time syncing on and off from within the simulation. That would allow time syncing to be used for the interactive parts of a session but then turned off when running a benchmark using the m5 utility program inside a script. Time syncing would probably not happen anyway while running a benchmark because there would be plenty of work for M5 to do, but the event overhead could be avoided.