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path: root/src/arch/riscv/isa/decoder.isa
AgeCommit message (Expand)Author
2018-05-12arch-riscv: Update CSR implementationsAlec Roelke
2018-03-20riscv: throw IllegalInstFault when decoding invalid instructionsTuan Ta
2018-02-19arch-riscv: Fix compressed branch op offsetAlec Roelke
2018-01-16arch-riscv: Fix floating-poing op classesAlec Roelke
2018-01-16arch-riscv: Fix floating-point conversion bugsAlec Roelke
2018-01-10arch-riscv: Make use of ImmOp's polymorphismAlec Roelke
2017-11-29arch-riscv: Move parts of mem insts out of ISAAlec Roelke
2017-07-14riscv: Disambiguate between the C and C++ versions of isnan and isinf.Gabe Black
2017-07-14riscv: Fix bugs with RISC-V decoder and detailed CPUsAlec Roelke
2017-07-11arch-riscv: Add support for compressed extension RV64CAlec Roelke
2017-07-11arch-riscv: Restructure ISA descriptionAlec Roelke
2017-04-05riscv: fix Linux problems with LR and SC opsAlec Roelke
2016-11-30riscv: [Patch 7/5] Corrected LRSC semanticsAlec Roelke
2016-11-30riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64AAlec Roelke
2016-11-30riscv: [Patch 3/5] Added RISCV floating point extensions RV64FDAlec Roelke
2016-11-30riscv: [Patch 2/5] Added RISC-V multiply extension RV64MAlec Roelke
2016-11-30arch: [Patch 1/5] Added RISC-V base instruction set RV64IAlec Roelke