Age | Commit message (Collapse) | Author |
|
into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops
src/arch/sparc/faults.hh:
Hand merged.
--HG--
extra : convert_revision : 1bcefe47fa98e878a0dfbcfa5869b5b171927911
|
|
--HG--
extra : convert_revision : eb7e016a127417cbb0e1e2c733b17f82469c2f24
|
|
--HG--
extra : convert_revision : 6339c82d3655694445c3eb43e467b9aa6b4c8224
|
|
Apparently, gdb expects to do single stepping on its own, so those functions panic for SPARC. acc still needs to be implemented.
--HG--
extra : convert_revision : c6e98e37b8ab3d6f8d6b3cd2c961faa65b08a179
|
|
--HG--
extra : convert_revision : 1626703583f02a1c9823874290462c1b6bdb6c3c
|
|
--HG--
extra : convert_revision : ba08da78693cc6f59f7358134f121f471910dbf6
|
|
--HG--
extra : convert_revision : ba31171a81b6c46de2997de2701d35fcf8c614b7
|
|
--HG--
rename : src/kern/alpha/idle_event.cc => src/arch/alpha/idle_event.cc
rename : src/kern/alpha/idle_event.hh => src/arch/alpha/idle_event.hh
rename : src/kern/alpha/kernel_stats.cc => src/arch/alpha/kernel_stats.cc
rename : src/kern/alpha/kernel_stats.hh => src/arch/alpha/kernel_stats.hh
rename : src/kern/sparc/kernel_stats.hh => src/arch/sparc/kernel_stats.hh
rename : src/kern/base_kernel_stats.cc => src/kern/kernel_stats.cc
rename : src/kern/base_kernel_stats.hh => src/kern/kernel_stats.hh
extra : convert_revision : 42bd3e36b407edbd19b912c9218f4e5923a15966
|
|
--HG--
extra : convert_revision : ea1e54a529ad7ae4a6564dd6fb47c31fb0573adf
|
|
--HG--
extra : convert_revision : 9df68973c63d5ff256d6de485e8d918c454c8ff1
|
|
--HG--
extra : convert_revision : 24ab1789496c5fae6c0992db2d521ea02354ee90
|
|
--HG--
extra : convert_revision : 4d4b866699e3450b88418822fc198411ee3d831a
|
|
--HG--
extra : convert_revision : 335b458d195a00dac3d04e92fe9df915e660538f
|
|
--HG--
extra : convert_revision : 8c528fab56a95b8245ad0f2572d62bb556ce0dde
|
|
into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops
src/SConscript:
SCCS merged
--HG--
extra : convert_revision : f130c8a2d33f58d857e5d5a02bb9698c1bceb23b
|
|
--HG--
extra : convert_revision : 7257e3387c01e84e5a1018a9cdcc09a79edfa934
|
|
but isn't tested. Other architectures will not.
--HG--
extra : convert_revision : fc7e1e73e2f3b1a4ab9905a1eb98c5f07c6c8707
|
|
SConstruct:
Add check to see if we need to include libsocket
src/arch/sparc/floatregfile.cc:
src/arch/sparc/intregfile.cc:
use memset rather than bzero and include the appropriate headerfile
src/base/pollevent.cc:
If we're compling under solaris we need sys/file.h
src/base/random.cc:
src/base/random.hh:
solaris doesn't have random(), so use rint with the correct rounding mode
if we're compiling on solaris
src/base/stats/flags.hh:
u_int32_t??
src/base/time.hh:
grab the timersub() define from freebsd since it doesn't exist in solaris
src/cpu/inst_seq.hh:
we don't need to include stdint here
src/sim/byteswap.hh:
the method to detect endianness on Solaris is a little more complex...
--HG--
extra : convert_revision : 6b7db0e900e7bccfc250d65c125065f27280dda1
|
|
--HG--
extra : convert_revision : cf7faf5001b31d61c61ddce2386d61c919075800
|
|
--HG--
extra : convert_revision : 9e65af095c37c7c67db377424d2d4363fa8065f9
|
|
because apparently you need an xc for that and not a tc. Cleaned up the TrapInstruction fault in light of this.
--HG--
extra : convert_revision : 1805c9244cfd62d0ee7862d8fd7c9983e00c5747
|
|
--HG--
extra : convert_revision : 6767dc1305a58e3e7eb0ee909d54768e51744927
|
|
PowerOnReset fault to kick start the CPU.
--HG--
extra : convert_revision : 79e1fa2ef40e326682069639e260db255fd29d93
|
|
--HG--
extra : convert_revision : 44d67a3bb95f875f17586499aa4a04268aa2fd46
|
|
could be improved and syscalls could be called from the trap's invoke method.
--HG--
extra : convert_revision : 127a3673a076110fb3605c0fbc93e8d7e9fec84b
|
|
--HG--
extra : convert_revision : a1cdd35c74f6e85f42a04061b466ec7617da8ac2
|
|
src/arch/sparc/faults.cc:
Moved some code here from miscregfile.cc
src/arch/sparc/miscregfile.cc:
Moved code from here to faults.cc, and merged (read|set)MiscRegWithEffect and it's FS version from ua2005.cc
src/arch/sparc/miscregfile.hh:
readFSRegWithEffect is no longer a seperate function, and is instead done in the main readRegWith Effect.
--HG--
extra : convert_revision : 0b45f0f78e83929b32ddd2f443c8b1dbf9bc04fb
|
|
system.cc
--HG--
extra : convert_revision : 2a124adcefe0d15860632a05e8788d3fd34008c2
|
|
--HG--
extra : convert_revision : bebc701508e1d38ee74a07377c634d5e46e89abe
|
|
file functions to not take faults
--HG--
extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675
|
|
--HG--
extra : convert_revision : 46e9f26917efab642b80ea9e4303ec95d43d935e
|
|
in the future for micro insts.
--HG--
extra : convert_revision : c71faa5e43b56ed15d00ed5fd57c020d1c845445
|
|
--HG--
extra : convert_revision : ab6cd69f82b2013d66a91beaa3e39d8f417a9251
|
|
src/arch/sparc/isa/decoder.isa:
Fix up the casa and casxa instructions.
src/arch/sparc/isa/formats/formats.isa:
This is handled in loadstore.isa now
src/arch/sparc/isa/formats/mem/basicmem.isa:
src/arch/sparc/isa/formats/mem/blockmem.isa:
Renamed doSplitExecute to doDualSplitExecute. This differentiates between the version that does both a register and immediate version, and one that just does a register version.
src/arch/sparc/isa/formats/mem/mem.isa:
The cas format is handled in loadstore.isa as well now.
src/arch/sparc/isa/formats/mem/util.isa:
Reorganized things a bit to better support cas
--HG--
extra : convert_revision : 12411e89e763287e52f9825bf7a417b263c1037f
|
|
the integer microcode register.
--HG--
extra : convert_revision : 7df5bd4bbe8a2607c7d2b4799826831d6a440926
|
|
--HG--
extra : convert_revision : f23dbfdfe44e8e6cdd6948000669ad4f743b9fb4
|
|
--HG--
extra : convert_revision : 30fa768c4a934cf5f9dc0ad84e0e421327ccbed3
|
|
--HG--
extra : convert_revision : d63ea6fb1e549e737204ee6653c06f89ec5e43ef
|
|
--HG--
extra : convert_revision : 3bc792596c99df3a5c2c82da58b801a63ccf6ddb
|
|
--HG--
extra : convert_revision : 088112c9b8a4ea09c8015da5a0b65ed2fc9398d2
|
|
--HG--
extra : convert_revision : a7050aa8768c132f0161f00ba17ae02d71f0b829
|
|
--HG--
extra : convert_revision : ae557307f377b19bae82226dafa8b4b2654cae52
|
|
--HG--
extra : convert_revision : 6e98cf839dc92bde5f06f9b9bf11ca6ac661c907
|
|
--HG--
extra : convert_revision : bedf422d51a52b009390b1e94f5330f752be2b87
|
|
src/arch/sparc/isa/formats/priv.isa:
Fix the priv format so that it uses isa_parser operands rather than accessing the registers directly in checkCode. Also, the expressions needed to be negated.
src/arch/sparc/isa/operands.isa:
Added an Hpstate operand, and adjusted the numbering.
--HG--
extra : convert_revision : 4a70862df061aa9e1b9eab125c4c2fc839ac3b5a
|
|
instructions so that the cwp is modified at the correct time (when handling the fault), and fixed the "done" instruction.
--HG--
extra : convert_revision : 3c9144422f087af1d375782cce1c9b77ca7936c9
|
|
--HG--
extra : convert_revision : 040beb4dd982784773c3c3ad04cc48c2dc98b58c
|
|
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
Added a function to do normal SPARC trap processing, and implemented the spill and fill faults for SE
src/arch/sparc/process.cc:
src/arch/sparc/process.hh:
Added fill and spill handlers which are stuffed into the processes address space. The location of these handlers are stored in fillStart and spillStart.
--HG--
extra : convert_revision : 59adb96570cce86f373fbc2c3e4c05abe1742d3b
|
|
--HG--
extra : convert_revision : bed03e63dc80bf24f21bad08e6553d7aab92c7b3
|
|
with the timing cpu
--HG--
extra : convert_revision : 37358504c4d05d78d08c19ba3d0c99d38c4babf5
|