gem5 - gem5

Age	Commit message (Expand)	Author
2017-05-26	x86: Rework how VEX prefixes are decoded.	Gabe Black
2015-10-12	misc: Remove redundant compiler-specific defines	Andreas Hansson
2015-10-09	isa: Add parameter to pick different decoder inside ISA	Rekai Gonzalez Alberquilla
2015-07-17	x86: decode instructions with vex prefix	Nilay Vaish
2014-12-04	x86: Rework opcode parsing to support 3 byte opcodes properly.	Gabe Black
2013-01-22	x86, cpu: corrects 270c9a75e91f, take over decoder on cpu switch	Nilay Vaish
2013-01-04	Decoder: Remove the thread context get/set from the decoder.	Gabe Black
2013-01-04	X86: Move address based decode caching in front of the predecoder.	Gabe Black
2012-06-04	X86: Ensure that the decoder's internal ExtMachInst is completely initialized.	Gabe Black
2012-05-26	ISA,CPU: Generalize and split out the components of the decode cache.	Gabe Black
2012-05-26	CPU: Merge the predecoder and decoder.	Gabe Black
2012-05-25	ISA: Make the decode function part of the ISA's decoder.	Gabe Black
2012-05-25	Decode: Make the Decoder class defined per ISA.	Gabe Black