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lsq_unit_impl.hh
Age
Commit message (
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Author
2012-03-09
CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable
Geoffrey Blake
2012-01-31
CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5
Geoffrey Blake
2012-01-28
O3 CPU LSQ: Implement TSO
Nilay Vaish
2011-09-27
O3: Tidy up some DPRINTFs in the LSQ.
Gabe Black
2011-09-27
Faults: Replace calls to genMachineCheckFault with M5PanicFault.
Gabe Black
2011-09-26
LSQ: Moved a couple of lines to enable O3 + Ruby
Nilay Vaish
2011-09-22
event: minor cleanup
Steve Reinhardt
2011-09-13
LSQ: Only trigger a memory violation with a load/load if the value changes.
Ali Saidi
2011-07-31
O3: Implement memory mapped IPRs for O3.
Gabe Black
2011-05-04
O3: Fix a small corner case with the lsq hazard detection logic.
Ali Saidi
2011-04-20
stats: one more name violation
Nathan Binkert
2011-04-15
trace: reimplement the DTRACE function so it doesn't use a vector
Nathan Binkert
2011-04-15
includes: sort all includes
Nathan Binkert
2011-04-04
O3: Tighten memory order violation checking to 16 bytes.
Ali Saidi
2011-03-17
O3: Fix unaligned stores when cache blocked
Ali Saidi
2011-02-11
O3: Enhance data address translation by supporting hardware page table walkers.
Giacomo Gabrielli
2011-01-18
O3: Fix corner cases where multiple squashes/fetch redirects overwrite timebuf.
Matt Horsnell
2011-01-18
ARM: Add support for moving predicated false dest operands from sources.
Ali Saidi
2011-01-07
Replace curTick global variable with accessor functions.
Steve Reinhardt
2010-12-07
O3: Support SWAP and predicated loads/store in ARM.
Min Kyu Jeong
2010-10-31
ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
Gabe Black
2010-08-23
O3: Skipping mem-order violation check for uncachable loads.
Min Kyu Jeong
2010-08-23
CPU: Make Exec trace to print predication result (if false) for memory instru...
Min Kyu Jeong
2010-08-23
O3: Handle loads when the destination is the PC.
Min Kyu Jeong
2010-08-23
ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.
Min Kyu Jeong
2010-02-12
O3PCU: Split loads and stores that cross cache line boundaries.
Timothy M. Jones
2009-09-23
arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
Nathan Binkert
2009-05-26
types: add a type for thread IDs and try to use it everywhere
Nathan Binkert
2009-04-19
Mem: Change isLlsc to isLLSC.
Gabe Black
2009-04-19
Memory: Rename LOCKED for load locked store conditional to LLSC.
Gabe Black
2008-10-09
eventq: convert all usage of events to use the new API.
Nathan Binkert
2008-08-11
params: Convert the CPU objects to use the auto generated param structs.
Nathan Binkert
2008-02-06
Make the Event::description() a const function
Stephen Hines
2007-08-26
Merge with head
Gabe Black
2007-08-21
o3: Fix for retry ID bug.
Kevin Lim
2007-07-23
Fix WriteReq/StoreCondReq setting in O3.
Steve Reinhardt
2007-06-30
Make CPU models use new LoadLockedReq/StoreCondReq commands.
Steve Reinhardt
2007-06-30
Event descriptions should not end in "event"
Steve Reinhardt
2007-06-30
Get rid of Packet result field. Error responses are
Steve Reinhardt
2007-04-26
Remove extra delete that was causing segfault.
Kevin Lim
2007-04-08
Get the "hard" SPARC instructions working in o3. I don't like that the IsStor...
Gabe Black
2007-04-04
Merge zizzer.eecs.umich.edu:/bk/newmem
Gabe Black
2007-04-04
Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU f...
Kevin Lim
2007-04-03
Made the "data" field of store queue entries into a character array. It's siz...
Gabe Black
2007-04-03
Fix a memory leak. Hopefully this fixes the longer running benchmarks.
Kevin Lim
2007-04-02
Remove/comment out DPRINTFs that were causing a segfault.
Kevin Lim
2007-03-23
Merge ktlim@zizzer:/bk/newmem
Kevin Lim
2007-03-23
Two fixes:
Kevin Lim
2007-02-07
Make memory commands dense again to avoid cache stat table explosion.
Steve Reinhardt
2006-12-16
Make sure endian conversion is done on the memory data when it's just set to ...
Gabe Black
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