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path: root/src/cpu/simple/atomic.cc
AgeCommit message (Expand)Author
2008-08-11params: Convert the CPU objects to use the auto generated param structs.Nathan Binkert
2008-07-01Make the cached virtPort have a thread context so it can do everything that a...Ali Saidi
2008-07-01After a checkpoint (and thus a stats reset), the not_idle_fraction/notIdleFra...Ali Saidi
2008-06-18AtomicSimpleCPU: Separate data stalls from instruction stalls.Nathan Binkert
2008-06-12CPU: Make the simple cpu trace data for loads/stores.Gabe Black
2008-02-14CPU: move the PC Events code to a place where the code won't be executed mult...Ali Saidi
2008-02-06Make the Event::description() a const functionStephen Hines
2008-01-02Additional comments and helper functions for PrintReq.Steve Reinhardt
2007-12-16CPU: Update where the simple cpus read their cpu id from the thread context t...Ali Saidi
2007-11-20Simple CPU fix simple mistake in translateDataWriteAddr.Gabe Black
2007-11-08AtomicSimpleCPU: Refactor resume() code to have a cleaner control path.Ali Saidi
2007-10-22CPU: Add functions to the "ExecContext"s that translate a given address.Gabe Black
2007-10-18CPU: Use the ThreadContext cpu id instead of the params cpu id in all cases.Ali Saidi
2007-09-28Update stats for quiesced cyclesAli Saidi
2007-09-28Rename cycles() function to ticks()Ali Saidi
2007-08-26Merge with headGabe Black
2007-08-26Simple CPU: Don't trace instructions that fault. Otherwise they show up twice.Gabe Black
2007-08-26Simple CPU: Added code that will split requests that cross block boundaries i...Gabe Black
2007-08-26Simple CPU: Make sure only instructions which complete without faulting are c...Gabe Black
2007-08-26Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.Gabe Black
2007-08-08Added fastmem option.Vincentius Robby
2007-08-04SimpleCPU: Add some DPRINTFsNathan Binkert
2007-07-29Merge Gabe's changes from head.Steve Reinhardt
2007-07-28Turn the instruction tracing code into pluggable sim objects.Gabe Black
2007-07-28AtomicSimpleCPU: fix inadvertent loss of endian conversion on read.Steve Reinhardt
2007-07-26Merge python and x86 changes with cache branchNathan Binkert
2007-07-23Major changes to how SimObjects are created and initialized. Almost allNathan Binkert
2007-06-30Make CPU models use new LoadLockedReq/StoreCondReq commands.Steve Reinhardt
2007-06-30Event descriptions should not end in "event"Steve Reinhardt
2007-06-30Get rid of Packet result field. Error responses areSteve Reinhardt
2007-06-19Make branches work by repopulating the predecoder every time through. This is...Gabe Black
2007-06-12Make microOp vs microop and macroOp vs macroop capitilization consistent.Gabe Black
2007-05-18Changes to make simple cpu handle pcs appropriately for x86Gabe Black
2007-04-10Even if you don't want to fetch more bytes, make sure you handle a fault.Gabe Black
2007-03-15Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2007-03-15Make the predecoder an object with it's own switched header file. Start addin...Gabe Black
2007-03-11Make sttw and sttwa use the twin memory operations.Gabe Black
2007-03-09Two fixes:Kevin Lim
2007-03-02make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way a...Ali Saidi
2007-02-12some forgotten commitsAli Saidi
2007-02-12Merge zizzer:/bk/newmemAli Saidi
2007-02-12rename store conditional stuff as extra data so it can be used for conditiona...Ali Saidi
2007-02-12Move store conditional result checking from SimpleAtomicCpu writeSteve Reinhardt
2007-02-07Make memory commands dense again to avoid cache stat table explosion.Steve Reinhardt
2007-01-16Modify ISA and staticInst to support a IsFirstMicroOp flagAli Saidi
2006-12-04More changes to get SPARC fs closer. Now at 1.2M cycles before differenceAli Saidi
2006-11-29Merge zizzer:/bk/newmemAli Saidi
2006-11-29Add support for mmapped iprs to atomic cpuAli Saidi
2006-11-29Change the connecting of the physPort and virtPort to the memory object below...Kevin Lim
2006-11-17Make an initialization pass for the thread context and set the [phys,virt]Por...Ron Dreslinski