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gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
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path:
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src
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cpu
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simple
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timing.cc
Age
Commit message (
Expand
)
Author
2014-01-24
mem: track per-request latencies and access depths in the cache hierarchy
Matt Horsnell
2013-08-19
cpu: Accurately count idle cycles for simple cpu
Lena Olson
2013-08-19
cpu: Fix timing CPU drain check
Andreas Hansson
2013-07-18
mem: Set the cache line size on a system level
Andreas Hansson
2013-04-22
sim: separate nextCycle() and clockEdge() in clockedObjects
Dam Sunwoo
2013-02-15
sim: Add a system-global option to bypass caches
Andreas Sandberg
2013-02-15
cpu: Refactor memory system checks
Andreas Sandberg
2013-01-07
cpu: Unify the serialization code for all of the CPU models
Andreas Sandberg
2013-01-07
cpu: Make sure that a drained timing CPU isn't executing ucode
Andreas Sandberg
2013-01-07
cpu: Rename defer_registration->switched_out
Andreas Sandberg
2013-01-07
cpu: Correctly call parent on switchOut() and takeOverFrom()
Andreas Sandberg
2013-01-07
cpu: Check that the memory system is in the correct mode
Andreas Sandberg
2012-11-02
sim: Move the draining interface into a separate base class
Andreas Sandberg
2012-08-28
Clock: Add a Cycles wrapper class and use where applicable
Andreas Hansson
2012-08-28
Clock: Rework clocks to avoid tick-to-cycle transformations
Andreas Hansson
2012-08-22
Packet: Remove NACKs from packet and its use in endpoints
Andreas Hansson
2012-08-15
O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...
Anthony Gutierrez
2012-06-05
cpu: Don't init simple and inorder CPUs if they are defered.
Anthony Gutierrez
2012-05-01
MEM: Separate requests and responses for timing accesses
Andreas Hansson
2012-04-14
MEM: Remove the Broadcast destination from the packet
Andreas Hansson
2012-04-14
MEM: Separate snoops and normal memory requests/responses
Andreas Hansson
2012-03-30
CPU: Unify initMemProxies across CPUs and simulation modes
Andreas Hansson
2012-02-24
CPU: Round-two unifying instr/data CPU ports across models
Andreas Hansson
2012-02-12
mem: Add a master ID to each request object.
Ali Saidi
2012-01-31
Merge with head, hopefully the last time for this batch.
Gabe Black
2012-01-31
clang: Enable compiling gem5 using clang 2.9 and 3.0
Koan-Sin Tan
2012-01-28
Merge with the main repo.
Gabe Black
2012-01-17
MEM: Simplify ports by removing EventManager
Andreas Hansson
2012-01-17
CPU: Moving towards a more general port across CPU models
Andreas Hansson
2012-01-17
MEM: Add port proxies instead of non-structural ports
Andreas Hansson
2011-11-18
SE/FS: Get rid of FULL_SYSTEM in the CPU directory.
Gabe Black
2011-11-01
SE/FS: Expose the same methods on the CPUs in SE and FS modes.
Gabe Black
2011-08-07
Translation: Use a pointer type as the template argument.
Gabe Black
2011-07-02
ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem.
Gabe Black
2011-07-02
ExecContext: Get rid of the now unused read/write templated functions.
Gabe Black
2011-05-04
CPU: Add some useful debug message to the timing simple cpu.
Ali Saidi
2011-05-04
CPU: Fix a case where timing simple cpu faults can nest.
Ali Saidi
2011-04-15
trace: reimplement the DTRACE function so it doesn't use a vector
Nathan Binkert
2011-04-15
includes: sort all includes
Nathan Binkert
2011-03-17
ARM: Detect and skip udelay() functions in linux kernel.
Ali Saidi
2011-03-01
Spelling: Fix the a spelling error by changing mmaped to mmapped.
Gabe Black
2011-02-11
SimpleCPU: Fix a case where a DTLB fault redirects fetch and an I-side walk o...
Ali Saidi
2011-02-06
TimingSimpleCPU: split data sender state fix
Joel Hestness
2011-02-06
mcpat: Adds McPAT performance counters
Joel Hestness
2011-01-07
Replace curTick global variable with accessor functions.
Steve Reinhardt
2010-11-15
CPU: Fix bug when a split transaction is issued to a faster cache
Ali Saidi
2010-11-08
ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.
Ali Saidi
2010-10-31
ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
Gabe Black
2010-09-30
CPU/Cache: Fix some errors exposed by valgrind
Ali Saidi
2010-09-13
Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.
Gabe Black
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