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path: root/src/cpu/simple
AgeCommit message (Expand)Author
2014-01-24mem: track per-request latencies and access depths in the cache hierarchyMatt Horsnell
2014-01-24cpu: remove faulty simpoint basic block inst count assertionDam Sunwoo
2013-10-15cpu: add a condition-code register classYasuko Eckert
2013-10-15cpu: rename *_DepTag constants to *_Reg_BaseSteve Reinhardt
2013-08-20cpu: Fix timing CPU isDrained comment formattingAndreas Hansson
2013-08-19cpu: Accurately count idle cycles for simple cpuLena Olson
2013-08-19cpu: Fix timing CPU drain checkAndreas Hansson
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
2013-05-30cpu: Make hash struct instead of class to please clangAndreas Hansson
2013-04-22sim: separate nextCycle() and clockEdge() in clockedObjectsDam Sunwoo
2013-04-22cpu: generate SimPoint basic block vector profilesDam Sunwoo
2013-03-26cpu: Remove CpuPort and use MasterPort in the CPU classesAndreas Hansson
2013-02-15sim: Add a system-global option to bypass cachesAndreas Sandberg
2013-02-15cpu: Refactor memory system checksAndreas Sandberg
2013-02-15cpu: Add CPU metadata om the Python classesAndreas Sandberg
2013-01-12base simple cpu: removes commented out code about cache opsNilay Vaish
2013-01-12x86: Changes to decoder, corrects 9376Nilay Vaish
2013-01-07cpu: Unify the serialization code for all of the CPU modelsAndreas Sandberg
2013-01-07cpu: Make sure that a drained atomic CPU isn't executing ucodeAndreas Sandberg
2013-01-07cpu: Make sure that a drained timing CPU isn't executing ucodeAndreas Sandberg
2013-01-07cpu: Rename defer_registration->switched_outAndreas Sandberg
2013-01-07cpu: Correctly call parent on switchOut() and takeOverFrom()Andreas Sandberg
2013-01-07cpu: Check that the memory system is in the correct modeAndreas Sandberg
2013-01-07arch: Make the ISA class inherit from SimObjectAndreas Sandberg
2013-01-04Decoder: Remove the thread context get/set from the decoder.Gabe Black
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
2012-09-25ARM: Squash outstanding walks when instructions are squashed.Ali Saidi
2012-09-19AddrRange: Transition from Range<T> to AddrRangeAndreas Hansson
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
2012-08-28Clock: Rework clocks to avoid tick-to-cycle transformationsAndreas Hansson
2012-08-22Packet: Remove NACKs from packet and its use in endpointsAndreas Hansson
2012-08-15O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...Anthony Gutierrez
2012-07-09Port: Align port names in C++ and PythonAndreas Hansson
2012-07-09Port: Move retry from port base class to Master/SlavePortAndreas Hansson
2012-06-08Timing CPU: Remove a redundant port pointerAndreas Hansson
2012-06-05cpu: Don't init simple and inorder CPUs if they are defered.Anthony Gutierrez
2012-05-26CPU: Merge the predecoder and decoder.Gabe Black
2012-05-25Decode: Make the Decoder class defined per ISA.Gabe Black
2012-05-01MEM: Separate requests and responses for timing accessesAndreas Hansson
2012-04-15CPU: Tidy up some formatting and a DPRINTF in the simple CPU base class.Gabe Black
2012-04-14MEM: Remove the Broadcast destination from the packetAndreas Hansson
2012-04-14MEM: Separate snoops and normal memory requests/responsesAndreas Hansson
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
2012-04-03Atomic: Remove the physmem_port and access memory directlyAndreas Hansson
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-03-30CPU: Unify initMemProxies across CPUs and simulation modesAndreas Hansson
2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
2012-02-24CPU: Round-two unifying instr/data CPU ports across modelsAndreas Hansson
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
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