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path: root/src/cpu
AgeCommit message (Expand)Author
2006-07-20Enforce the timing cpu ticking at it's clock rateAli Saidi
2006-07-19Minor changes to reflect state used for regression stats.Kevin Lim
2006-07-19Put regression tests back into m5. They are located in the "tests" directory...Kevin Lim
2006-07-19O3CPU fixes.Kevin Lim
2006-07-19Some minor compiling fixes.Kevin Lim
2006-07-14Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-07-14Fix the CheckerCPU being included via python.Kevin Lim
2006-07-14forgot tidKorey Sewell
2006-07-14For now, halt context is the same as deallocating.Korey Sewell
2006-07-13Move Dcache port creation from LSQUnit to LSQ in order to support Ron's recen...Kevin Lim
2006-07-13Fix for bug when squashing and the fetching. Now fetch checks if the cache d...Kevin Lim
2006-07-13Update for changes to draining.Kevin Lim
2006-07-12memory mode information now contained in system objectAli Saidi
2006-07-12Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-07-12Serialization changes to make O3CPU consistent with the other models.Kevin Lim
2006-07-12Updates for serialization. As long as the tickEvent doesn't need to be seria...Kevin Lim
2006-07-12Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-07-12Track the PC of the cache data stored in fetch so it doesn't access memory mu...Kevin Lim
2006-07-11Fix ordering issue with squashed Icache Fetches and Static data in packet.Ron Dreslinski
2006-07-10Minor fixes.Kevin Lim
2006-07-10Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-07-10Some minor cleanups.Kevin Lim
2006-07-10Add parameters for backwards and forwards sizes for time buffers.Kevin Lim
2006-07-10Fix cpu in full system to match SE.Ron Dreslinski
2006-07-07Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemKorey Sewell
2006-07-07Support for recent port changes.Kevin Lim
2006-07-07Support Ron's changes for hooking up ports.Kevin Lim
2006-07-07Fix for bug when draining and a memory access is outstanding.Kevin Lim
2006-07-07Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-07-07Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemKorey Sewell
2006-07-07Minor fix for SMT Hello Worlds to finish correctly.Korey Sewell
2006-07-07Switch out fixes for CPUs.Kevin Lim
2006-07-07Remove hack now that ports work properlyRon Dreslinski
2006-07-07Update cpus to use the getPort function to use a connector object to connect ...Ron Dreslinski
2006-07-07Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemKorey Sewell
2006-07-07Fix so that O3CPU doesnt segfault on exit.Korey Sewell
2006-07-06Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-07-06Support serializing and unserializing in the O3 CPU. Also a few small fixes ...Kevin Lim
2006-07-06Fix the O3CPU to support the multi-pass method for checking if the system has...Kevin Lim
2006-07-06Various serialization changes to make it possible for the O3CPU to checkpoint.Kevin Lim
2006-07-06Timing cache works for hello world test.Ron Dreslinski
2006-07-06Fixes for draining.Kevin Lim
2006-07-06Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-07-06Support for draining, and the new method of switching out. Now switching out...Kevin Lim
2006-07-06Had to add this because for some reason gcc wasnt recognizing "THE_ISA == ALP...Korey Sewell
2006-07-06Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemKorey Sewell
2006-07-06Use O3DynInst in cpu_models.py and in static_inst_exec_sigs.hh instead of a s...Korey Sewell
2006-07-06more steps toward O3 SMTKorey Sewell
2006-07-05Remove sampler and serializer. Now they are handled through C++ interacting ...Kevin Lim
2006-07-05Rename quiesce to drain to avoid confusion with the pseudo instruction.Kevin Lim
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