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RubySlicc_Types.sm
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Author
2016-01-19
gpu-compute: AMD's baseline GPU model
Tony Gutierrez
2016-01-19
mem: write combining for ruby protocols
Tony Gutierrez
2016-01-19
* * *
Tony Gutierrez
2015-07-20
mem: misc flags for AMD gpu model
Blake Hechtman
2015-09-23
ruby: bloom filters: refactor code
Nilay Vaish
2015-09-16
ruby: message buffer, timer table: significant changes
Nilay Vaish
2015-09-05
ruby: call setMRU from L1 controllers, not from sequencer
Nilay Vaish
2015-08-19
ruby: reverts to changeset: bf82f1f7b040
Nilay Vaish
2015-08-14
ruby: add accessor functions to SLICC def of MachineID
Nilay Vaish
2015-08-14
ruby: call setMRU from L1 controllers, not from sequencer
Nilay Vaish
2015-08-14
ruby: replace Address by Addr
Nilay Vaish
2015-07-20
ruby: adds size and empty apis to the msg buffer stallmap
David Hashe
2015-07-20
ruby: fix deadlock bug in banked array resource checks
David Hashe
2015-07-20
ruby: allocate a block in CacheMemory without updating LRU state
David Hashe
2015-07-20
ruby: speed up function used for cache walks
David Hashe
2015-07-20
ruby: give access to cache tag/data latencies from SLICC
David Hashe
2014-11-06
ruby: interface with classic memory controller
Nilay Vaish
2014-11-06
ruby: coherence protocols: remove data block from dirctory entry
Nilay Vaish
2014-05-23
ruby: message buffer: drop dequeue_getDelayCycles()
Nilay Vaish
2013-06-25
ruby: profiler: lots of inter-related changes
Nilay Vaish
2013-05-21
ruby: add stats to .sm files, remove cache profiler
Nilay Vaish ext:(%2C%20Malek%20Musleh%20%3Cmalek.musleh%40gmail.com%3E)
2013-02-28
ruby: mesi coherence protocol: invalidate lock
Dibakar Gope ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2013-02-10
ruby: replace Time with Cycles (final patch in the series)
Nilay Vaish
2013-02-10
ruby: replaces Time with Cycles in many places
Nilay Vaish
2013-01-14
Ruby: use ClockedObject in Consumer class
Nilay Vaish
2012-12-11
ruby: add support for prefetching to MESI protocol
Nilay Vaish
2012-10-15
ruby: allow function definition in slicc structs
Nilay Vaish
2012-07-10
ruby: banked cache array resource model
Brad Beckmann
2012-07-10
ruby: tag and data cache access support
Joel Hestness
2012-01-23
O3, Ruby: Forward invalidations from Ruby to O3 CPU
Nilay Vaish
2011-12-31
SLICC: Use pointers for directory entries
Nilay Vaish
2011-11-03
Ruby: Remove some unused typedefs
Nilay Vaish
2011-06-08
Ruby: Correctly set access permissions for directory entries
Nilay Vaish
2011-03-31
CacheMemory: add allocateVoid() that is == allocate() but no return value.
Lisa Hsu
2011-03-31
Ruby: Add new object called WireBuffer to mimic a Wire.
Lisa Hsu
2011-03-31
Ruby: pass Packet->Req->contextId() to Ruby.
Lisa Hsu
2011-03-22
Ruby: Remove CacheMsg class from SLICC
Nilay Vaish
2011-03-19
Ruby: Convert AccessModeType to RubyAccessMode
Nilay Vaish
2011-03-18
SLICC: Remove external_type for structures
Nilay Vaish
2011-02-23
ruby: automate permission setting
Brad Beckmann
2011-01-17
Change interface between coherence protocols and CacheMemory
Nilay Vaish
2010-08-20
MOESI_hammer: break down miss latency stalled cycles
Brad Beckmann
2010-08-20
ruby: Fixed L2 cache miss profiling
Brad Beckmann
2010-08-20
ruby: Reincarnated the responding machine profiling
Brad Beckmann
2010-01-29
ruby: MOESI_CMP_token updates to use the new config system
Brad Beckmann
2010-01-29
ruby: MI_example updates to use the new config system
Brad Beckmann
2010-01-29
ruby: Converted MOESI_hammer dma cntrl to new config system
Brad Beckmann
2010-01-29
ruby: Ruby changes required to use the python config system
Brad Beckmann
2009-08-04
slicc: added MOESI_CMP_directory, DMA SequencerMsg, parameterized controllers
Derek Hower
2009-07-06
ruby: Import the latest ruby changes from gems.
Nathan Binkert
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