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2018-03-20arch, arm: Fix implicit-fallthrough GCC warningsChun-Chen Hsu
GCC 7 generates spurious fallthrough warnings in nested switch blocks where the inner switch block return. There is already a GCC fix [1] submitted for review but, until it is merged into GCC trunk, GEM5 will not build with GCC 7 due to these fallthrough warnings. This patch silences the spurious fallthrough warnings by appending a M5_UNREACHABLE statement in the outer switch cases. Note there is another GEM5 patch [2] to fix other fallthrough warnings. [1] https://gcc.gnu.org/ml/gcc-patches/2018-02/msg01105.html [2] https://gem5-review.googlesource.com/c/public/gem5/+/8541 Change-Id: I97cd8bfa90a88e93cee60cf27a8c93611d11a242 Signed-off-by: Chun-Chen Hsu <chunchenhsu@google.com> Reviewed-on: https://gem5-review.googlesource.com/9101 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-03-20riscv: throw IllegalInstFault when decoding invalid instructionsTuan Ta
If an instruction is invalid, some assertions may in the decoder may fail the entire simulation. Instead, we want to raise an IllegalInstFault instead of failing immediately in the decoder if the invalid instruction is being speculatively executed. Change-Id: I5cb72ba06f07f173922f86897ddfdf677e8c702f Reviewed-on: https://gem5-review.googlesource.com/9261 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Monir Zaman <monir.zaman.m@gmail.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-03-15arm: Fix implicit-fallthrough warnings when building with gcc-7+Siddhesh Poyarekar
gcc 7 onwards have additional heuristics to detect implicit fallthroughs and it fails the build with warnings for ARM as a result. There was one gcc bug[1] that I fixed but the rest are cases that gcc cannot detect due to the point at which it does the fallthrough check. Most of this patch adds __builtin_unreachable() hints in places that throw this warning to indicate to gcc that the fallthrough will never happen. The remaining cases are actually possible fallthroughs due to incorrect code running on the simulator; in which case an Unknown instruction is returned. [1] https://gcc.gnu.org/ml/gcc-patches/2018-02/msg01105.html Change-Id: I1baa9fa0ed15181c10c755c0bd777f88b607c158 Signed-off-by: Siddhesh Poyarekar <siddhesh.poyarekar@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/8541 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-03-15arch-x86,sim-se: Enable prlimit syscallJason Lowe-Power
Change-Id: I15f0e5ddb72578de90ed68866c8a0c1501717d61 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/8921 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-03-15sim-se: Fix fallthrough in prlimitJason Lowe-Power
Change-Id: Ieec4651000b3b4de05ba5ba11fdfa5392a5477e7 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/8904 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-03-15arch-x86,sim-se: Bump kernel version to 3.2Jason Lowe-Power
Current glibc expects at least kernel 3.2. Bump this so syscall emulation with dynamically-linked binaries works. Change-Id: I07077ed2de14c308f6ff79cae677915612557332 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/8903 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-03-15sim-se: Add /sys/devices/system/cpu/online fileJason Lowe-Power
Add the special file /sys/devices/system/cpu/online to the files that gem5 knows how to handle in SE mode. This file lists the CPUs that are active. For instance, in an 8 CPU system it is the following: 0-7 This implementation simply returns a file that is 0-%d where %d is the current number of thread contexts. This file is required for C++11 threads with gcc 4.8 and above. Change-Id: I0b566f77e75e9eca480509814d0fd038a231b940 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/8902 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-03-15arch-arm: Fix unused variable warning in faults.ccNikos Nikoleris
Change-Id: Ife4a2189e140cdefcf53fa88213d8a5225067457 Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9201 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-03-15x86: Add bitfields which can gather/scatter bases and limits.Gabe Black
Add bitfields which can gather/scatter base and limit fields within "normal" segment descriptors, and in TSS descriptors which have the same bitfields in the same positions for those two values. This centralizes the code which manages those bitfields and makes it less likely that a local implementation will be buggy. Change-Id: I9809aa626fc31388595c3d3b225c25a0ec6a1275 Reviewed-on: https://gem5-review.googlesource.com/7661 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-14x86: Simplify the implementations of RDTSC and RDTSCP slightly.Gabe Black
These instructions originally read the TSC into t1 and then unpacked it into eax and edx using a move, a right shift, and then another move. We can combine the second shift and move. The shift will move the upper 32 bits into the lower 32 bits, and clear the upper 32 bits to zero. This has the same effect as moving the lower 32 bits post-shift into another register, since the upper 32 bits will be cleared to zero based on x86 partial register access semantics. Change-Id: Iba85e501c7e84147ad0047f5c555e61bdf8f032b Reviewed-on: https://gem5-review.googlesource.com/9044 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-14x86: Implement the RDTSCP instruction.Gabe Black
This is very similar to RDTSC, except that it requires all younger instructions to retire before it completes, and it writes the TSC_AUX MSR into ECX. I've added an mfence as an iniitial microop to ensure that memory accesses complete before RDTSCP runs, and added an rdval microop at the end to read the TSC_AUX value into ECX. Change-Id: I9766af562b7fd0c22e331b56e06e8818a9e268c9 Reviewed-on: https://gem5-review.googlesource.com/9043 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-14x86: Mark the RDTSC instruction as .serialize_before.Gabe Black
Change-Id: I20bf6a57ea4354aac9267845bb37b70b83d6fcde Reviewed-on: https://gem5-review.googlesource.com/9042 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-14x86: Replace the .serializing directive with .serialize_(before|after).Gabe Black
This makes it explicit which type of serialization you want, and also makes it possible to make a macroop serialize before. The old serializing directive was renamed .serialize_after in the microcode assembler, and throughout the microcode implementation, and its behavior is unchanged. More specifically, it still marks the last microop within the macroop as IsSerializing and IsSerializeAfter. The new .serialize_before directive does something similar and marks the first microop as IsSerializing and IsSerializeBefore. Change-Id: Ia53466c734c651c65400809de7ef903c4a6c3e7e Reviewed-on: https://gem5-review.googlesource.com/9041 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-14arm: Fix maybe-uninitialized GCC warningsChun-Chen Hsu
GCC 7 generates maybe-uninitialized warnings at the code that updates the "dest" variables in the writeVecElem function of neon64_mem.hh file. It is because the generated code does not appropriately initialize the output variable before passing it to the writeVecElem function. This patch initializes the output variable to fix this. Change-Id: I50a8f4e456ccdcaa3db1392ec097017450c56ecb Signed-off-by: Chun-Chen Hsu <chunchenhsu@google.com> Reviewed-on: https://gem5-review.googlesource.com/9121 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-14base: Fix loop range in pngwriterChun-Chen Hsu
The inner loop range limit should be width instead of height. Change-Id: I091c590713c945d4bd04ffcc974d4eb8aa23d1b2 Signed-off-by: Chun-Chen Hsu <chunchenhsu@google.com> Reviewed-on: https://gem5-review.googlesource.com/9081 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-03-14arch-arm: ERET from AArch64 to AArch32 ignore MSBsGiacomo Travaglini
The 32 most significant bits of ELR_ELx must be ignored when returning from AArch64 to AArch32. Change-Id: I412d72908997916404e16e9eeca2789a9c529e58 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8881 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-12mem-ruby: Fix RubyPrefetcher support in MESI_Two_LevelRico Amslinger
Only a small quantity of prefetches were issued, as the positive feedback mechanism was not implemented. This commit adds a new action po_observeHit, which notifies the RubyPrefetcher of successful prefetches and resets the prefetch flag. When a cache line was replaced by a prefetch, the wrong queue could be stalled. This commit adds a new event PF_L1_Replacement, which stalls the correct queue. The behavior when receiving a prefetch or instruction fetch while in PF_IS_I (prefetch caused GETs, but got invalidated before the response was received) was undefined. This was changed to drop the prefetch request or change the state to non-prefetch, respectively. This behavior is analogous to IS_I (non-prefetch caused GETs, but got invalidated before the response was received) and the data case, respectively. In my local branch a major (20+%) performance increase can be observed in SPEC2006 gobmk and leslie3d when enabling the prefetcher. Some other benchmarks like bwaves, GemsFDTD, sphinx and wrf show smaller (~10%) performance increases. Unfortunately, the performance in most other SPEC benchmarks is still poor, most likely as the prefetcher does not detect strides fast/often enough. In order to push the change timely (most benchmarks have runtimes in the order of days on my machine even with the smallest parameters) after checkout, I have only run gobmk with the base repository + this commit. The results match those of my local branch. Change-Id: I9903a2fcd02060ea5e619b409f31f7d6fac47ae8 Reviewed-on: https://gem5-review.googlesource.com/8801 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Swapnil Haria <swapnilster@gmail.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-03-12arch-arm: Adding IPA-Based Invalidating instructionsGiacomo Travaglini
This patch introduces the TLB IPA-Based invalidating instructions in aarch32. In the entry selection policy the level of translation is not taken into account. This means that no difference stands between (e.g.) TLBIIPAS2 and TLBIPAS2L. Change-Id: Ieeb54665480874d2041056f356d86448c45043cb Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8822 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-12arch-arm: Implement missing aarch32 TLBI registersGiacomo Travaglini
In the pool of TLB Invalidate system register a category of instruction was missing: the ones operating on entries added to the TLB during the last level only of a table walk. (E.g. TLBIVMAL). This patch is not considering this matching criteria when invalidating the entries and it is rather performing the invalidation on all levels. Change-Id: I5f2186cfdd73793e76c90b260f7128be187903fe Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8821 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-09mem-cache: Use CacheBlk parameter on address regenerationDaniel R. Carvalho
Skewed caches need to know the way to regenerate a block address. Change-Id: I62c61ac9509eff2f37bad36862751956db7a6e40 Reviewed-on: https://gem5-review.googlesource.com/8782 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-08mem-cache: Fix missing overridesJason Lowe-Power
clang doesn't like inconsistent overrides. Add override to all overidden functions in lru.hh Change-Id: I100ff4a7d90757439afee879ff9838c15f5c0b1d Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/8861 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-08sparc: Passify a new g++ warning.Gabe Black
g++ seems to think there are some missing brackets when initializing the sparc fault information. Passify it by adding extra brackets. Change-Id: I826995f88b8ac8a21721c949a244dec480831b80 Reviewed-on: https://gem5-review.googlesource.com/8763 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com>
2018-03-08arch-arm: Enable Debug IFSC when faulting to aarch64 modeGiacomo Travaglini
Previous code was aborting simulation when a debug exception taken in aarch64 mode was encountered. This because an invalid (0xff) instruction fault status code was produced. Change-Id: I289f93f672be70cfbdc404be536809835160bdaf Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8363 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-08arch-arm: Fix FSC generation in AbortFaultGiacomo Travaglini
The fault status code generated by a Prefetch/Data Fault was containing a wrong value when the fault was triggered in aarch32 but handled in aarch64. This because the encoding differs between the two ISAs and the encoder was just checking the starting ISA rather than the the ending one. In this case the getFsr must be called after we know which is the ending ISA, which happens only after ArmFault::invoke gets called. The fsc update hence happens before writing into the Syndrome register. Change-Id: I725f12b6dcc0178f608233bd3d15e466d1cd1ffc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8362 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-08arch-arm: Introduce update method in ArmFault classGiacomo Travaglini
There is a set of internal variables in ArmFault thats get updated once the fault is invoked (ArmFault::invoke). Sometimes we rely on those even if the fault is generated but not invoked (e.g. when checking if a memory access is producing a fault). This patch is moving the update functionalities inside a public method so that a client can make use of it even when not invoking the fault. Change-Id: I3ac5b6835023f28ec569fe25487dffa356e1b2fd Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8361 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-08arch-arm: Fix PCAlignmentFault routing to HypervisorGiacomo Travaglini
This patch enables PCAlignmentFault routing to Hypervisor in case HCR_EL2.TGE == 1, as is happening for other arm exceptions. Change-Id: I48364ef1a0bcb5d030135221ae4bc6429e32759e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8841 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-07mem-cache: Make the block invalidate functions virtualNikos Nikoleris
This change makes the cache block invalidation function in the BaseTags and CacheBlk class virtual to enable derived classes. Change-Id: I2e64b01c6ca637f16d10474fc8b08eeec3f23453 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8287 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2018-03-07mem-cache: Make invalidate a common function between tag classesNikos Nikoleris
invalidate was defined as a separate function in the base associative and fully-associative tags classes although both functions should implement identical functionality. This patch moves the invalidate function in the base tags class. Change-Id: I206ee969b00ab9e05873c6d87531474fcd712907 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8286 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-07mem-cache: Allow prefetchers to override setCache.Xiaoyu Ma
This lets them hook setCache, perhaps to set up additional state based on the set cache. Change-Id: Ic3b34fa43d052c71e8ef733a57fe47c70899cd27 Reviewed-on: https://gem5-review.googlesource.com/8701 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-06scons: Switch from the print statement to the print function.Gabe Black
Starting with version 3, scons imposes using the print function instead of the print statement in code it processes. To get things building again, this change moves all python code within gem5 to use the function version. Another change by another author separately made this same change to the site_tools and site_init.py files. Change-Id: I2de7dc3b1be756baad6f60574c47c8b7e80ea3b0 Reviewed-on: https://gem5-review.googlesource.com/8761 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-06dev: Don't fall through into BRAR after RFDR caseSiddhesh Poyarekar
If the switch block inside the RFDR case selects the non-default case and breaks out, it will fall through into the BRAR case, which seems incorrect. Put in a break to ensure that it breaks out of the parent switch block as well. Change-Id: Ie4cedf66954b7e8f4b884ad9e3a653968bbfaef7 Signed-off-by: Siddhesh Poyarekar <siddhesh.poyarekar@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/8563 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-06arm: Remove ignored const qualifierSiddhesh Poyarekar
gcc8 warns about ignored const qualifiers (-Wignored-qualifiers) and that breaks builds. It was suggested that the warning be moved to Wextra[1] but that's probably not going to happen anytime soon. [1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82711 Change-Id: Ib808906deb9a1c2dccb1c34b6563db0c24c66655 Signed-off-by: Siddhesh Poyarekar <siddhesh.poyarekar@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/8562 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-06dev: Leave last byte in strncpy for NULLSiddhesh Poyarekar
The length of the strncpy should be one less than the destination to ensure that there is space for the last NULL byte in case the source is longer than the destination. Change-Id: Iea65fa6327c8242bd8ddf4bf9a5a2b5164996495 Signed-off-by: Siddhesh Poyarekar <siddhesh.poyarekar@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/8561 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-06mem-cache: Fix bug generated by 8282Daniel R. Carvalho
Merge 1ae7fced4d32898531a6875a339ef00e43e20e66 generated a bug in tagsInUse calculation. Change-Id: I079e327a0a26a7968f2ed8e433dd6e790c80998b Reviewed-on: https://gem5-review.googlesource.com/8781 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-06mem-cache: Populate whenReady for blocks filled from writebacksNikos Nikoleris
Writebacks write data to either an existing block or a newly allocated block. In either case we need to populate the whenReady field of the block which will determine when the new value can be used. Change-Id: I5788fad0b8086a1be96714639bf6a9470b334926 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8285 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-06mem-cache: Use findBlock() in accessBlock()Daniel R. Carvalho
Use placement policy specific block search within generic access. Change-Id: I6070035e6e00595bcf073d4011f78a55ba7e7a8a Reviewed-on: https://gem5-review.googlesource.com/8721 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-05mem-cache: Remove redundant block initialization on allocationNikos Nikoleris
Change-Id: I7496e12e6a517529316c480d5f6e2ade601f0e2d Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8282 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-02mem-cache: Remove mumBlock redundant initialiation from FALRUNikos Nikoleris
Change-Id: Id3afec0a62446d6d0f44ccb655032343037637e0 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8281 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-02mem-cache: Populate the secure bit when the temp block is filledNikos Nikoleris
The secure bit should be set when we fill a block with data from a secure location, as indicated by the packet that triggers the fill. This patch fixes a bug in which the cache wouldn't populate the secure bit when filling the temp block. Change-Id: I95c706146449804ff42b205b25dd79750f3e882a Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8284 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2018-03-02mem-cache: Remove unnecessary block initialization on writebackNikos Nikoleris
Change-Id: Ia9b825bcbb8d326705f74c15a93a88703153ba5a Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8283 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2018-03-01mem-cache: Remove extra block init in BaseSetAssocDaniel R. Carvalho
Removed extra initialization of cache block just after they have been created and organized the comments. Change-Id: I75c1beaf0489e3e530fd8cbff2739dc7593e3e6f Reviewed-on: https://gem5-review.googlesource.com/8661 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-01mem-cache: Vectorize C arrays in BaseSetAssoc.Daniel R. Carvalho
Transform BaseSetAssoc's arrays into C++ vectors to avoid unnecessary resource management. Change-Id: I656f42f29e5f9589eba491b410ca1df5a64f2f34 Reviewed-on: https://gem5-review.googlesource.com/8621 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-02-28sim, power: Temperature used for power calculationsAnouk Van Laer
The temperature used for the power calculations was fixed at 0 degrees, unless a thermal model was setup. This commit allows the user to set the temperature that needs to be used by the power calculation during gem5 configuration. This value will be overwritten if there are thermal models present. Change-Id: I7ca8fa6766bdcba9d362c12fc75d1e1f74385f35 Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8602 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-28sim: Added model type to power modelAnouk Van Laer
Static, dynamic or all to differentiate between types of power models so for example static models will not be asked for a dynamic power Change-Id: I3a0385821f7c671aedddaebeb038c677367faa81 Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8601 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-24mem-cache: Fix CacheSet memory leakDaniel R. Carvalho
CacheSet blocks were being allocated but never freed. Used vector to avoid using pure C array. Change-Id: I6f32fa5a305ff4e1d7602535026c1396764102ed Reviewed-on: https://gem5-review.googlesource.com/8603 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-02-24sparc: Fix FS Checkpoint loadingKhalique
Proposed changes to SPARC FS simulation, testing indicates that checkpoints are now loaded correctly with the following command: build/SPARC/gem5.opt configs/example/fs.py -r 1 Change-Id: Icd44f01a74c41a78828ef6fd7b661e584bdb6966 Reviewed-on: https://gem5-review.googlesource.com/8581 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-02-20arch-arm: Make hlt64 a mem barrier with semihostingGiacomo Travaglini
The HLT instruction is used to trap into semihosting. The semihosting code can change the contents of memory behind the back of the CPU, which requires instructions triggering semihosting to be non-speculative and memory barriers. Change-Id: I735166251aa194120ad49c08082d4ac65fe96524 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8373 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-20arch-arm: Add AArch32 HLT Semihosting interfaceGiacomo Travaglini
AArch32 HLT instruction is now able to issue Arm Semihosting commands as the AArch64 counterpart in either Arm and Thumb mode. Change-Id: I77da73d2e6a9288c704a5f646f4447022517ceb6 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8372 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-20arch-arm: Add AArch32 SVC Semihosting interfaceGiacomo Travaglini
AArch32 Svc instruction is now able to issue Arm Semihosting commands as the AArch64 counterpart in either Arm and Thumb mode. Change-Id: Ibe47ac23d0c26f3f819cc0e2b3ee874b5cdbb3d3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8371 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-20arch-arm: Adding isa templates for semihosting opsGiacomo Travaglini
A new class of Semihosting constructor templates has been added. Their main purpose is to check if the Exception Generation Instructions (HLT, SVC) are actually a semihosting command. If that is the case, the IsMemBarrier flag is raised, so that in the O3 model we perform a coherent memory access during the semihosting operation. Change-Id: Ib87fdeb70ee7a930659563230a80cce0e1372c32 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8370 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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