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AgeCommit message (Expand)Author
2015-03-19arm: Add a GICv2m deviceMatt Evans
2015-03-19arm: Remove the 'magic MSI register' in the GIC (PL390)Matt Evans
2015-03-19cpu: Fix TrafficGen message formatWendy Elsasser
2015-03-19mem: Use emplace front/back for deferred packetsAndreas Hansson
2015-03-19mem: Enable CommMonitor to output traces in atomic modeGeoffrey Blake
2015-02-11mem: remove redundant test in in Cache::recvTimingResp()Steve Reinhardt
2015-02-11mem: add local var in Cache::recvTimingResp()Steve Reinhardt
2015-02-11mem: restructure Packet cmd initialization a bit moreSteve Reinhardt
2015-03-14mem: clean up write buffer check in Cache::handleSnoop()Steve Reinhardt
2015-03-09cpu: o3: another assert instead of checkNilay Vaish
2015-03-09cpu: o3: Remove unused code in iew, add assert instead.Nilay Vaish
2015-03-09cpu: o3: commit: mark pipeline delay variable as constsNilay Vaish
2015-03-09cpu: o3: remove unused stat variables.Nilay Vaish
2015-03-09cpu: o3: combine if with same conditionNilay Vaish
2015-03-09cpu: o3: remove member variable squashCounterNilay Vaish
2015-03-09cpu: o3: remove unused function annotateMemoryUnits()Nilay Vaish
2015-03-02mem: Unify all cache DPRINTF address formattingAndreas Hansson
2015-03-02mem: Fix cache MSHR conflict determinationAndreas Hansson
2015-03-02mem: Add byte mask to Packet::checkFunctionalAndreas Hansson
2015-03-02mem: Add option to force in-order insertion in PacketQueueStephan Diestelhorst
2015-03-02mem: Downstream components consumes new crossbar delaysMarco Balboni
2015-03-02mem: Move crossbar default latencies to subclassesAndreas Hansson
2015-03-02mem: Add crossbar latenciesMarco Balboni
2015-03-02dev, arm: Clean up PL011 and rewrite interrupt handlingAndreas Sandberg
2015-03-02arm: Share a port for the two table walker objectsAndreas Hansson
2015-03-02arm: Remove unnecessary dependencies between AArch64 FP instructionsGiacomo Gabrielli
2015-03-02cpu: o3 register renaming request handling improvedRekai
2015-03-02mem: Tidy up the cache debug messagesAndreas Hansson
2015-03-02mem: Split port retry for all different packet classesAndreas Hansson
2015-03-02mem: Fix prefetchSquash + memInhibitAsserted bugAli Jafri
2015-03-02cpu: Add a PC-value to the traffic generator requestsStephan Diestelhorst
2015-03-02arm: Don't truncate 16-bit ASIDs to 8 bitsAndreas Sandberg
2015-03-02arm: Correctly access the stack pointer in GDBAndreas Sandberg
2015-03-02arm: Fix broken page table permissions checks in remote GDBAndreas Sandberg
2015-02-26Ruby: Update backing store option to propagate through to all RubyPortsJason Power
2015-02-16cpu: TrafficGen sinks snoops without complainingAndreas Hansson
2015-02-16mem: Fix initial value problem with MemCheckerStephan Diestelhorst
2015-02-16dev: Fix undefined behaviuor in i8254xGBeAndreas Hansson
2015-02-16arm: Wire up the GIC with the platform in the base classAndreas Sandberg
2015-02-16mem: mmap the backing store with MAP_NORESERVEAndreas Hansson
2015-02-16mem: Use the range cache for lookup as well as accessAndreas Hansson
2015-02-16arch: Make readMiscRegNoEffect const throughoutAndreas Hansson
2015-02-16arm: Merge ISA files with pseudo instructionsAndreas Sandberg
2015-02-16cpu: add support for outputing a protobuf formatted CPU traceAli Saidi
2015-02-11mem: Clarification of packet crossbar timingsMarco Balboni
2015-02-11mem: Clarify usage of latency in the cacheMarco Balboni
2015-02-11cpu: Tidy up the MemTest and make false sharing more obviousAndreas Hansson
2015-02-11sim: Move the BaseTLB to src/arch/generic/Andreas Sandberg
2015-02-11base: Add compiler macros to add deprecation warningsAndreas Sandberg
2015-02-11base: Do not dereference NULL in CompoundFlag creationAndreas Hansson
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