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AgeCommit message (Expand)Author
2014-04-09kvm, x86: Add initial support for multicore simulationAndreas Sandberg
2014-04-09dev: Protect PollEvent processing when running in parallel modeAndreas Sandberg
2014-04-08ruby: slicc: change enqueue statementNilay Vaish
2014-04-08ruby: coherence protocols: drop the phrase IntraChipNilay Vaish
2014-04-03sim: Add the ability to lock and migrate between event queuesAndreas Sandberg
2014-03-25cpu: o3: lsq: Fix TSO implementationMarco Elver
2014-03-23mem: Track DRAM read/write switching and add hysteresisAndreas Hansson
2014-03-23mem: Rename SimpleDRAM to a more suitable DRAMCtrlAndreas Hansson
2014-03-23mem: Change memory defaults to be more representativeAndreas Hansson
2014-03-23mem: Add close adaptive paging policy to DRAM controller modelWendy Elsasser
2014-03-23mem: DRAM controller tidying upAndreas Hansson
2014-03-23mem: Fix bug in DRAM bytes per activateAndreas Hansson
2014-03-23mem: Limit the accesses to a page before forcing a prechargeAndreas Hansson
2014-03-23mem: Make DRAM write queue draining more aggressiveAndreas Hansson
2014-03-23cpu: DRAM Traffic GeneratorNeha Agarwal
2014-03-23mem: DDR3 config for comparing with DRAMSim2Neha Agarwal
2014-03-23mem: More descriptive address-mapping scheme namesAndreas Hansson
2014-03-23misc: Fix -q (quiet) flagStan Czerniawski
2014-03-23ruby: Move Ruby debug flags to ruby dir and remove stale optionsAndreas Hansson
2014-03-23mem: Include the DRAMSim2 wrapper in NULL buildAndreas Hansson
2014-03-23mem: CommMonitor trace warn on non-timing modeSascha Bischoff
2014-03-23cpu: Add basic check to TrafficGen initial stateStan Czerniawski
2014-03-23dev: Fix IsaFake's cxx_header settingAndrew Bardsley
2014-03-23arm: m5ops readfile64 args broken, offset coming through garbageEric Van Hensbergen
2014-03-23base: Fix error message time unit (cycle -> tick)Andreas Hansson
2014-03-20ruby: consumer: avoid accessing wakeup times when waking upNilay Vaish
2014-03-20ruby: garnet: convert network interfaces into clocked objectsNilay Vaish
2014-03-20ruby: slicc: code refactorNilay Vaish
2014-03-20ruby: no piobus in se modeNilay Vaish
2014-03-17ruby: remove some of the unnecessary codeNilay Vaish
2014-03-16kvm: Clean up signal handlingAndreas Sandberg
2014-03-16kvm: x86: Adjust PC to remove the CS segment base addressAndreas Sandberg
2014-03-16kvm: x86: Add support for x86 INIT and STARTUP handlingAndreas Sandberg
2014-03-12alpha: Small removal of dead comments/code from alpha ISAPaul Rosenfeld
2014-03-07cpu: Make CPU and ThreadContext getters constAndreas Hansson
2014-03-07arm: Handle functional TLB walks properlyGeoffrey Blake
2014-03-07mem: Fix incorrect assert failure in the CachePrakash Ramrakhyani
2014-03-07mem: Edit proto Packet and enhance the python scriptRadhika Jagtap
2014-03-07misc: Add panic_if / fatal_if / chatty_assertStephan Diestelhorst
2014-03-07scons: Fixes uninitialized warnings issued by clangMitch Hayenga
2014-03-07arm: Fix uninitialised warning with gcc 4.8Stephan Diestelhorst
2014-03-07mem: Wakeup sleeping CPUs without caches on LLSCAli Saidi
2014-03-06sim: Schedule the global sync event at curTick() + simQuantumAndreas Sandberg
2014-03-03x86: Setup correct TSL/TR segment attributes on INITAndreas Sandberg
2014-03-03kvm: x86: Always assume segments to be usableAndreas Sandberg
2014-03-03kvm: Initialize signal handlers from startupThread()Andreas Sandberg
2014-03-01ruby: message buffer: changes related to tracking push/pop timesNilay Vaish
2014-03-01ruby: make the max_size variable of the MessageBuffer unsignedNilay Vaish
2014-03-01cpu: Enable fast-forwarding for MIPS InOrderCPU and O3CPUChristopher Torng
2014-03-01ruby: profiler: statically allocate stats variableNilay Vaish