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2010-02-23cache: Make caches sharing aware and add occupancy stats.Lisa Hsu
On the config end, if a shared L2 is created for the system, it is parameterized to have n sharers as defined by option.num_cpus. In addition to making the cache sharing aware so that discriminating tag policies can make use of context_ids to make decisions, I added an occupancy AverageStat and an occ % stat to each cache so that you could know which contexts are occupying how much cache on average, both in terms of blocks and percentage. Note that since devices have context_id -1, having an array of occ stats that correspond to each context_id will break here, so in FS mode I add an extra bucket for device blocks. This bucket is explicitly not added in SE mode in order to not only avoid ugliness in the stats.txt file, but to avoid broken stats (some formulas break when a bucket is 0).
2010-02-23stats: this makes some fixes to AverageStat and AverageVector.Lisa Hsu
Also, make Formulas work on AverageVector. First, Stat::Average (and thus Stats::AverageVector) was broken when coming out of a checkpoint and on resets, this fixes that. Formulas also didn't work with AverageVector, but added support for that.
2010-02-23cache: pull CacheSet out of LRU so that other tags can use associative sets.Lisa Hsu
2010-02-20BaseDynInst: Preserve the faults returned from read and write.Timothy M. Jones
When implementing timing address translations instead of atomic, I forgot to preserve the faults that are returned from the read and write calls. This patch reinstates them.
2010-02-12O3PCU: Split loads and stores that cross cache line boundaries.Timothy M. Jones
When each load or store is sent to the LSQ, we check whether it will cross a cache line boundary and, if so, split it in two. This creates two TLB translations and two memory requests. Care has to be taken if the first packet of a split load is sent but the second blocks the cache. Similarly, for a store, if the first packet cannot be sent, we must store the second one somewhere to retry later. This modifies the LSQSenderState class to record both packets in a split load or store. Finally, a new const variable, HasUnalignedMemAcc, is added to each ISA to indicate whether unaligned memory accesses are allowed. This is used throughout the changed code so that compiler can optimise away code dealing with split requests for ISAs that don't need them.
2010-02-12BaseDynInst: Make the TLB translation timing instead of atomic.Timothy M. Jones
This initiates a timing translation and passes the read or write on to the processor before waiting for it to finish. Once the translation is finished, the instruction's state is updated via the 'finish' function. A new DataTranslation class is created to handle this. The idea is taken from the implementation of timing translations in TimingSimpleCPU by Gabe Black. This patch also separates out the timing translations from this CPU and uses the new DataTranslation class.
2010-02-12Power ISA: Add an alignment fault to Power ISA and check alignment in TLB.Timothy M. Jones
2010-02-10ruby: fixed data block assignment fixBrad Beckmann
Fixed data block assignment to not delete if not internally allocated.
2010-02-10ruby: Initialize sender in MI_example-dirBrad Beckmann
2010-02-10ruby: Fixed slicc to initialize the m_is_blocking flagBrad Beckmann
2010-02-01ruby: Added FS support to the simple mesh topologyBrad Beckmann
Added full-system support to the simple mesh toplogy by allowing dma contrllers to be attached to router zero in the network.
2010-02-01ruby: Set default protocol back to MI_exampleBrad Beckmann
2010-01-31inorder: double delete inst bugKorey Sewell
Make sure that instructions are dereferenced/deleted twice by marking they are on the remove list
2010-01-31inorder: inst count mgmtKorey Sewell
2010-01-31inorder: implement split storesKorey Sewell
2010-01-31inorder: implement split loadsKorey Sewell
2010-01-31inorder: add activity statsKorey Sewell
2010-01-31inorder: object cleanup in destructorsKorey Sewell
2010-01-31inorder: user per-thread dummy insts/reqsKorey Sewell
2010-01-31inorder: add execution unit statsKorey Sewell
2010-01-31inorder: recvRetry bug fixKorey Sewell
- on certain retry requests you can get an assertion failure - fix by allowing the request to literally "Retry" itself if it wasnt successful before, and then block any requests through cache port while waiting for the cache to be made available for access
2010-01-31inorder-stats: add prereq to basic statKorey Sewell
only show requests processed when the resource is actually in use
2010-01-31inorder: ctxt switch statsKorey Sewell
- m5 line enforcement on use_def.cc,hh
2010-01-31inorder: pipeline stage statsKorey Sewell
add idle/run/utilization stats for each pipeline stage
2010-01-31inorder: enforce stage bandwidthKorey Sewell
each stage keeps track of insts_processed on a per_thread basis but we should be keeping that on a total basis inorder to enforce stage width limits
2010-01-31inorder: set thread status'Korey Sewell
set Active/Suspended/Halted status for threads. useful for system when determining if/when to exit simulation
2010-01-31inorder: add/remove halt/deallocate context respectivelyKorey Sewell
Halt is called from the exit() system call while deallocate is unused. So to clear up things, just use halt and remove deallocate.
2010-01-31inorder: track last branch committedKorey Sewell
when threads are switching in/out the CPU, we need to keep track of special cases like branches. Add appropriate variables in ThreadState t track this and then use these variables when updating pc after context switch
2010-01-31inorder: add updatePC event to resPoolKorey Sewell
this will be used for when a thread comes back from a cache miss, it needs to update the PCs because the inst might of been a branch or delayslot in which the next PC isnt always a straight addition
2010-01-31inorder: ready thread wakeupKorey Sewell
allow a thread to wakeup and be activated after it has been in suspended state and another thread is switched out. Need to give pipeline stages a "activateThread" function so that can get to their suspended instruction when the time is right.
2010-01-31inorder: add threadmodel flagKorey Sewell
this prints out messages relative to what threading model is being used (smt, switch-on-miss, single, etc.)
2010-01-31inorder: mem. mgmt. updateKorey Sewell
update address List and address Map to take into account multiple threads
2010-01-31inorder: suspend in respoolKorey Sewell
give resources their own specific activity to do for a "suspend" event instead of defaulting to deactivating the thread for a suspend thread event. This really matters for the fetch sequence unit which wants to remove the thread from fetching while other units want to ignore a thread suspension. If you deactivate a thread in a resource then you may lose some of the allotted bandwidth that the thread is taking up...
2010-01-31inorder: fetch thread bugKorey Sewell
dont check total # of threads but instead all active threads
2010-01-31inorder: ready/suspend status fnsKorey Sewell
update/add in the use of isThreadReady & isThreadSuspended functions.Check in activateThread what list a thread is on so it can be managed accordingly.
2010-01-31inorder-cleanup: remove unused thread functionsKorey Sewell
2010-01-31inorder: activate thread on cache missKorey Sewell
-Support ability to activate next ready thread after a cache miss through the activateNextReadyContext/Thread() functions -To support this a "readyList" of thread ids is added -After a cache miss, thread will suspend and then call activitynextreadythread
2010-01-31inorder: add event priority offsetKorey Sewell
allow for events to schedule themselves later if desired. this is important because of cases like where you need to activate a thread only after the previous thread has been deactivated. The ordering there has to be enforced
2010-01-31inorder: squash on memory stallKorey Sewell
add code to recognize memory stalls in resources and the pipeline as well as squash a thread if there is a stall and we are in the switch on cache miss model
2010-01-31inorder: add insts to cpu eventKorey Sewell
some events are going to need instruction data when they process, so just include the instruction in the event construction
2010-01-31inorder: switch out bufferKorey Sewell
add buffer for instructions to switch out to in a pipeline stage can't squash the instruction and remove the pipeline so we kind of need to 'suspend' an instruction at the stage while the memory stall resolves for the switch on cache miss model
2010-01-31inorder: dont allow early loadsKorey Sewell
- loads were happening on same cycle as the address was generated which is slightly unrealistic. Instead, force address generation to be on separate cycle from load initiation - also, mark the stages in a more traditional way (F-D-X-M-W)
2010-01-31configs/inorder: add options for switch-on-miss to inorder cpuKorey Sewell
2010-01-31inorder: init internal debug cpu countersKorey Sewell
- cpuEventNum - resReqCount
2010-01-29m5: Regression Tester UpdateBrad Beckmann
This patch includes the necessary regression updates to test the new ruby configuration system. The patch includes support for multiple ruby protocols and adds the ruby random tester. The patch removes atomic mode test for ruby since ruby does not support atomic mode acceses. These tests can be added back in when ruby supports atomic mode for real. --HG-- rename : tests/quick/50.memtest/test.py => tests/quick/60.rubytest/test.py
2010-01-29ruby: Replaced gems_common debug statementsBrad Beckmann
Replaced Ruby debug statements with M5 statements.
2010-01-29ruby: removed last level cache supportBrad Beckmann
Removed the last level cache support and MOESI_hammer's dependency on it. Replaces the LLC support with the more generic MachineType count.
2010-01-29ruby: Added a Scons option to prevent HTML file creationBrad Beckmann
2010-01-29ruby: Removed static members in RubyPort including hitcallbackBrad Beckmann
Removed static members in RubyPort and removed the ruby request unique id.
2010-01-29ruby: Removed the old config interfaceBrad Beckmann
Removed the old config interface from RubySystem and libruby.
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