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AgeCommit message (Expand)Author
2018-01-29arm: DT autogeneration - Generate cpus nodeGlenn Bergmans
2018-01-29arm: DT autogeneration - Device Tree generation methodsGlenn Bergmans
2018-01-29ext: DT autogeneration - Add PyFtd to m5 spaceGlenn Bergmans
2018-01-29arm: make Arm GenericTimer a ClockedObjectCurtis Dunham
2018-01-27base: Add an "override" to name() in the HardBreakpoint class.Gabe Black
2018-01-27base: Get bitunions to compile on clang 3.8.Gabe Black
2018-01-23arch-x86: Adding clflush, clflushopt, clwb instructionsSwapnil Haria
2018-01-23arch: Remove the "arch/tlb.hh" switching header.Gabe Black
2018-01-23tarch, mem: Abstract the data stored in the SE page tables.Gabe Black
2018-01-23x86, mem: Rewrite the multilevel page table class.Gabe Black
2018-01-20x86, mem: Don't try to force physical addresses on the system.Gabe Black
2018-01-20x86, mem: Get rid of PageTableOps::getBasePtr.Gabe Black
2018-01-20x86, mem: Pass the multi level page table layout in as a parameter.Gabe Black
2018-01-20arch, mem: Make the page table lookup function return a pointer.Gabe Black
2018-01-20base: Hide the BitUnion::__StorageType type.Gabe Black
2018-01-20arm, base: Generalize and move the BitUnion hash struct.Gabe Black
2018-01-20sim: Use the new BitUnion templates in serialize.hh.Gabe Black
2018-01-20base: Enable specializing templates on BitUnion types.Gabe Black
2018-01-20base: Rework bitunions so they can be more flexible.Gabe Black
2018-01-20sim, arch, base: Refactor the base remote GDB class.Gabe Black
2018-01-19arch, mem, sim: Consolidate and rename the SE mode page table classes.Gabe Black
2018-01-17mem: Change the multilevel page table to inherit from FuncPageTable.Gabe Black
2018-01-16arch-riscv: Fix floating-poing op classesAlec Roelke
2018-01-16arch-riscv: Fix floating-point conversion bugsAlec Roelke
2018-01-16sim: Simplify registerThreadContext a little bit.Gabe Black
2018-01-15mem: Track TLB entries in the lookup cache as pointers.Gabe Black
2018-01-15arch: Fix a fatal_if in most of the arch's process classes.Gabe Black
2018-01-12sim: Allow passing a user-defined L2XBar to addTwoLevelCacheHierarchy().Xiaoyu Ma
2018-01-11arch-riscv: Don't crash when printing unknown CSRsAlec Roelke
2018-01-11mem-ruby: Fix wakeup timeouts for the MOESI_CMP_token protocolNikos Nikoleris
2018-01-11mem-ruby: Remove function that maps responses to a DMA engineNikos Nikoleris
2018-01-11mem-ruby: Add support for multiple DMA engines in MESI_Two_LevelNikos Nikoleris
2018-01-11cpu: Make the CPU's TLB parameter a BaseTLB.Gabe Black
2018-01-11arm, power: Make the python TLB simobjects inherit from BaseTLB.Gabe Black
2018-01-11arch,mem: Remove the default value for page size.Gabe Black
2018-01-11arch,mem: Move page table construction into the arch classes.Gabe Black
2018-01-10style: change C/C++ source permissions to noexecBKP
2018-01-10arch-riscv: Make use of ImmOp's polymorphismAlec Roelke
2018-01-10alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT.Gabe Black
2018-01-10arch-riscv,sim: Support clone syscall in RISC-VTuan Ta
2018-01-09mem-cache: Prune unnecessary writebacks in exclusive cachesNikos Nikoleris
2018-01-09cpu: Use the NotAnInst flag to avoid passing an inst to fetch faults.Gabe Black
2018-01-09cpu: Add a NotAnInst flag to the BaseDynInst class.Gabe Black
2018-01-09cpu, power: Get rid of the remnants of the EA computation insts.Gabe Black
2018-01-09arm: Make translateFunctional override the base implementation.Gabe Black
2018-01-05arch-riscv: Ignore sched_yield syscall in SE modeTuan Ta
2018-01-05sim: Fix a bug in prlimit syscall in SE modeTuan Ta
2018-01-05arch-riscv: Ignore set_robust_list and get_robust_list syscallsTuan Ta
2018-01-05arch-riscv: Add an implementation of set_tid_address syscall in RISCVTuan Ta
2018-01-05arch-riscv: Correct syscall argument reg countAlec Roelke