summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Expand)Author
2019-11-26sim: prefix --debug-flags Event logs with the flag nameCiro Santilli
2019-11-26cpu: prefix ExecEnable to the native trace to match DPRINTFCiro Santilli
2019-11-26base: generalize ExecTicks to all messages with FmtTicksOffCiro Santilli
2019-11-26base: create DPRINTF_UNCONDITIONALCiro Santilli
2019-11-26base: add the --debug-flag to DPRINTF output with FmtFlagCiro Santilli
2019-11-26arch-arm: Make the Tarmac parsed registers case insensitiveGiacomo Travaglini
2019-11-26arch-riscv: Fix immediate decoding for integer shift immediate instructionsIan Jiang
2019-11-26arch-riscv: Fix disassembling for fence and fence.iIan Jiang
2019-11-26arch,cpu: Get rid of ISA_HAS_CC_REGS and its associated ifdefs.Gabe Black
2019-11-25arm: Stop serializing ISA values wihch are cached from the system.Gabe Black
2019-11-25arch-arm: default MIDR for Armv8 ISA processorsAdrian Herrera
2019-11-25dev-arm: Adjust off_chip ranges in VExpress_GEM5 platformGiacomo Travaglini
2019-11-25cpu: log thread activate and suspend with --debug-flags ThreadCiro Santilli
2019-11-25sim-se: don't wake up threads that are halted on futexCiro Santilli
2019-11-25arch-riscv: Fix disassembling for atomic instructionsIan Jiang
2019-11-25arch-riscv: Fix disassembling of operand list for compressed instructionsIan Jiang
2019-11-25arch-riscv: Fix disassembling of immediate for U-type instructionsIan Jiang
2019-11-22arch-riscv: Fix bug in serialize and unserialize of InterrutpsIanJiangICT
2019-11-21scons: Use the new error() and warning() methods.Gabe Black
2019-11-21scons: Use HAVE_PROTOC when building protobuf files.Gabe Black
2019-11-21tests,base: Added GTests for exec_ecoff.h and exec_aout.hBobby R. Bruce
2019-11-21test,base: Added GTest for base/loader/image_file_data.ccBobby R. Bruce
2019-11-21base: Remove tests making use of Big/LittleEndianOrder NamespaceGiacomo Travaglini
2019-11-20base,tests: Expanded GTests for addr_range.hhBrandon Potter
2019-11-20tests, base: Added GTests for base/intmath.ccBobby R. Bruce
2019-11-20tests, base: Removed dead code from base/intmathMahyar Samani
2019-11-18arch: Get rid of the (Big|Little)EndianGuest namespaces.Gabe Black
2019-11-18arch: Make and use endian specific versions of the mem helpers.Gabe Black
2019-11-18arch-arm: R/W interface to AArch32 HCR2 misc regAdrian Herrera
2019-11-18mem-cache: Initialize all members of `QueuedPrefetcher::DeferredPacket`.Isaac Sánchez Barrera
2019-11-18mem-cache: Fix destructor of `BasePrefetcher::PrefetchInfo`.Isaac Sánchez Barrera
2019-11-18arch-arm: Fix short descriptors cacheability during table walksGiacomo Travaglini
2019-11-18arch-arm: Fix long descriptors cacheability during table walksGiacomo Travaglini
2019-11-16tests: Added GTests for byteswap.hhBobby R. Bruce
2019-11-14tests, base: Removed ambiguity from base/intmath.hhMahyar Samani
2019-11-14arch-arm: Refactor code to check if gic is GicV2Chun-Chen TK Hsu
2019-11-14config: Add fastmodel cluster in fs_bigLITTLE.pyChun-Chen TK Hsu
2019-11-14fastmodel: Add VExpressFastmodel platformChun-Chen TK Hsu
2019-11-13arm: Replace most htog and gtoh with htole and letoh.Gabe Black
2019-11-13arch-arm: fix routeToHyp for AArch64 in faultsAdrian Herrera
2019-11-13tests: Added GTests for base/chunk_generator.hhBobby R. Bruce
2019-11-13fastmodel: Implement reading vector registers with readVecReg.Gabe Black
2019-11-13tests: Added GTests for base/types.ccBobby R. Bruce
2019-11-12tests,base: Added GTests for base/condcodes.hhBobby R. Bruce
2019-11-11arch-arm: Fix TarmacParser handling of 64bit LD/STGiacomo Travaglini
2019-11-11arch-arm: Provide SVE support to the TarmacTracerGiacomo Travaglini
2019-11-11arch-arm: Provide SVE support to the TarmacParserGiacomo Gabrielli
2019-11-07arm: Set the number of FloatRegs to zero.Gabe Black
2019-11-07tests,base: Added GTests for base/match.ccBobby R. Bruce
2019-11-07cpu: Fix a bug in getCurrentInstCount in the checker CPU.Gabe Black
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-29 15:36:09 +0000