gem5 - gem5

Age	Commit message (Expand)	Author
2019-08-12	mem-ruby: Use check_on_cache_probe to protect locked lines from eviction	Pouya Fotouhi
2019-08-12	dev-arm: Enable DTB autogeneration in GICv3	Giacomo Travaglini
2019-08-12	dev-arm: Fix PCI node's interrupt-map property	Giacomo Travaglini
2019-08-12	dev-arm: Use FdtState to generate GIC properites	Giacomo Travaglini
2019-08-12	python: FdtState using interrupt-cells	Giacomo Travaglini
2019-08-12	arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic func	Jordi Vaquero
2019-08-12	sim-se: rename Process::setpgid member	Brandon Potter
2019-08-10	cpu: Pull more arch specialization to the top of BaseCPU.py.	Gabe Black
2019-08-10	x86: Move some fixed or dummy config information into X86LocalApic.py.	Gabe Black
2019-08-09	arch: Bump MaxVecRegLenInBytes to 4096	Tony Gutierrez
2019-08-09	sim-se: minor refactor for ProcessParams::create	Brandon Potter
2019-08-09	sim-se: remove unused parameter	Brandon Potter
2019-08-07	cpu-o3: fix atomic instructions non-speculative	Jordi Vaquero
2019-08-07	cpu-o3: added _amo_op parameter in o3 LSQ	Jordi Vaquero
2019-08-07	arch-arm: Add TypeAtomicOp class to be used by new atomic instructions	Jordi Vaquero
2019-08-07	arch-arm: adding register control flags enabling LSE implementation	Jordi Vaquero
2019-08-07	dev-arm: Perform SMMUv3 CFG Invalidation at device interface	Giacomo Travaglini
2019-08-07	mem-cache: Fix non-virtual base destructor of Repl Entry	Daniel R. Carvalho
2019-08-06	sim-se: add new getpgrp system call	Brandon Potter
2019-08-06	sim-se: adding pipe2 syscall	Matthew Sinclair
2019-08-05	arch-arm: Implement ARMv8.1-PAN, Privileged access never	Giacomo Travaglini
2019-08-05	arch-arm: Rewrite MSR immediate instruction class	Giacomo Travaglini
2019-08-05	systemc: Provide Port wrapper classes for sc_port	Chun-Chen TK Hsu
2019-08-02	mem-ruby: Remove assertion with incorrect assumption	Pouya Fotouhi
2019-08-02	sim-se: small refactor on pipe syscall	Brandon Potter
2019-08-02	mem: Move eraseIfNullEntry to when holder is updated	Daniel R. Carvalho
2019-08-02	mem: Encapsulate retry variables of SnoopFilter	Daniel R. Carvalho
2019-08-01	sim-se: small performance optimization	Brandon Potter
2019-08-01	sim-se: fstat64 bugfix	Brandon Potter
2019-08-01	sim-se: add new option to getrlimit syscall	Brandon Potter
2019-07-31	mem-cache: mark block as dirty when handling SW prefetch	Tiago Mück
2019-07-31	mem-cache: Fix set and way of sub-entries	Daniel R. Carvalho
2019-07-30	dev-arm: Rewrite SMMUv3 Commands	Giacomo Travaglini
2019-07-28	cpu: Fix the type of the effective mem request size	Gabor Dozsa
2019-07-28	cpu-o3: Fix too strict assert condition in writeback()	Gabor Dozsa
2019-07-27	arch-arm: Fix reg dependency for SVE gather microops	Gabor Dozsa
2019-07-27	arch-arm: Fix tracing code for SVE gather	Gabor Dozsa
2019-07-27	arch-arm: Add SVE LD1RQ[BHWD]	Javier Setoain
2019-07-27	arch-arm: Fix decoding for SVE memory instructions	Adrià Armejach
2019-07-27	arch-arm: Add support for SVE load/store structures	Javier Setoain
2019-07-27	cpu: Add first-/non-faulting load support to Minor and O3	Gabor Dozsa
2019-07-25	dev-arm: Fix SMMUv3 CMDQ wrapping	Giacomo Travaglini
2019-07-25	dev-arm: Polish SMMUv3 CMDQ setup	Giacomo Travaglini
2019-07-25	dev-arm: Define enum masks for SMMU_CR0 register	Giacomo Travaglini
2019-07-25	dev-arm: TnSZ fields need to be cached in SMMUv3::ConfigCache	Giacomo Travaglini
2019-07-25	dev-arm: SMMUv3 Table walks using TnSZ	Giacomo Travaglini
2019-07-25	dev-arm: Use override keyword for SMMUv3 PTOPS	Giacomo Travaglini
2019-07-25	dev-arm: Add 16K granule support to SMMUv3 model	Michiel Van Tol
2019-07-23	mem-ruby: Adding a new slicc statement - to not evict locked cachelines	Pouya Fotouhi
2019-07-22	arch-x86: Don't free PTW state with inflight requests	Matthew Poremba