From 0004a6a06073131d5785100b2d7b9b07ecee63af Mon Sep 17 00:00:00 2001
From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Tue, 3 Sep 2019 12:36:29 +0100
Subject: dev-arm: Writes to IGRPEN1_EL3 triggering update

Change-Id: I56804eb1bfc8913bd0d3cab05865a382bf270bc1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20634
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
---
 src/dev/arm/gic_v3_cpu_interface.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/dev/arm/gic_v3_cpu_interface.cc b/src/dev/arm/gic_v3_cpu_interface.cc
index 792337fe9..d7988e13d 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -1378,6 +1378,7 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val)
               MISCREG_ICC_IGRPEN1_EL1_S, icc_igrpen1_el3.EnableGrp1S);
           isa->setMiscRegNoEffect(
               MISCREG_ICC_IGRPEN1_EL1_NS, icc_igrpen1_el3.EnableGrp1NS);
+          updateDistributor();
           return;
       }
 
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