From 0e6dc004978fbf2963dc467b8330544f563231d0 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 14 Aug 2011 17:41:34 -0700
Subject: O3: When squashing, restore the macroop that should be used for
 fetching.

---
 src/cpu/o3/comm.hh        |  1 +
 src/cpu/o3/decode_impl.hh |  1 +
 src/cpu/o3/fetch.hh       | 10 ++++++----
 src/cpu/o3/fetch_impl.hh  | 18 ++++++++++++------
 4 files changed, 20 insertions(+), 10 deletions(-)

diff --git a/src/cpu/o3/comm.hh b/src/cpu/o3/comm.hh
index 840dde9ea..053d4f6be 100644
--- a/src/cpu/o3/comm.hh
+++ b/src/cpu/o3/comm.hh
@@ -135,6 +135,7 @@ struct TimeBufStruct {
         bool branchTaken;
         Addr mispredPC;
         TheISA::PCState nextPC;
+        DynInstPtr squashInst;
         unsigned branchCount;
     };
 
diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
index 67d32f0fe..0c0ec768e 100644
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -280,6 +280,7 @@ DefaultDecode<Impl>::squash(DynInstPtr &inst, ThreadID tid)
     toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
     toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
     toFetch->decodeInfo[tid].branchTaken = inst->pcState().branching();
+    toFetch->decodeInfo[tid].squashInst = inst;
 
     InstSeqNum squash_seq_num = inst->seqNum;
 
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 7b9be7b67..6d93f2cc8 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -332,13 +332,15 @@ class DefaultFetch
     }
 
     /** Squashes a specific thread and resets the PC. */
-    inline void doSquash(const TheISA::PCState &newPC, ThreadID tid);
+    inline void doSquash(const TheISA::PCState &newPC,
+                         const DynInstPtr squashInst, ThreadID tid);
 
     /** Squashes a specific thread and resets the PC. Also tells the CPU to
      * remove any instructions between fetch and decode that should be sqaushed.
      */
     void squashFromDecode(const TheISA::PCState &newPC,
-                          const InstSeqNum &seq_num, ThreadID tid);
+                          const DynInstPtr squashInst,
+                          const InstSeqNum seq_num, ThreadID tid);
 
     /** Checks if a thread is stalled. */
     bool checkStall(ThreadID tid) const;
@@ -352,8 +354,8 @@ class DefaultFetch
      * remove any instructions that are not in the ROB. The source of this
      * squash should be the commit stage.
      */
-    void squash(const TheISA::PCState &newPC, const InstSeqNum &seq_num,
-                DynInstPtr &squashInst, ThreadID tid);
+    void squash(const TheISA::PCState &newPC, const InstSeqNum seq_num,
+                DynInstPtr squashInst, ThreadID tid);
 
     /** Ticks the fetch stage, processing all inputs signals and fetching
      * as many instructions as possible.
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index c635a1b30..86f5df9c7 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -746,14 +746,18 @@ DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req)
 
 template <class Impl>
 inline void
-DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC, ThreadID tid)
+DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC,
+                             const DynInstPtr squashInst, ThreadID tid)
 {
     DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %s.\n",
             tid, newPC);
 
     pc[tid] = newPC;
     fetchOffset[tid] = 0;
-    macroop[tid] = NULL;
+    if (squashInst && squashInst->pcState().instAddr() == newPC.instAddr())
+        macroop[tid] = squashInst->macroop;
+    else
+        macroop[tid] = NULL;
     predecoder.reset();
 
     // Clear the icache miss if it's outstanding.
@@ -786,11 +790,12 @@ DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC, ThreadID tid)
 template<class Impl>
 void
 DefaultFetch<Impl>::squashFromDecode(const TheISA::PCState &newPC,
-                                     const InstSeqNum &seq_num, ThreadID tid)
+                                     const DynInstPtr squashInst,
+                                     const InstSeqNum seq_num, ThreadID tid)
 {
     DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n", tid);
 
-    doSquash(newPC, tid);
+    doSquash(newPC, squashInst, tid);
 
     // Tell the CPU to remove any instructions that are in flight between
     // fetch and decode.
@@ -866,12 +871,12 @@ DefaultFetch<Impl>::updateFetchStatus()
 template <class Impl>
 void
 DefaultFetch<Impl>::squash(const TheISA::PCState &newPC,
-                           const InstSeqNum &seq_num, DynInstPtr &squashInst,
+                           const InstSeqNum seq_num, DynInstPtr squashInst,
                            ThreadID tid)
 {
     DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid);
 
-    doSquash(newPC, tid);
+    doSquash(newPC, squashInst, tid);
 
     // Tell the CPU to remove any instructions that are not in the ROB.
     cpu->removeInstsNotInROB(tid);
@@ -1052,6 +1057,7 @@ DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid)
             DPRINTF(Fetch, "Squashing from decode with PC = %s\n", nextPC);
             // Squash unless we're already squashing
             squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
+                             fromDecode->decodeInfo[tid].squashInst,
                              fromDecode->decodeInfo[tid].doneSeqNum,
                              tid);
 
-- 
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