From 14edc6013d8d62782d58536214c669e12c64da37 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Sat, 14 Apr 2012 05:46:59 -0400 Subject: Ruby: Use MasterPort base-class pointers where possible This patch simplifies future patches by changing the pointer type used in a number of the Ruby testers to use MasterPort instead of using a derived CpuPort class. There is no reason for using the more specialised pointers, and there is no longer a need to do any casting. With the latest changes to the tester, organising ports as readers and writes, things got a bit more complicated, and the "type" now had to be removed to be able to fall back to using MasterPort rather than CpuPort. --- .../testers/directedtest/InvalidateGenerator.cc | 8 +++----- src/cpu/testers/directedtest/RubyDirectedTester.hh | 2 +- .../testers/directedtest/SeriesRequestGenerator.cc | 4 +--- src/cpu/testers/rubytest/Check.cc | 16 ++++++--------- src/cpu/testers/rubytest/RubyTester.cc | 14 ++++++++----- src/cpu/testers/rubytest/RubyTester.hh | 23 +++++++--------------- 6 files changed, 27 insertions(+), 40 deletions(-) diff --git a/src/cpu/testers/directedtest/InvalidateGenerator.cc b/src/cpu/testers/directedtest/InvalidateGenerator.cc index 4c248ea05..a89853061 100644 --- a/src/cpu/testers/directedtest/InvalidateGenerator.cc +++ b/src/cpu/testers/directedtest/InvalidateGenerator.cc @@ -52,7 +52,7 @@ InvalidateGenerator::~InvalidateGenerator() bool InvalidateGenerator::initiate() { - RubyDirectedTester::CpuPort* port; + MasterPort* port; Request::Flags flags; PacketPtr pkt; Packet::Command cmd; @@ -66,14 +66,12 @@ InvalidateGenerator::initiate() if (m_status == InvalidateGeneratorStatus_Load_Waiting) { DPRINTF(DirectedTest, "initiating read\n"); cmd = MemCmd::ReadReq; - port = safe_cast(m_directed_tester-> - getCpuPort(m_active_read_node)); + port = m_directed_tester->getCpuPort(m_active_read_node); pkt = new Packet(req, cmd); } else if (m_status == InvalidateGeneratorStatus_Inv_Waiting) { DPRINTF(DirectedTest, "initiating invalidating write\n"); cmd = MemCmd::WriteReq; - port = safe_cast(m_directed_tester-> - getCpuPort(m_active_inv_node)); + port = m_directed_tester->getCpuPort(m_active_inv_node); pkt = new Packet(req, cmd); } else { panic("initiate was unexpectedly called\n"); diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.hh b/src/cpu/testers/directedtest/RubyDirectedTester.hh index 0965fb786..bd0b52a90 100644 --- a/src/cpu/testers/directedtest/RubyDirectedTester.hh +++ b/src/cpu/testers/directedtest/RubyDirectedTester.hh @@ -113,7 +113,7 @@ class RubyDirectedTester : public MemObject RubyDirectedTester& operator=(const RubyDirectedTester& obj); uint64 m_requests_completed; - std::vector ports; + std::vector ports; uint64 m_requests_to_complete; DirectedGenerator* generator; }; diff --git a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc index 92dc46f85..b8c42b67d 100644 --- a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc +++ b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc @@ -52,9 +52,7 @@ SeriesRequestGenerator::initiate() DPRINTF(DirectedTest, "initiating request\n"); assert(m_status == SeriesRequestGeneratorStatus_Thinking); - RubyDirectedTester::CpuPort* port = - safe_cast(m_directed_tester-> - getCpuPort(m_active_node)); + MasterPort* port = m_directed_tester->getCpuPort(m_active_node); Request::Flags flags; diff --git a/src/cpu/testers/rubytest/Check.cc b/src/cpu/testers/rubytest/Check.cc index 892e05dd0..8188fecbb 100644 --- a/src/cpu/testers/rubytest/Check.cc +++ b/src/cpu/testers/rubytest/Check.cc @@ -82,8 +82,7 @@ Check::initiatePrefetch() DPRINTF(RubyTest, "initiating prefetch\n"); int index = random() % m_num_readers; - RubyTester::CpuPort* port = - safe_cast(m_tester_ptr->getReadableCpuPort(index)); + MasterPort* port = m_tester_ptr->getReadableCpuPort(index); Request::Flags flags; flags.set(Request::PREFETCH); @@ -95,7 +94,7 @@ Check::initiatePrefetch() cmd = MemCmd::ReadReq; // if necessary, make the request an instruction fetch - if (port->type == RubyTester::CpuPort::InstOnly) { + if (m_tester_ptr->isInstReadableCpuPort(index)) { flags.set(Request::INST_FETCH); } } else { @@ -137,8 +136,7 @@ Check::initiateFlush() DPRINTF(RubyTest, "initiating Flush\n"); int index = random() % m_num_writers; - RubyTester::CpuPort* port = - safe_cast(m_tester_ptr->getWritableCpuPort(index)); + MasterPort* port = m_tester_ptr->getWritableCpuPort(index); Request::Flags flags; @@ -168,8 +166,7 @@ Check::initiateAction() assert(m_status == TesterStatus_Idle); int index = random() % m_num_writers; - RubyTester::CpuPort* port = - safe_cast(m_tester_ptr->getWritableCpuPort(index)); + MasterPort* port = m_tester_ptr->getWritableCpuPort(index); Request::Flags flags; @@ -233,13 +230,12 @@ Check::initiateCheck() assert(m_status == TesterStatus_Ready); int index = random() % m_num_readers; - RubyTester::CpuPort* port = - safe_cast(m_tester_ptr->getReadableCpuPort(index)); + MasterPort* port = m_tester_ptr->getReadableCpuPort(index); Request::Flags flags; // If necessary, make the request an instruction fetch - if (port->type == RubyTester::CpuPort::InstOnly) { + if (m_tester_ptr->isInstReadableCpuPort(index)) { flags.set(Request::INST_FETCH); } diff --git a/src/cpu/testers/rubytest/RubyTester.cc b/src/cpu/testers/rubytest/RubyTester.cc index 67f4c372a..1e9827515 100644 --- a/src/cpu/testers/rubytest/RubyTester.cc +++ b/src/cpu/testers/rubytest/RubyTester.cc @@ -75,13 +75,11 @@ RubyTester::RubyTester(const Params *p) // for (int i = 0; i < p->port_cpuInstPort_connection_count; ++i) { readPorts.push_back(new CpuPort(csprintf("%s-instPort%d", name(), i), - this, i, - RubyTester::CpuPort::InstOnly)); + this, i)); } for (int i = 0; i < p->port_cpuDataPort_connection_count; ++i) { - CpuPort *port = NULL; - port = new CpuPort(csprintf("%s-dataPort%d", name(), i), this, i, - RubyTester::CpuPort::DataOnly); + CpuPort *port = new CpuPort(csprintf("%s-dataPort%d", name(), i), + this, i); readPorts.push_back(port); writePorts.push_back(port); } @@ -168,6 +166,12 @@ RubyTester::CpuPort::recvTiming(PacketPtr pkt) return true; } +bool +RubyTester::isInstReadableCpuPort(int idx) +{ + return idx < m_num_inst_ports; +} + MasterPort* RubyTester::getReadableCpuPort(int idx) { diff --git a/src/cpu/testers/rubytest/RubyTester.hh b/src/cpu/testers/rubytest/RubyTester.hh index aaf609e1e..266209b8f 100644 --- a/src/cpu/testers/rubytest/RubyTester.hh +++ b/src/cpu/testers/rubytest/RubyTester.hh @@ -56,23 +56,12 @@ class RubyTester : public MemObject // only instruction or data requests, not both. However, for those // RubyPorts that support both types of requests, separate InstOnly // and DataOnly CpuPorts will map to that RubyPort - // - enum Type - { - // Port supports only instruction requests - InstOnly, - // Port supports only data requests - DataOnly - }; - - CpuPort(const std::string &_name, RubyTester *_tester, int _idx, - Type _type) - : MasterPort(_name, _tester), tester(_tester), idx(_idx), - type(_type) + + CpuPort(const std::string &_name, RubyTester *_tester, int _idx) + : MasterPort(_name, _tester), tester(_tester), idx(_idx) {} int idx; - Type type; protected: virtual bool recvTiming(PacketPtr pkt); @@ -105,6 +94,8 @@ class RubyTester : public MemObject virtual MasterPort &getMasterPort(const std::string &if_name, int idx = -1); + bool isInstReadableCpuPort(int idx); + MasterPort* getReadableCpuPort(int idx); MasterPort* getWritableCpuPort(int idx); @@ -154,8 +145,8 @@ class RubyTester : public MemObject int m_num_cpus; uint64 m_checks_completed; - std::vector writePorts; - std::vector readPorts; + std::vector writePorts; + std::vector readPorts; uint64 m_checks_to_complete; int m_deadlock_threshold; int m_num_writers; -- cgit v1.2.3