From 1595558f39f6724b3f5bd630c68bcb35fe8bf012 Mon Sep 17 00:00:00 2001 From: Iru Cai Date: Tue, 11 Feb 2020 16:43:31 +0800 Subject: learning-gem5: memory access example for simple object Change-Id: I63a68239ac73b2bce3dea5692deac29a3467d27b --- .../learning_gem5/part2/simple_object_memory.py | 74 ++++++++++++++++++++++ src/learning_gem5/part2/SimpleObject.py | 5 ++ src/learning_gem5/part2/simple_object.cc | 53 +++++++++++++++- src/learning_gem5/part2/simple_object.hh | 37 +++++++++++ 4 files changed, 168 insertions(+), 1 deletion(-) create mode 100644 configs/learning_gem5/part2/simple_object_memory.py diff --git a/configs/learning_gem5/part2/simple_object_memory.py b/configs/learning_gem5/part2/simple_object_memory.py new file mode 100644 index 000000000..5f83bc37f --- /dev/null +++ b/configs/learning_gem5/part2/simple_object_memory.py @@ -0,0 +1,74 @@ +# -*- coding: utf-8 -*- +# Copyright (c) 2017 Jason Lowe-Power +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Jason Lowe-Power + +""" Simple config/run script for the HelloObject + +This is probably the simplest gem5 config file you can possibly create. +It creates a Root object and one *very* simple SimObject and simulates the +system. Since there are no events, this "simulation" should finish immediately + +""" + +from __future__ import print_function +from __future__ import absolute_import + +# import the m5 (gem5) library created when gem5 is built +import m5 +# import all of the SimObjects +from m5.objects import * + +system = System() +system.clk_domain = SrcClockDomain() +system.clk_domain.clock = '1GHz' +system.clk_domain.voltage_domain = VoltageDomain() + +system.memory = SimpleMemory(range=AddrRange('512MB')) + +system.membus = SystemXBar() +system.system_port = system.membus.slave + +system.memory.port = system.membus.master + +# Create an instantiation of the simobject you created +system.hello = SimpleObject() +system.goodbye = SimpleObject() + +system.hello.mem_side = system.membus.slave +system.goodbye.mem_side = system.membus.slave +system.goodbye.isread = False + +# set up the root SimObject and start the simulation +root = Root(full_system = False, system = system) + +# instantiate all of the objects we've created above +m5.instantiate() + +print("Beginning simulation!") +exit_event = m5.simulate() +print('Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause())) diff --git a/src/learning_gem5/part2/SimpleObject.py b/src/learning_gem5/part2/SimpleObject.py index ee7e9aef2..18ae60e3c 100644 --- a/src/learning_gem5/part2/SimpleObject.py +++ b/src/learning_gem5/part2/SimpleObject.py @@ -28,8 +28,13 @@ # Authors: Jason Lowe-Power from m5.params import * +# m5.proxy for Parent +from m5.proxy import * from m5.SimObject import SimObject class SimpleObject(SimObject): type = 'SimpleObject' cxx_header = "learning_gem5/part2/simple_object.hh" + mem_side = MasterPort("memory side port, send requests") + isread = Param.Bool(True, "is it going to read memory") + system = Param.System(Parent.any, "system object") diff --git a/src/learning_gem5/part2/simple_object.cc b/src/learning_gem5/part2/simple_object.cc index f340f1327..76dadf9c8 100644 --- a/src/learning_gem5/part2/simple_object.cc +++ b/src/learning_gem5/part2/simple_object.cc @@ -32,12 +32,63 @@ #include +#include "mem/packet.hh" +#include "mem/request.hh" +#include "sim/system.hh" + SimpleObject::SimpleObject(SimpleObjectParams *params) : - SimObject(params) + SimObject(params), + masterId(params->system->getMasterId(this)), + memPort(params->name + ".mem_side", this), + isread(params->isread), + event([this] { processEvent(); }, name() + ".event") { std::cout << "Hello World! From a SimObject!" << std::endl; } +void SimpleObject::processEvent() +{ + readAtomic(); +} + +void SimpleObject::readAtomic() +{ + uint32_t val = 0; + + RequestPtr req = std::make_shared(0x200000, 4, 0, masterId); + PacketPtr pkt = Packet::createRead(req); + + pkt->dataStatic(&val); + // pkt->setData((const uint8_t *)&x); + + Tick t = memPort.sendAtomic(pkt); + std::cout << "sendAtomic read " << t << " ticks." << std::endl; + std::cout << "read value 0x" << std::hex << val << std::endl; +} + +void SimpleObject::writeAtomic() +{ + RequestPtr req = std::make_shared(0x200000, 4, 0, masterId); + PacketPtr pkt = Packet::createWrite(req); + + uint32_t x = 0xdeadbeef; + pkt->dataStatic(&x); + // pkt->setData((const uint8_t *)&x); + + Tick t = memPort.sendAtomic(pkt); + std::cout << "sendAtomic write " << t << " ticks." << std::endl; +} + +void SimpleObject::startup() +{ + if (!isread) { + writeAtomic(); + } else { + schedule(event, 40000); + } + +} + SimpleObject* SimpleObjectParams::create() { diff --git a/src/learning_gem5/part2/simple_object.hh b/src/learning_gem5/part2/simple_object.hh index 53a6ec919..53fa1fea1 100644 --- a/src/learning_gem5/part2/simple_object.hh +++ b/src/learning_gem5/part2/simple_object.hh @@ -31,13 +31,50 @@ #ifndef __LEARNING_GEM5_SIMPLE_OBJECT_HH__ #define __LEARNING_GEM5_SIMPLE_OBJECT_HH__ +#include "mem/port.hh" #include "params/SimpleObject.hh" #include "sim/sim_object.hh" class SimpleObject : public SimObject { + class SimplePort: public MasterPort + { + public: + // these virtual functions must be implemented + virtual bool recvTimingResp(PacketPtr pkt) + { + fatal("SimplePort::recvTimingResp not implemented!\n"); + } + virtual void recvReqRetry() + { + fatal("SimplePort::recvReqRetry not implemented!\n"); + } + // SimplePort::SimplePort() is deleted + SimplePort(const std::string &name, SimpleObject *owner): + MasterPort(name, owner) + { + } + + }; + + MasterID masterId; + SimplePort memPort; + bool isread; + EventFunctionWrapper event; + public: SimpleObject(SimpleObjectParams *p); + virtual Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override + { + if (if_name == "mem_side") + return memPort; + return SimpleObject::getPort(if_name, idx); + } + virtual void startup() override; + void processEvent(); + void readAtomic(); + void writeAtomic(); }; #endif // __LEARNING_GEM5_SIMPLE_OBJECT_HH__ -- cgit v1.2.3