From 1e1d5e247ecc55dc3d92875ca5ec6ae70879d8c1 Mon Sep 17 00:00:00 2001
From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Mon, 2 Sep 2019 15:28:58 +0100
Subject: arch-arm: MISCREG_ICC_BPR1_EL1 using AA64 banking

Change-Id: Ib30c7a49490f05f88ddfd7572dd360cb92647f81
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20625
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/arch/arm/miscregs.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 0bae01893..76a991746 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -4603,7 +4603,7 @@ ISA::initializeMiscRegMetadata()
         .allPrivileges().exceptUserMode().writes(0)
         .mapsTo(MISCREG_ICC_HPPIR1);
     InitReg(MISCREG_ICC_BPR1_EL1)
-        .banked()
+        .banked64()
         .mapsTo(MISCREG_ICC_BPR1);
     InitReg(MISCREG_ICC_BPR1_EL1_NS)
         .bankedChild()
-- 
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