From aff3d92c007f7c971eed8417b1d7602394755398 Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Tue, 10 Oct 2006 17:25:50 -0400
Subject: Some more code cleanup

src/mem/cache/base_cache.cc:
    Add sanity checks
src/mem/cache/base_cache.hh:
    Fix for retry mechanism

--HG--
extra : convert_revision : 9298e32e64194b1ef3fe51242595eaa56dcbbcfd
---
 src/mem/cache/base_cache.cc | 2 ++
 src/mem/cache/base_cache.hh | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index 0141fa2a0..4df13fb2b 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -221,6 +221,7 @@ BaseCache::CacheEvent::process()
         }
         else if (!cachePort->isCpuSide)
         {
+            assert(cachePort->cache->doMasterRequest());
             //MSHR
             pkt = cachePort->cache->getPacket();
             MSHR* mshr = (MSHR*) pkt->senderState;
@@ -238,6 +239,7 @@ BaseCache::CacheEvent::process()
         }
         else
         {
+            assert(cachePort->cache->doSlaveRequest());
             //CSHR
             pkt = cachePort->cache->getCoherencePacket();
             bool success = cachePort->sendTiming(pkt);
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index 41c28f3a1..563b1ca8b 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -467,7 +467,7 @@ class BaseCache : public MemObject
      */
     void setMasterRequest(RequestCause cause, Tick time)
     {
-        if (!doMasterRequest() && memSidePort->drainList.empty())
+        if (!doMasterRequest() && !memSidePort->waitingOnRetry)
         {
             BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(memSidePort);
             reqCpu->schedule(time);
-- 
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