From 2a818db77ab5fe5cc7d716dd2aa88241550045a7 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Tue, 20 Aug 2019 20:48:29 +0100 Subject: arch-arm, dev-arm: MISCREG_ICC_IGRPEN1_EL1 using AA64 banking Change-Id: Ic08ac1e7f3ebef408a83aa068ce15e9dfe2aa3cd Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20628 Maintainer: Andreas Sandberg Tested-by: kokoro --- src/arch/arm/miscregs.cc | 2 +- src/dev/arm/gic_v3_cpu_interface.cc | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 81bc3efae..bffb4446a 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -4646,7 +4646,7 @@ ISA::initializeMiscRegMetadata() .allPrivileges().exceptUserMode() .mapsTo(MISCREG_ICC_IGRPEN0); InitReg(MISCREG_ICC_IGRPEN1_EL1) - .banked() + .banked64() .mapsTo(MISCREG_ICC_IGRPEN1); InitReg(MISCREG_ICC_IGRPEN1_EL1_NS) .bankedChild() diff --git a/src/dev/arm/gic_v3_cpu_interface.cc b/src/dev/arm/gic_v3_cpu_interface.cc index 0d444f165..b793f7c28 100644 --- a/src/dev/arm/gic_v3_cpu_interface.cc +++ b/src/dev/arm/gic_v3_cpu_interface.cc @@ -191,6 +191,7 @@ Gicv3CPUInterface::readMiscReg(int misc_reg) return readMiscReg(MISCREG_ICV_IGRPEN1_EL1); } + value = readBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1); break; } @@ -1358,7 +1359,8 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val) icc_igrpen1_el3); } - break; + setBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1, val); + return; } // Virtual Interrupt Group 1 Enable register -- cgit v1.2.3