From 373e55c7b9bb2ec7be12ca31e6ecdd5180c00b2e Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Tue, 12 May 2009 20:30:40 -0400 Subject: inorder-regress: missing regress config file regressions need to access this file to setup the InOrderCPU object --- tests/configs/inorder-timing.py | 52 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 tests/configs/inorder-timing.py diff --git a/tests/configs/inorder-timing.py b/tests/configs/inorder-timing.py new file mode 100644 index 000000000..62f8b5850 --- /dev/null +++ b/tests/configs/inorder-timing.py @@ -0,0 +1,52 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Steve Reinhardt + +import m5 +from m5.objects import * +m5.AddToPath('../configs/common') + +class MyCache(BaseCache): + assoc = 2 + block_size = 64 + latency = '1ns' + mshrs = 10 + tgts_per_mshr = 5 + +cpu = InOrderCPU(cpu_id=0) +cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), + MyCache(size = '2MB', latency='10ns')) + +cpu.clock = '2GHz' + +system = System(cpu = cpu, + physmem = PhysicalMemory(), + membus = Bus()) +system.physmem.port = system.membus.port +cpu.connectMemPorts(system.membus) + +root = Root(system = system) -- cgit v1.2.3