From 374ba9bae359e68c1496f8db25c38a817af2da19 Mon Sep 17 00:00:00 2001
From: Nathan Binkert <nate@binkert.org>
Date: Wed, 8 Apr 2009 22:21:30 -0700
Subject: tests: update tests for TLB unification

---
 .../00.gzip/ref/alpha/tru64/o3-timing/config.ini   |   4 +-
 .../long/00.gzip/ref/alpha/tru64/o3-timing/simout  |   8 +-
 .../00.gzip/ref/alpha/tru64/o3-timing/stats.txt    |  40 ++++--
 .../ref/alpha/tru64/simple-atomic/config.ini       |   4 +-
 .../00.gzip/ref/alpha/tru64/simple-atomic/simout   |  10 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt        |  40 ++++--
 .../ref/alpha/tru64/simple-timing/config.ini       |   4 +-
 .../00.gzip/ref/alpha/tru64/simple-timing/simout   |  10 +-
 .../ref/alpha/tru64/simple-timing/stats.txt        |  40 ++++--
 .../00.gzip/ref/sparc/linux/o3-timing/config.ini   |   4 +-
 .../long/00.gzip/ref/sparc/linux/o3-timing/simout  |   8 +-
 .../00.gzip/ref/sparc/linux/o3-timing/stats.txt    |   8 +-
 .../ref/sparc/linux/simple-atomic/config.ini       |   4 +-
 .../00.gzip/ref/sparc/linux/simple-atomic/simout   |  10 +-
 .../ref/sparc/linux/simple-atomic/stats.txt        |   8 +-
 .../ref/sparc/linux/simple-timing/config.ini       |   4 +-
 .../00.gzip/ref/sparc/linux/simple-timing/simout   |   8 +-
 .../ref/sparc/linux/simple-timing/stats.txt        |   8 +-
 .../00.gzip/ref/x86/linux/simple-atomic/config.ini |   4 +-
 .../00.gzip/ref/x86/linux/simple-atomic/simout     |  10 +-
 .../00.gzip/ref/x86/linux/simple-atomic/stats.txt  |   8 +-
 .../00.gzip/ref/x86/linux/simple-timing/config.ini |   4 +-
 .../00.gzip/ref/x86/linux/simple-timing/simout     |  10 +-
 .../00.gzip/ref/x86/linux/simple-timing/stats.txt  |   8 +-
 .../ref/alpha/linux/tsunami-o3-dual/config.ini     |   8 +-
 .../ref/alpha/linux/tsunami-o3-dual/simout         |   8 +-
 .../ref/alpha/linux/tsunami-o3-dual/stats.txt      |  72 ++++++++---
 .../ref/alpha/linux/tsunami-o3/config.ini          |   4 +-
 .../ref/alpha/linux/tsunami-o3/simout              |   8 +-
 .../ref/alpha/linux/tsunami-o3/stats.txt           |  40 ++++--
 .../ref/sparc/linux/simple-atomic/config.ini       |   4 +-
 .../10.mcf/ref/sparc/linux/simple-atomic/simout    |  10 +-
 .../10.mcf/ref/sparc/linux/simple-atomic/stats.txt |   8 +-
 .../ref/sparc/linux/simple-timing/config.ini       |   4 +-
 .../10.mcf/ref/sparc/linux/simple-timing/simout    |   8 +-
 .../10.mcf/ref/sparc/linux/simple-timing/stats.txt |   8 +-
 .../10.mcf/ref/x86/linux/simple-atomic/config.ini  |   4 +-
 .../long/10.mcf/ref/x86/linux/simple-atomic/simout |  10 +-
 .../10.mcf/ref/x86/linux/simple-atomic/stats.txt   |   8 +-
 .../10.mcf/ref/x86/linux/simple-timing/config.ini  |   4 +-
 .../long/10.mcf/ref/x86/linux/simple-timing/simout |  10 +-
 .../10.mcf/ref/x86/linux/simple-timing/stats.txt   |   8 +-
 .../ref/x86/linux/simple-atomic/config.ini         |   4 +-
 .../20.parser/ref/x86/linux/simple-atomic/simout   |  10 +-
 .../ref/x86/linux/simple-atomic/stats.txt          |   8 +-
 .../ref/x86/linux/simple-timing/config.ini         |   4 +-
 .../20.parser/ref/x86/linux/simple-timing/simout   |  10 +-
 .../ref/x86/linux/simple-timing/stats.txt          |   8 +-
 .../30.eon/ref/alpha/tru64/o3-timing/config.ini    |   4 +-
 tests/long/30.eon/ref/alpha/tru64/o3-timing/simout |   8 +-
 .../30.eon/ref/alpha/tru64/o3-timing/stats.txt     |  40 ++++--
 .../ref/alpha/tru64/simple-atomic/config.ini       |   4 +-
 .../30.eon/ref/alpha/tru64/simple-atomic/simout    |  10 +-
 .../30.eon/ref/alpha/tru64/simple-atomic/stats.txt |  40 ++++--
 .../ref/alpha/tru64/simple-timing/config.ini       |   4 +-
 .../30.eon/ref/alpha/tru64/simple-timing/simout    |  10 +-
 .../30.eon/ref/alpha/tru64/simple-timing/stats.txt |  40 ++++--
 .../ref/alpha/tru64/o3-timing/config.ini           |   4 +-
 .../40.perlbmk/ref/alpha/tru64/o3-timing/simout    |   8 +-
 .../40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt |  40 ++++--
 .../ref/alpha/tru64/simple-atomic/config.ini       |   4 +-
 .../ref/alpha/tru64/simple-atomic/simout           |  10 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt        |  40 ++++--
 .../ref/alpha/tru64/simple-timing/config.ini       |   4 +-
 .../ref/alpha/tru64/simple-timing/simout           |  10 +-
 .../ref/alpha/tru64/simple-timing/stats.txt        |  40 ++++--
 .../50.vortex/ref/alpha/tru64/o3-timing/config.ini |   4 +-
 .../50.vortex/ref/alpha/tru64/o3-timing/simout     |   8 +-
 .../50.vortex/ref/alpha/tru64/o3-timing/stats.txt  |  40 ++++--
 .../ref/alpha/tru64/simple-atomic/config.ini       |   4 +-
 .../50.vortex/ref/alpha/tru64/simple-atomic/simout |  10 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt        |  40 ++++--
 .../ref/alpha/tru64/simple-timing/config.ini       |   4 +-
 .../50.vortex/ref/alpha/tru64/simple-timing/simout |  10 +-
 .../ref/alpha/tru64/simple-timing/stats.txt        |  40 ++++--
 .../ref/sparc/linux/simple-atomic/config.ini       |   4 +-
 .../50.vortex/ref/sparc/linux/simple-atomic/simout |  10 +-
 .../ref/sparc/linux/simple-atomic/stats.txt        |   8 +-
 .../ref/sparc/linux/simple-timing/config.ini       |   4 +-
 .../50.vortex/ref/sparc/linux/simple-timing/simout |   8 +-
 .../ref/sparc/linux/simple-timing/stats.txt        |   8 +-
 .../60.bzip2/ref/alpha/tru64/o3-timing/config.ini  |   4 +-
 .../long/60.bzip2/ref/alpha/tru64/o3-timing/simout |   8 +-
 .../60.bzip2/ref/alpha/tru64/o3-timing/stats.txt   |  40 ++++--
 .../ref/alpha/tru64/simple-atomic/config.ini       |   4 +-
 .../60.bzip2/ref/alpha/tru64/simple-atomic/simout  |  10 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt        |  40 ++++--
 .../ref/alpha/tru64/simple-timing/config.ini       |   4 +-
 .../60.bzip2/ref/alpha/tru64/simple-timing/simout  |  10 +-
 .../ref/alpha/tru64/simple-timing/stats.txt        |  40 ++++--
 .../ref/x86/linux/simple-atomic/config.ini         |   4 +-
 .../60.bzip2/ref/x86/linux/simple-atomic/simout    |  10 +-
 .../60.bzip2/ref/x86/linux/simple-atomic/stats.txt |   8 +-
 .../ref/x86/linux/simple-timing/config.ini         |   4 +-
 .../60.bzip2/ref/x86/linux/simple-timing/simout    |  10 +-
 .../60.bzip2/ref/x86/linux/simple-timing/stats.txt |   8 +-
 .../70.twolf/ref/alpha/tru64/o3-timing/config.ini  |   4 +-
 .../long/70.twolf/ref/alpha/tru64/o3-timing/simout |   8 +-
 .../70.twolf/ref/alpha/tru64/o3-timing/stats.txt   |  40 ++++--
 .../ref/alpha/tru64/simple-atomic/config.ini       |   4 +-
 .../70.twolf/ref/alpha/tru64/simple-atomic/simout  |  10 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt        |  40 ++++--
 .../ref/alpha/tru64/simple-timing/config.ini       |   4 +-
 .../70.twolf/ref/alpha/tru64/simple-timing/simout  |  10 +-
 .../ref/alpha/tru64/simple-timing/stats.txt        |  40 ++++--
 .../ref/sparc/linux/simple-atomic/config.ini       |   4 +-
 .../70.twolf/ref/sparc/linux/simple-atomic/simout  |  10 +-
 .../ref/sparc/linux/simple-atomic/stats.txt        |   8 +-
 .../ref/sparc/linux/simple-timing/config.ini       |   4 +-
 .../70.twolf/ref/sparc/linux/simple-timing/simout  |  12 +-
 .../ref/sparc/linux/simple-timing/stats.txt        |   8 +-
 .../ref/x86/linux/simple-atomic/config.ini         |   4 +-
 .../70.twolf/ref/x86/linux/simple-atomic/simout    |  12 +-
 .../70.twolf/ref/x86/linux/simple-atomic/stats.txt |   8 +-
 .../ref/x86/linux/simple-timing/config.ini         |   4 +-
 .../70.twolf/ref/x86/linux/simple-timing/simout    |  12 +-
 .../70.twolf/ref/x86/linux/simple-timing/stats.txt |   8 +-
 .../sparc/solaris/t1000-simple-atomic/config.ini   |   4 +-
 .../ref/sparc/solaris/t1000-simple-atomic/simout   |  10 +-
 .../sparc/solaris/t1000-simple-atomic/stats.txt    |   8 +-
 .../00.hello/ref/alpha/linux/o3-timing/config.ini  |   4 +-
 .../00.hello/ref/alpha/linux/o3-timing/simout      |   8 +-
 .../00.hello/ref/alpha/linux/o3-timing/stats.txt   |  40 ++++--
 .../ref/alpha/linux/simple-atomic/config.ini       |   4 +-
 .../00.hello/ref/alpha/linux/simple-atomic/simout  |  10 +-
 .../ref/alpha/linux/simple-atomic/stats.txt        |  38 ++++--
 .../ref/alpha/linux/simple-timing/config.ini       |   4 +-
 .../00.hello/ref/alpha/linux/simple-timing/simout  |  10 +-
 .../ref/alpha/linux/simple-timing/stats.txt        |  40 ++++--
 .../00.hello/ref/alpha/tru64/o3-timing/config.ini  |   4 +-
 .../00.hello/ref/alpha/tru64/o3-timing/simout      |   8 +-
 .../00.hello/ref/alpha/tru64/o3-timing/stats.txt   |  40 ++++--
 .../ref/alpha/tru64/simple-atomic/config.ini       |   4 +-
 .../00.hello/ref/alpha/tru64/simple-atomic/simout  |  10 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt        |  40 ++++--
 .../ref/alpha/tru64/simple-timing/config.ini       |   4 +-
 .../00.hello/ref/alpha/tru64/simple-timing/simout  |  10 +-
 .../ref/alpha/tru64/simple-timing/stats.txt        |  40 ++++--
 .../ref/mips/linux/simple-atomic/config.ini        |  12 +-
 .../00.hello/ref/mips/linux/simple-atomic/simout   |  10 +-
 .../ref/mips/linux/simple-atomic/stats.txt         |  26 +---
 .../ref/mips/linux/simple-timing/config.ini        |  12 +-
 .../00.hello/ref/mips/linux/simple-timing/simout   |  10 +-
 .../ref/mips/linux/simple-timing/stats.txt         |  26 +---
 .../ref/sparc/linux/simple-atomic/config.ini       |   4 +-
 .../00.hello/ref/sparc/linux/simple-atomic/simout  |  10 +-
 .../ref/sparc/linux/simple-atomic/stats.txt        |   8 +-
 .../ref/sparc/linux/simple-timing/config.ini       |   4 +-
 .../00.hello/ref/sparc/linux/simple-timing/simout  |  10 +-
 .../ref/sparc/linux/simple-timing/stats.txt        |   8 +-
 .../ref/x86/linux/simple-atomic/config.ini         |   4 +-
 .../00.hello/ref/x86/linux/simple-atomic/simout    |  10 +-
 .../00.hello/ref/x86/linux/simple-atomic/stats.txt |   8 +-
 .../ref/x86/linux/simple-timing/config.ini         |   4 +-
 .../00.hello/ref/x86/linux/simple-timing/simout    |  10 +-
 .../00.hello/ref/x86/linux/simple-timing/stats.txt |   8 +-
 .../ref/alpha/linux/o3-timing/config.ini           |   4 +-
 .../ref/alpha/linux/o3-timing/simout               |   8 +-
 .../ref/alpha/linux/o3-timing/stats.txt            |  40 ++++--
 .../ref/sparc/linux/o3-timing/config.ini           |   4 +-
 .../02.insttest/ref/sparc/linux/o3-timing/simout   |   8 +-
 .../ref/sparc/linux/o3-timing/stats.txt            |   8 +-
 .../ref/sparc/linux/simple-atomic/config.ini       |   4 +-
 .../ref/sparc/linux/simple-atomic/simout           |  10 +-
 .../ref/sparc/linux/simple-atomic/stats.txt        |   8 +-
 .../ref/sparc/linux/simple-timing/config.ini       |   4 +-
 .../ref/sparc/linux/simple-timing/simout           |  10 +-
 .../ref/sparc/linux/simple-timing/stats.txt        |   8 +-
 .../linux/tsunami-simple-atomic-dual/config.ini    |   8 +-
 .../alpha/linux/tsunami-simple-atomic-dual/simout  |  10 +-
 .../linux/tsunami-simple-atomic-dual/stats.txt     |  72 ++++++++---
 .../alpha/linux/tsunami-simple-atomic/config.ini   |   4 +-
 .../ref/alpha/linux/tsunami-simple-atomic/simout   |  10 +-
 .../alpha/linux/tsunami-simple-atomic/stats.txt    |  40 ++++--
 .../linux/tsunami-simple-timing-dual/config.ini    |   8 +-
 .../alpha/linux/tsunami-simple-timing-dual/simout  |  10 +-
 .../linux/tsunami-simple-timing-dual/stats.txt     |  72 ++++++++---
 .../alpha/linux/tsunami-simple-timing/config.ini   |   4 +-
 .../ref/alpha/linux/tsunami-simple-timing/simout   |  10 +-
 .../alpha/linux/tsunami-simple-timing/stats.txt    |  40 ++++--
 .../ref/alpha/eio/simple-atomic/config.ini         |   4 +-
 .../ref/alpha/eio/simple-atomic/simout             |  10 +-
 .../ref/alpha/eio/simple-atomic/stats.txt          |  40 ++++--
 .../ref/alpha/eio/simple-timing/config.ini         |   4 +-
 .../ref/alpha/eio/simple-timing/simout             |  10 +-
 .../ref/alpha/eio/simple-timing/stats.txt          |  40 ++++--
 .../ref/alpha/eio/simple-atomic-mp/config.ini      |  16 +--
 .../ref/alpha/eio/simple-atomic-mp/simout          |  10 +-
 .../ref/alpha/eio/simple-atomic-mp/stats.txt       | 136 ++++++++++++++------
 .../ref/alpha/eio/simple-timing-mp/config.ini      |  16 +--
 .../ref/alpha/eio/simple-timing-mp/simout          |  10 +-
 .../ref/alpha/eio/simple-timing-mp/stats.txt       | 136 ++++++++++++++------
 .../50.memtest/ref/alpha/linux/memtest/simout      |  10 +-
 .../50.memtest/ref/alpha/linux/memtest/stats.txt   |   6 +-
 .../linux/twosys-tsunami-simple-atomic/config.ini  |  12 +-
 .../linux/twosys-tsunami-simple-atomic/simout      |  10 +-
 .../linux/twosys-tsunami-simple-atomic/stats.txt   | 142 +++++++++++++++------
 197 files changed, 1885 insertions(+), 1171 deletions(-)

diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
index 068fb2315..b2e89e8ab 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
@@ -132,7 +132,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu.fuPool]
@@ -305,7 +305,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu.l2cache]
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
index 0988daaa5..635bbafa8 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar  6 2009 18:15:46
-M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
-M5 started Mar  6 2009 18:15:58
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:37:48
 M5 executing on maize
-command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py long/00.gzip/alpha/tru64/o3-timing
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
index b3f903358..ace5a05aa 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 309694                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 206028                       # Number of bytes of host memory used
-host_seconds                                  1826.17                       # Real time elapsed on the host
-host_tick_rate                               91491135                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 312901                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 206004                       # Number of bytes of host memory used
+host_seconds                                  1807.45                       # Real time elapsed on the host
+host_tick_rate                               92438667                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   565552443                       # Number of instructions simulated
 sim_seconds                                  0.167078                       # Number of seconds simulated
@@ -123,10 +123,14 @@ system.cpu.decode.DECODE:RunCycles          123896058                       # Nu
 system.cpu.decode.DECODE:SquashCycles         9869862                       # Number of cycles decode is squashing
 system.cpu.decode.DECODE:SquashedInsts           2004                       # Number of squashed instructions handled by decode
 system.cpu.decode.DECODE:UnblockCycles        5413191                       # Number of cycles decode is unblocking
-system.cpu.dtb.accesses                     163077390                       # DTB accesses
-system.cpu.dtb.acv                                  0                       # DTB access violations
-system.cpu.dtb.hits                         163013880                       # DTB hits
-system.cpu.dtb.misses                           63510                       # DTB misses
+system.cpu.dtb.data_accesses                163077390                       # DTB accesses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_hits                    163013880                       # DTB hits
+system.cpu.dtb.data_misses                      63510                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                122284109                       # DTB read accesses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
 system.cpu.dtb.read_hits                    122260496                       # DTB read hits
@@ -319,10 +323,22 @@ system.cpu.iq.iqSquashedInstsExamined        53519286                       # Nu
 system.cpu.iq.iqSquashedInstsIssued             12833                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved              6                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined     29313548                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses                      66014446                       # ITB accesses
-system.cpu.itb.acv                                  0                       # ITB acv
-system.cpu.itb.hits                          66014406                       # ITB hits
-system.cpu.itb.misses                              40                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses                66014446                       # ITB accesses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_hits                    66014406                       # ITB hits
+system.cpu.itb.fetch_misses                        40                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.l2cache.ReadExReq_accesses          256647                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency 34260.342026                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31141.538767                       # average ReadExReq mshr miss latency
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
index 53e8ae1eb..af1fb07c3 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
@@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
 icache_port=system.membus.port[1]
 
 [system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu.tracer]
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
index 2a4b52a28..512d13649 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:27:51
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py long/00.gzip/alpha/tru64/simple-atomic
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:34:49
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
index d5f13f08c..aa16ad6b4 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,17 +1,21 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                6175770                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 195684                       # Number of bytes of host memory used
-host_seconds                                    97.45                       # Real time elapsed on the host
-host_tick_rate                             3087904278                       # Simulator tick rate (ticks/s)
+host_inst_rate                                5975527                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 197448                       # Number of bytes of host memory used
+host_seconds                                   100.72                       # Real time elapsed on the host
+host_tick_rate                             2987780856                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   601856964                       # Number of instructions simulated
 sim_seconds                                  0.300931                       # Number of seconds simulated
 sim_ticks                                300930958000                       # Number of ticks simulated
-system.cpu.dtb.accesses                     153970296                       # DTB accesses
-system.cpu.dtb.acv                                  0                       # DTB access violations
-system.cpu.dtb.hits                         153965363                       # DTB hits
-system.cpu.dtb.misses                            4933                       # DTB misses
+system.cpu.dtb.data_accesses                153970296                       # DTB accesses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_hits                    153965363                       # DTB hits
+system.cpu.dtb.data_misses                       4933                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                114516673                       # DTB read accesses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
 system.cpu.dtb.read_hits                    114514042                       # DTB read hits
@@ -21,10 +25,22 @@ system.cpu.dtb.write_acv                            0                       # DT
 system.cpu.dtb.write_hits                    39451321                       # DTB write hits
 system.cpu.dtb.write_misses                      2302                       # DTB write misses
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                     601861917                       # ITB accesses
-system.cpu.itb.acv                                  0                       # ITB acv
-system.cpu.itb.hits                         601861897                       # ITB hits
-system.cpu.itb.misses                              20                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses               601861917                       # ITB accesses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_hits                   601861897                       # ITB hits
+system.cpu.itb.fetch_misses                        20                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                        601861917                       # number of cpu cycles simulated
 system.cpu.num_insts                        601856964                       # Number of instructions executed
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
index 6d294469b..b0f992d6d 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu.l2cache]
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
index 8b3b6bb5d..20994514f 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:27:51
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py long/00.gzip/alpha/tru64/simple-timing
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:34:42
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
index 57d9b05f8..d4bd93848 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1969135                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 203124                       # Number of bytes of host memory used
-host_seconds                                   305.65                       # Real time elapsed on the host
-host_tick_rate                             2545444210                       # Simulator tick rate (ticks/s)
+host_inst_rate                                3011769                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 204988                       # Number of bytes of host memory used
+host_seconds                                   199.84                       # Real time elapsed on the host
+host_tick_rate                             3893225431                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   601856964                       # Number of instructions simulated
 sim_seconds                                  0.778004                       # Number of seconds simulated
@@ -71,10 +71,14 @@ system.cpu.dcache.tagsinuse               4094.195523                       # Cy
 system.cpu.dcache.total_refs                153509968                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              579204000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                   325723                       # number of writebacks
-system.cpu.dtb.accesses                     153970296                       # DTB accesses
-system.cpu.dtb.acv                                  0                       # DTB access violations
-system.cpu.dtb.hits                         153965363                       # DTB hits
-system.cpu.dtb.misses                            4933                       # DTB misses
+system.cpu.dtb.data_accesses                153970296                       # DTB accesses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_hits                    153965363                       # DTB hits
+system.cpu.dtb.data_misses                       4933                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                114516673                       # DTB read accesses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
 system.cpu.dtb.read_hits                    114514042                       # DTB read hits
@@ -137,10 +141,22 @@ system.cpu.icache.total_refs                601861103                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                     601861918                       # ITB accesses
-system.cpu.itb.acv                                  0                       # ITB acv
-system.cpu.itb.hits                         601861898                       # ITB hits
-system.cpu.itb.misses                              20                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses               601861918                       # ITB accesses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_hits                   601861898                       # ITB hits
+system.cpu.itb.fetch_misses                        20                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.l2cache.ReadExReq_accesses          254163                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
index ee1f88977..35d154fac 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
@@ -132,7 +132,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=SparcDTB
+type=SparcTLB
 size=64
 
 [system.cpu.fuPool]
@@ -305,7 +305,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=SparcITB
+type=SparcTLB
 size=64
 
 [system.cpu.l2cache]
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
index 293987f44..f6e5574f7 100755
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 16 2009 00:51:12
-M5 revision 208de84f046d 6013 default tip
-M5 started Mar 16 2009 00:51:29
-M5 executing on zizzer
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:30:04
+M5 executing on maize
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
index 3e5a615cf..c367ac34c 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 159348                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 206344                       # Number of bytes of host memory used
-host_seconds                                  8821.04                       # Real time elapsed on the host
-host_tick_rate                              125003315                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 150366                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 208016                       # Number of bytes of host memory used
+host_seconds                                  9347.96                       # Real time elapsed on the host
+host_tick_rate                              117957212                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1405618365                       # Number of instructions simulated
 sim_seconds                                  1.102659                       # Number of seconds simulated
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
index 8d0eebe28..92041a7ce 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
@@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
 icache_port=system.membus.port[1]
 
 [system.cpu.dtb]
-type=SparcDTB
+type=SparcTLB
 size=64
 
 [system.cpu.itb]
-type=SparcITB
+type=SparcTLB
 size=64
 
 [system.cpu.tracer]
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
index d1dad3acf..2a36b7985 100755
--- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:17:12
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:46:25
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py long/00.gzip/sparc/linux/simple-atomic
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:31:00
+M5 executing on maize
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
index d5f28736a..077429fb4 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                3714547                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 197792                       # Number of bytes of host memory used
-host_seconds                                   401.00                       # Real time elapsed on the host
-host_tick_rate                             1857278454                       # Simulator tick rate (ticks/s)
+host_inst_rate                                3659022                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 199544                       # Number of bytes of host memory used
+host_seconds                                   407.08                       # Real time elapsed on the host
+host_tick_rate                             1829515892                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1489523295                       # Number of instructions simulated
 sim_seconds                                  0.744764                       # Number of seconds simulated
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
index 90217b2a5..7de5a10fa 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=SparcDTB
+type=SparcTLB
 size=64
 
 [system.cpu.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=SparcITB
+type=SparcTLB
 size=64
 
 [system.cpu.l2cache]
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
index d75186ab5..73072ad1d 100755
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 16 2009 00:51:12
-M5 revision 208de84f046d 6013 default tip
-M5 started Mar 16 2009 00:51:29
-M5 executing on zizzer
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:32:24
+M5 executing on maize
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
index 8851d2d2a..f480451f2 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1328193                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 205396                       # Number of bytes of host memory used
-host_seconds                                  1121.47                       # Real time elapsed on the host
-host_tick_rate                             1851148785                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1898996                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 207084                       # Number of bytes of host memory used
+host_seconds                                   784.37                       # Real time elapsed on the host
+host_tick_rate                             2646697045                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1489523295                       # Number of instructions simulated
 sim_seconds                                  2.076001                       # Number of seconds simulated
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
index 1f354a5d6..8edc68d8c 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
@@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
 icache_port=system.membus.port[1]
 
 [system.cpu.dtb]
-type=X86DTB
+type=X86TLB
 size=64
 
 [system.cpu.itb]
-type=X86ITB
+type=X86TLB
 size=64
 
 [system.cpu.tracer]
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
index 875533d57..a87cf6c93 100755
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 24 2009 22:05:32
-M5 revision dda4746d9215 5940 default qtip tip rtcbcd.patch
-M5 started Feb 24 2009 22:07:57
-M5 executing on tater
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py long/00.gzip/x86/linux/simple-atomic
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:59:49
+M5 executing on maize
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
index 0158d9e3d..d6c1760ba 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1045935                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 197296                       # Number of bytes of host memory used
-host_seconds                                  1548.25                       # Real time elapsed on the host
-host_tick_rate                              621947296                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2819266                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 199720                       # Number of bytes of host memory used
+host_seconds                                   574.39                       # Real time elapsed on the host
+host_tick_rate                             1676428354                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1619365942                       # Number of instructions simulated
 sim_seconds                                  0.962929                       # Number of seconds simulated
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
index 1e457c793..3764c63b0 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=X86DTB
+type=X86TLB
 size=64
 
 [system.cpu.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=X86ITB
+type=X86TLB
 size=64
 
 [system.cpu.l2cache]
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
index 4f608c9b1..d1ddd37b9 100755
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 24 2009 22:05:32
-M5 revision dda4746d9215 5940 default qtip tip rtcbcd.patch
-M5 started Feb 24 2009 22:07:57
-M5 executing on tater
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py long/00.gzip/x86/linux/simple-timing
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 13:09:59
+M5 executing on maize
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
index b764de67a..2cd851868 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 660241                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 204740                       # Number of bytes of host memory used
-host_seconds                                  2452.69                       # Real time elapsed on the host
-host_tick_rate                              739961389                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1747793                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 207260                       # Number of bytes of host memory used
+host_seconds                                   926.52                       # Real time elapsed on the host
+host_tick_rate                             1958830620                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1619365942                       # Number of instructions simulated
 sim_seconds                                  1.814897                       # Number of seconds simulated
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
index cd4931e34..e37ceeeed 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
@@ -158,7 +158,7 @@ cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.port[2]
 
 [system.cpu0.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu0.fuPool]
@@ -334,7 +334,7 @@ mem_side=system.toL2Bus.port[1]
 type=AlphaInterrupts
 
 [system.cpu0.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu0.tracer]
@@ -465,7 +465,7 @@ cpu_side=system.cpu1.dcache_port
 mem_side=system.toL2Bus.port[4]
 
 [system.cpu1.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu1.fuPool]
@@ -641,7 +641,7 @@ mem_side=system.toL2Bus.port[3]
 type=AlphaInterrupts
 
 [system.cpu1.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu1.tracer]
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
index a6115dc06..5616a9db3 100755
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar  6 2009 18:15:39
-M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
-M5 started Mar  6 2009 18:15:43
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:30:05
 M5 executing on maize
-command line: /n/blue/z/binkert/build/work/build/ALPHA_FS/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3-dual
+command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
index a35446ce7..00fb3cdfd 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 195579                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 296668                       # Number of bytes of host memory used
-host_seconds                                   287.30                       # Real time elapsed on the host
-host_tick_rate                             6640015618                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 198409                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 296696                       # Number of bytes of host memory used
+host_seconds                                   283.21                       # Real time elapsed on the host
+host_tick_rate                             6736112914                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    56190549                       # Number of instructions simulated
 sim_seconds                                  1.907705                       # Number of seconds simulated
@@ -146,10 +146,14 @@ system.cpu0.decode.DECODE:RunCycles           9143957                       # Nu
 system.cpu0.decode.DECODE:SquashCycles        1094068                       # Number of cycles decode is squashing
 system.cpu0.decode.DECODE:SquashedInsts         84180                       # Number of squashed instructions handled by decode
 system.cpu0.decode.DECODE:UnblockCycles        924165                       # Number of cycles decode is unblocking
-system.cpu0.dtb.accesses                       812672                       # DTB accesses
-system.cpu0.dtb.acv                               801                       # DTB access violations
-system.cpu0.dtb.hits                         11625470                       # DTB hits
-system.cpu0.dtb.misses                          28525                       # DTB misses
+system.cpu0.dtb.data_accesses                  812672                       # DTB accesses
+system.cpu0.dtb.data_acv                          801                       # DTB access violations
+system.cpu0.dtb.data_hits                    11625470                       # DTB hits
+system.cpu0.dtb.data_misses                     28525                       # DTB misses
+system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu0.dtb.fetch_acv                           0                       # ITB acv
+system.cpu0.dtb.fetch_hits                          0                       # ITB hits
+system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.read_accesses                  605265                       # DTB read accesses
 system.cpu0.dtb.read_acv                          596                       # DTB read access violations
 system.cpu0.dtb.read_hits                     7063685                       # DTB read hits
@@ -343,10 +347,22 @@ system.cpu0.iq.iqSquashedInstsExamined        5737873                       # Nu
 system.cpu0.iq.iqSquashedInstsIssued            23379                       # Number of squashed instructions issued
 system.cpu0.iq.iqSquashedNonSpecRemoved        939346                       # Number of squashed non-spec instructions that were removed
 system.cpu0.iq.iqSquashedOperandsExamined      3058467                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.itb.accesses                       875811                       # ITB accesses
-system.cpu0.itb.acv                               900                       # ITB acv
-system.cpu0.itb.hits                           845925                       # ITB hits
-system.cpu0.itb.misses                          29886                       # ITB misses
+system.cpu0.itb.data_accesses                       0                       # DTB accesses
+system.cpu0.itb.data_acv                            0                       # DTB access violations
+system.cpu0.itb.data_hits                           0                       # DTB hits
+system.cpu0.itb.data_misses                         0                       # DTB misses
+system.cpu0.itb.fetch_accesses                 875811                       # ITB accesses
+system.cpu0.itb.fetch_acv                         900                       # ITB acv
+system.cpu0.itb.fetch_hits                     845925                       # ITB hits
+system.cpu0.itb.fetch_misses                    29886                       # ITB misses
+system.cpu0.itb.read_accesses                       0                       # DTB read accesses
+system.cpu0.itb.read_acv                            0                       # DTB read access violations
+system.cpu0.itb.read_hits                           0                       # DTB read hits
+system.cpu0.itb.read_misses                         0                       # DTB read misses
+system.cpu0.itb.write_accesses                      0                       # DTB write accesses
+system.cpu0.itb.write_acv                           0                       # DTB write access violations
+system.cpu0.itb.write_hits                          0                       # DTB write hits
+system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.kern.callpal                       129578                       # number of callpals executed
 system.cpu0.kern.callpal_cserve                     1      0.00%      0.00% # number of callpals executed
 system.cpu0.kern.callpal_wripir                    96      0.07%      0.07% # number of callpals executed
@@ -596,10 +612,14 @@ system.cpu1.decode.DECODE:RunCycles           4724229                       # Nu
 system.cpu1.decode.DECODE:SquashCycles         641522                       # Number of cycles decode is squashing
 system.cpu1.decode.DECODE:SquashedInsts         52769                       # Number of squashed instructions handled by decode
 system.cpu1.decode.DECODE:UnblockCycles        232141                       # Number of cycles decode is unblocking
-system.cpu1.dtb.accesses                       433929                       # DTB accesses
-system.cpu1.dtb.acv                                77                       # DTB access violations
-system.cpu1.dtb.hits                          6280849                       # DTB hits
-system.cpu1.dtb.misses                          17153                       # DTB misses
+system.cpu1.dtb.data_accesses                  433929                       # DTB accesses
+system.cpu1.dtb.data_acv                           77                       # DTB access violations
+system.cpu1.dtb.data_hits                     6280849                       # DTB hits
+system.cpu1.dtb.data_misses                     17153                       # DTB misses
+system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu1.dtb.fetch_acv                           0                       # ITB acv
+system.cpu1.dtb.fetch_hits                          0                       # ITB hits
+system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.read_accesses                  314117                       # DTB read accesses
 system.cpu1.dtb.read_acv                           13                       # DTB read access violations
 system.cpu1.dtb.read_hits                     3872885                       # DTB read hits
@@ -793,10 +813,22 @@ system.cpu1.iq.iqSquashedInstsExamined        3483485                       # Nu
 system.cpu1.iq.iqSquashedInstsIssued            16725                       # Number of squashed instructions issued
 system.cpu1.iq.iqSquashedNonSpecRemoved        620822                       # Number of squashed non-spec instructions that were removed
 system.cpu1.iq.iqSquashedOperandsExamined      1773520                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.itb.accesses                       525294                       # ITB accesses
-system.cpu1.itb.acv                               109                       # ITB acv
-system.cpu1.itb.hits                           518481                       # ITB hits
-system.cpu1.itb.misses                           6813                       # ITB misses
+system.cpu1.itb.data_accesses                       0                       # DTB accesses
+system.cpu1.itb.data_acv                            0                       # DTB access violations
+system.cpu1.itb.data_hits                           0                       # DTB hits
+system.cpu1.itb.data_misses                         0                       # DTB misses
+system.cpu1.itb.fetch_accesses                 525294                       # ITB accesses
+system.cpu1.itb.fetch_acv                         109                       # ITB acv
+system.cpu1.itb.fetch_hits                     518481                       # ITB hits
+system.cpu1.itb.fetch_misses                     6813                       # ITB misses
+system.cpu1.itb.read_accesses                       0                       # DTB read accesses
+system.cpu1.itb.read_acv                            0                       # DTB read access violations
+system.cpu1.itb.read_hits                           0                       # DTB read hits
+system.cpu1.itb.read_misses                         0                       # DTB read misses
+system.cpu1.itb.write_accesses                      0                       # DTB write accesses
+system.cpu1.itb.write_acv                           0                       # DTB write access violations
+system.cpu1.itb.write_hits                          0                       # DTB write hits
+system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.kern.callpal                        87355                       # number of callpals executed
 system.cpu1.kern.callpal_cserve                     1      0.00%      0.00% # number of callpals executed
 system.cpu1.kern.callpal_wripir                    17      0.02%      0.02% # number of callpals executed
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
index c7a30cef6..ee39a929f 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
@@ -158,7 +158,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.toL2Bus.port[2]
 
 [system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu.fuPool]
@@ -334,7 +334,7 @@ mem_side=system.toL2Bus.port[1]
 type=AlphaInterrupts
 
 [system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu.tracer]
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
index 139f5f740..bb339ffda 100755
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar  6 2009 18:15:39
-M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
-M5 started Mar  6 2009 18:15:42
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:30:19
 M5 executing on maize
-command line: /n/blue/z/binkert/build/work/build/ALPHA_FS/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3
+command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
index 4534484ec..a49abde89 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 203131                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 294692                       # Number of bytes of host memory used
-host_seconds                                   261.36                       # Real time elapsed on the host
-host_tick_rate                             7144744614                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 201864                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 294704                       # Number of bytes of host memory used
+host_seconds                                   263.00                       # Real time elapsed on the host
+host_tick_rate                             7100171671                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    53090630                       # Number of instructions simulated
 sim_seconds                                  1.867363                       # Number of seconds simulated
@@ -146,10 +146,14 @@ system.cpu.decode.DECODE:RunCycles           13077120                       # Nu
 system.cpu.decode.DECODE:SquashCycles         1650418                       # Number of cycles decode is squashing
 system.cpu.decode.DECODE:SquashedInsts         134762                       # Number of squashed instructions handled by decode
 system.cpu.decode.DECODE:UnblockCycles        1151082                       # Number of cycles decode is unblocking
-system.cpu.dtb.accesses                       1236420                       # DTB accesses
-system.cpu.dtb.acv                                825                       # DTB access violations
-system.cpu.dtb.hits                          16772347                       # DTB hits
-system.cpu.dtb.misses                           44495                       # DTB misses
+system.cpu.dtb.data_accesses                  1236420                       # DTB accesses
+system.cpu.dtb.data_acv                           825                       # DTB access violations
+system.cpu.dtb.data_hits                     16772347                       # DTB hits
+system.cpu.dtb.data_misses                      44495                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                   910052                       # DTB read accesses
 system.cpu.dtb.read_acv                           586                       # DTB read access violations
 system.cpu.dtb.read_hits                     10174508                       # DTB read hits
@@ -343,10 +347,22 @@ system.cpu.iq.iqSquashedInstsExamined         8738375                       # Nu
 system.cpu.iq.iqSquashedInstsIssued             34584                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved        1383913                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined      4729371                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses                       1303895                       # ITB accesses
-system.cpu.itb.acv                                943                       # ITB acv
-system.cpu.itb.hits                           1264480                       # ITB hits
-system.cpu.itb.misses                           39415                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses                 1303895                       # ITB accesses
+system.cpu.itb.fetch_acv                          943                       # ITB acv
+system.cpu.itb.fetch_hits                     1264480                       # ITB hits
+system.cpu.itb.fetch_misses                     39415                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.kern.callpal                        192656                       # number of callpals executed
 system.cpu.kern.callpal_cserve                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal_wrmces                      1      0.00%      0.00% # number of callpals executed
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
index 3c2bf8020..93528e180 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
@@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
 icache_port=system.membus.port[1]
 
 [system.cpu.dtb]
-type=SparcDTB
+type=SparcTLB
 size=64
 
 [system.cpu.itb]
-type=SparcITB
+type=SparcTLB
 size=64
 
 [system.cpu.tracer]
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
index 6c41adbc1..772ffba43 100755
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:17:12
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:51:47
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py long/10.mcf/sparc/linux/simple-atomic
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:30:33
+M5 executing on maize
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
index a02166247..b6a29a98d 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2414989                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 329980                       # Number of bytes of host memory used
-host_seconds                                   100.97                       # Real time elapsed on the host
-host_tick_rate                             1210444801                       # Simulator tick rate (ticks/s)
+host_inst_rate                                3425998                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 331732                       # Number of bytes of host memory used
+host_seconds                                    71.17                       # Real time elapsed on the host
+host_tick_rate                             1717182841                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   243835278                       # Number of instructions simulated
 sim_seconds                                  0.122216                       # Number of seconds simulated
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
index 8066afd8e..ee3e7a244 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=SparcDTB
+type=SparcTLB
 size=64
 
 [system.cpu.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=SparcITB
+type=SparcTLB
 size=64
 
 [system.cpu.l2cache]
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
index b171def01..3e2f8211c 100755
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 16 2009 00:51:12
-M5 revision 208de84f046d 6013 default tip
-M5 started Mar 16 2009 00:51:29
-M5 executing on zizzer
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:30:42
+M5 executing on maize
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
index 1e841feab..1ac5ddac3 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1212571                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 337588                       # Number of bytes of host memory used
-host_seconds                                   201.09                       # Real time elapsed on the host
-host_tick_rate                             1822248337                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1860125                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 339272                       # Number of bytes of host memory used
+host_seconds                                   131.09                       # Real time elapsed on the host
+host_tick_rate                             2795388911                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   243835278                       # Number of instructions simulated
 sim_seconds                                  0.366435                       # Number of seconds simulated
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
index 640586f7b..75f4bc257 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
@@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
 icache_port=system.membus.port[1]
 
 [system.cpu.dtb]
-type=X86DTB
+type=X86TLB
 size=64
 
 [system.cpu.itb]
-type=X86ITB
+type=X86TLB
 size=64
 
 [system.cpu.tracer]
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
index b197a138a..2feff24bb 100755
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 23 2009 23:45:19
-M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch
-M5 started Feb 23 2009 23:48:10
-M5 executing on tater
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py long/10.mcf/x86/linux/simple-atomic
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 13:07:56
+M5 executing on maize
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
index 412b43cf4..955d0c3ba 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 738696                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 331676                       # Number of bytes of host memory used
-host_seconds                                   365.09                       # Real time elapsed on the host
-host_tick_rate                              451120089                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2496453                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 334252                       # Number of bytes of host memory used
+host_seconds                                   108.03                       # Real time elapsed on the host
+host_tick_rate                             1524575559                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   269686773                       # Number of instructions simulated
 sim_seconds                                  0.164697                       # Number of seconds simulated
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
index c34572b5c..fc66ed40b 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=X86DTB
+type=X86TLB
 size=64
 
 [system.cpu.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=X86ITB
+type=X86TLB
 size=64
 
 [system.cpu.l2cache]
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout
index 160928f1d..2f53f3c01 100755
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 24 2009 01:30:29
-M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch
-M5 started Feb 24 2009 01:36:40
-M5 executing on tater
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py long/10.mcf/x86/linux/simple-timing
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:50:00
+M5 executing on maize
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
index cc9d82b6a..73615cc93 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 587866                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 339232                       # Number of bytes of host memory used
-host_seconds                                   458.76                       # Real time elapsed on the host
-host_tick_rate                              831860032                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1552325                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 341792                       # Number of bytes of host memory used
+host_seconds                                   173.73                       # Real time elapsed on the host
+host_tick_rate                             2196615579                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   269686773                       # Number of instructions simulated
 sim_seconds                                  0.381620                       # Number of seconds simulated
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
index dd5474f9a..5b5021cae 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
@@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
 icache_port=system.membus.port[1]
 
 [system.cpu.dtb]
-type=X86DTB
+type=X86TLB
 size=64
 
 [system.cpu.itb]
-type=X86ITB
+type=X86TLB
 size=64
 
 [system.cpu.tracer]
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout
index 6f49cefcf..4cc446c6f 100755
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 23 2009 23:45:19
-M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch
-M5 started Feb 23 2009 23:48:10
-M5 executing on tater
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py long/20.parser/x86/linux/simple-atomic
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:52:55
+M5 executing on maize
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
index a32bcd78e..4ce9ac1a4 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 954040                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 200820                       # Number of bytes of host memory used
-host_seconds                                  1567.53                       # Real time elapsed on the host
-host_tick_rate                              554042856                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2610049                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 203408                       # Number of bytes of host memory used
+host_seconds                                   572.97                       # Real time elapsed on the host
+host_tick_rate                             1515741316                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1495482356                       # Number of instructions simulated
 sim_seconds                                  0.868476                       # Number of seconds simulated
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
index 87163bbc2..d9d78b96d 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=X86DTB
+type=X86TLB
 size=64
 
 [system.cpu.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=X86ITB
+type=X86TLB
 size=64
 
 [system.cpu.l2cache]
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout
index e9b88174e..bbd611598 100755
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 24 2009 01:30:29
-M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch
-M5 started Feb 24 2009 01:46:46
-M5 executing on tater
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py long/20.parser/x86/linux/simple-timing
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:55:56
+M5 executing on maize
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
index 422faa1c9..458dc4744 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 782704                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 208376                       # Number of bytes of host memory used
-host_seconds                                  1910.66                       # Real time elapsed on the host
-host_tick_rate                              901442913                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1776301                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 210956                       # Number of bytes of host memory used
+host_seconds                                   841.91                       # Real time elapsed on the host
+host_tick_rate                             2045771672                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1495482356                       # Number of instructions simulated
 sim_seconds                                  1.722352                       # Number of seconds simulated
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
index 253ff4370..e8b0d97b4 100644
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
@@ -132,7 +132,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu.fuPool]
@@ -305,7 +305,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu.l2cache]
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
index d243310c6..cebbf9144 100755
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar  6 2009 18:15:46
-M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
-M5 started Mar  6 2009 18:25:10
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:46:50
 M5 executing on maize
-command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py long/30.eon/alpha/tru64/o3-timing
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
index 5e076a275..1ba62881c 100644
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 243217                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 213460                       # Number of bytes of host memory used
-host_seconds                                  1544.20                       # Real time elapsed on the host
-host_tick_rate                               87422028                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 244825                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 213432                       # Number of bytes of host memory used
+host_seconds                                  1534.05                       # Real time elapsed on the host
+host_tick_rate                               88000012                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   375574819                       # Number of instructions simulated
 sim_seconds                                  0.134997                       # Number of seconds simulated
@@ -123,10 +123,14 @@ system.cpu.decode.DECODE:RunCycles          101952317                       # Nu
 system.cpu.decode.DECODE:SquashCycles        15306974                       # Number of cycles decode is squashing
 system.cpu.decode.DECODE:SquashedInsts          12561                       # Number of squashed instructions handled by decode
 system.cpu.decode.DECODE:UnblockCycles        1275127                       # Number of cycles decode is unblocking
-system.cpu.dtb.accesses                     185115437                       # DTB accesses
-system.cpu.dtb.acv                                  1                       # DTB access violations
-system.cpu.dtb.hits                         185076670                       # DTB hits
-system.cpu.dtb.misses                           38767                       # DTB misses
+system.cpu.dtb.data_accesses                185115437                       # DTB accesses
+system.cpu.dtb.data_acv                             1                       # DTB access violations
+system.cpu.dtb.data_hits                    185076670                       # DTB hits
+system.cpu.dtb.data_misses                      38767                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                104449499                       # DTB read accesses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
 system.cpu.dtb.read_hits                    104412186                       # DTB read hits
@@ -319,10 +323,22 @@ system.cpu.iq.iqSquashedInstsExamined        89615992                       # Nu
 system.cpu.iq.iqSquashedInstsIssued            918381                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved             24                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined     68228113                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses                      63866476                       # ITB accesses
-system.cpu.itb.acv                                  0                       # ITB acv
-system.cpu.itb.hits                          63866189                       # ITB hits
-system.cpu.itb.misses                             287                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses                63866476                       # ITB accesses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_hits                    63866189                       # ITB hits
+system.cpu.itb.fetch_misses                       287                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.l2cache.ReadExReq_accesses            3197                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency 34596.340006                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31467.625899                       # average ReadExReq mshr miss latency
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
index b219ea49a..193b9744b 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
@@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
 icache_port=system.membus.port[1]
 
 [system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu.tracer]
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
index 320d9365d..5cd2ed646 100755
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:27:51
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py long/30.eon/alpha/tru64/simple-atomic
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:41:56
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
index f57fc8170..09b41faf1 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,17 +1,21 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                3515833                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 203260                       # Number of bytes of host memory used
-host_seconds                                   113.39                       # Real time elapsed on the host
-host_tick_rate                             1757913715                       # Simulator tick rate (ticks/s)
+host_inst_rate                                5193663                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 205028                       # Number of bytes of host memory used
+host_seconds                                    76.76                       # Real time elapsed on the host
+host_tick_rate                             2596825201                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   398664595                       # Number of instructions simulated
 sim_seconds                                  0.199332                       # Number of seconds simulated
 sim_ticks                                199332411500                       # Number of ticks simulated
-system.cpu.dtb.accesses                     168275274                       # DTB accesses
-system.cpu.dtb.acv                                  0                       # DTB access violations
-system.cpu.dtb.hits                         168275218                       # DTB hits
-system.cpu.dtb.misses                              56                       # DTB misses
+system.cpu.dtb.data_accesses                168275274                       # DTB accesses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_hits                    168275218                       # DTB hits
+system.cpu.dtb.data_misses                         56                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                 94754510                       # DTB read accesses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
 system.cpu.dtb.read_hits                     94754489                       # DTB read hits
@@ -21,10 +25,22 @@ system.cpu.dtb.write_acv                            0                       # DT
 system.cpu.dtb.write_hits                    73520729                       # DTB write hits
 system.cpu.dtb.write_misses                        35                       # DTB write misses
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                     398664824                       # ITB accesses
-system.cpu.itb.acv                                  0                       # ITB acv
-system.cpu.itb.hits                         398664651                       # ITB hits
-system.cpu.itb.misses                             173                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses               398664824                       # ITB accesses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_hits                   398664651                       # ITB hits
+system.cpu.itb.fetch_misses                       173                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                        398664824                       # number of cpu cycles simulated
 system.cpu.num_insts                        398664595                       # Number of instructions executed
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
index 86203bb88..6bb84f209 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu.l2cache]
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
index 3eda1fae9..15ed4127f 100755
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:27:52
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re tests/run.py long/30.eon/alpha/tru64/simple-timing
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:44:12
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
index 56640f3eb..64814b26f 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1674592                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 210700                       # Number of bytes of host memory used
-host_seconds                                   238.07                       # Real time elapsed on the host
-host_tick_rate                             2383160323                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2545334                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 212560                       # Number of bytes of host memory used
+host_seconds                                   156.63                       # Real time elapsed on the host
+host_tick_rate                             3622337158                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   398664609                       # Number of instructions simulated
 sim_seconds                                  0.567352                       # Number of seconds simulated
@@ -71,10 +71,14 @@ system.cpu.dcache.tagsinuse               3288.899192                       # Cy
 system.cpu.dcache.total_refs                168271068                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                      625                       # number of writebacks
-system.cpu.dtb.accesses                     168275276                       # DTB accesses
-system.cpu.dtb.acv                                  0                       # DTB access violations
-system.cpu.dtb.hits                         168275220                       # DTB hits
-system.cpu.dtb.misses                              56                       # DTB misses
+system.cpu.dtb.data_accesses                168275276                       # DTB accesses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_hits                    168275220                       # DTB hits
+system.cpu.dtb.data_misses                         56                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                 94754511                       # DTB read accesses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
 system.cpu.dtb.read_hits                     94754490                       # DTB read hits
@@ -137,10 +141,22 @@ system.cpu.icache.total_refs                398660993                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                     398664839                       # ITB accesses
-system.cpu.itb.acv                                  0                       # ITB acv
-system.cpu.itb.hits                         398664666                       # ITB hits
-system.cpu.itb.misses                             173                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses               398664839                       # ITB accesses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_hits                   398664666                       # ITB hits
+system.cpu.itb.fetch_misses                       173                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.l2cache.ReadExReq_accesses            3202                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
index 2eb72fecc..c9c4bd8a4 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
@@ -132,7 +132,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu.fuPool]
@@ -305,7 +305,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu.l2cache]
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
index 3ec2c9e61..2c39c411e 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar  6 2009 18:15:46
-M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
-M5 started Mar  6 2009 18:24:11
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:41:37
 M5 executing on maize
-command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py long/40.perlbmk/alpha/tru64/o3-timing
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
index 655e48f3b..4f72e1349 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 233158                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 213372                       # Number of bytes of host memory used
-host_seconds                                  7818.92                       # Real time elapsed on the host
-host_tick_rate                               90186298                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 236247                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 213344                       # Number of bytes of host memory used
+host_seconds                                  7716.70                       # Real time elapsed on the host
+host_tick_rate                               91380999                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1823043370                       # Number of instructions simulated
 sim_seconds                                  0.705159                       # Number of seconds simulated
@@ -123,10 +123,14 @@ system.cpu.decode.DECODE:RunCycles          561391036                       # Nu
 system.cpu.decode.DECODE:SquashCycles       100159084                       # Number of cycles decode is squashing
 system.cpu.decode.DECODE:SquashedInsts          45706                       # Number of squashed instructions handled by decode
 system.cpu.decode.DECODE:UnblockCycles          83764                       # Number of cycles decode is unblocking
-system.cpu.dtb.accesses                     775959987                       # DTB accesses
-system.cpu.dtb.acv                                  0                       # DTB access violations
-system.cpu.dtb.hits                         775335043                       # DTB hits
-system.cpu.dtb.misses                          624944                       # DTB misses
+system.cpu.dtb.data_accesses                775959987                       # DTB accesses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_hits                    775335043                       # DTB hits
+system.cpu.dtb.data_misses                     624944                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                516992085                       # DTB read accesses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
 system.cpu.dtb.read_hits                    516404963                       # DTB read hits
@@ -319,10 +323,22 @@ system.cpu.iq.iqSquashedInstsExamined       562621267                       # Nu
 system.cpu.iq.iqSquashedInstsIssued          12403599                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved             18                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined    516017454                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses                     348448092                       # ITB accesses
-system.cpu.itb.acv                                  0                       # ITB acv
-system.cpu.itb.hits                         348447899                       # ITB hits
-system.cpu.itb.misses                             193                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses               348448092                       # ITB accesses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_hits                   348447899                       # ITB hits
+system.cpu.itb.fetch_misses                       193                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.l2cache.ReadExReq_accesses           71650                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency 35090.990928                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32065.847872                       # average ReadExReq mshr miss latency
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
index 4863763a5..d69895fd2 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
@@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
 icache_port=system.membus.port[1]
 
 [system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu.tracer]
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
index 3e0584ae3..c197c46fb 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:27:51
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py long/40.perlbmk/alpha/tru64/simple-atomic
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:38:04
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
index a2839e9d4..ebae3bb0f 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,17 +1,21 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                3467416                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 202428                       # Number of bytes of host memory used
-host_seconds                                   579.39                       # Real time elapsed on the host
-host_tick_rate                             1734081372                       # Simulator tick rate (ticks/s)
+host_inst_rate                                5314394                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 204196                       # Number of bytes of host memory used
+host_seconds                                   378.03                       # Real time elapsed on the host
+host_tick_rate                             2657768720                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  2008987605                       # Number of instructions simulated
 sim_seconds                                  1.004711                       # Number of seconds simulated
 sim_ticks                                1004710587000                       # Number of ticks simulated
-system.cpu.dtb.accesses                     722298387                       # DTB accesses
-system.cpu.dtb.acv                                  0                       # DTB access violations
-system.cpu.dtb.hits                         721864922                       # DTB hits
-system.cpu.dtb.misses                          433465                       # DTB misses
+system.cpu.dtb.data_accesses                722298387                       # DTB accesses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_hits                    721864922                       # DTB hits
+system.cpu.dtb.data_misses                     433465                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                511488910                       # DTB read accesses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
 system.cpu.dtb.read_hits                    511070026                       # DTB read hits
@@ -21,10 +25,22 @@ system.cpu.dtb.write_acv                            0                       # DT
 system.cpu.dtb.write_hits                   210794896                       # DTB write hits
 system.cpu.dtb.write_misses                     14581                       # DTB write misses
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                    2009421175                       # ITB accesses
-system.cpu.itb.acv                                  0                       # ITB acv
-system.cpu.itb.hits                        2009421070                       # ITB hits
-system.cpu.itb.misses                             105                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses              2009421175                       # ITB accesses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_hits                  2009421070                       # ITB hits
+system.cpu.itb.fetch_misses                       105                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                       2009421175                       # number of cpu cycles simulated
 system.cpu.num_insts                       2008987605                       # Number of instructions executed
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
index a7ffe8cab..8c5285f82 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu.l2cache]
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
index bfb6dafd6..cdafa0ab2 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:29:29
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py long/40.perlbmk/alpha/tru64/simple-timing
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:45:29
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
index 87861b454..4c7aa8469 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2199489                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 209876                       # Number of bytes of host memory used
-host_seconds                                   913.39                       # Real time elapsed on the host
-host_tick_rate                             3081877276                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2595694                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 211736                       # Number of bytes of host memory used
+host_seconds                                   773.97                       # Real time elapsed on the host
+host_tick_rate                             3637030411                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  2008987605                       # Number of instructions simulated
 sim_seconds                                  2.814951                       # Number of seconds simulated
@@ -71,10 +71,14 @@ system.cpu.dcache.tagsinuse               4095.198740                       # Cy
 system.cpu.dcache.total_refs                720334778                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle             1054514000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                    74589                       # number of writebacks
-system.cpu.dtb.accesses                     722298387                       # DTB accesses
-system.cpu.dtb.acv                                  0                       # DTB access violations
-system.cpu.dtb.hits                         721864922                       # DTB hits
-system.cpu.dtb.misses                          433465                       # DTB misses
+system.cpu.dtb.data_accesses                722298387                       # DTB accesses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_hits                    721864922                       # DTB hits
+system.cpu.dtb.data_misses                     433465                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                511488910                       # DTB read accesses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
 system.cpu.dtb.read_hits                    511070026                       # DTB read hits
@@ -137,10 +141,22 @@ system.cpu.icache.total_refs               2009410475                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                    2009421176                       # ITB accesses
-system.cpu.itb.acv                                  0                       # ITB acv
-system.cpu.itb.hits                        2009421071                       # ITB hits
-system.cpu.itb.misses                             105                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses              2009421176                       # ITB accesses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_hits                  2009421071                       # ITB hits
+system.cpu.itb.fetch_misses                       105                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.l2cache.ReadExReq_accesses           71952                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
index 2927f396f..bf2f959df 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
@@ -132,7 +132,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu.fuPool]
@@ -305,7 +305,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu.l2cache]
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
index 3c4f7e5f4..dc258abe3 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar  6 2009 18:15:46
-M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
-M5 started Mar  6 2009 18:23:18
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:36:30
 M5 executing on maize
-command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py long/50.vortex/alpha/tru64/o3-timing
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index c3cb349a5..9dcaad468 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 261905                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 216920                       # Number of bytes of host memory used
-host_seconds                                   303.90                       # Real time elapsed on the host
-host_tick_rate                               89289765                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 259851                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 216888                       # Number of bytes of host memory used
+host_seconds                                   306.30                       # Real time elapsed on the host
+host_tick_rate                               88589448                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    79591756                       # Number of instructions simulated
 sim_seconds                                  0.027135                       # Number of seconds simulated
@@ -123,10 +123,14 @@ system.cpu.decode.DECODE:RunCycles           19520694                       # Nu
 system.cpu.decode.DECODE:SquashCycles         1290101                       # Number of cycles decode is squashing
 system.cpu.decode.DECODE:SquashedInsts         284696                       # Number of squashed instructions handled by decode
 system.cpu.decode.DECODE:UnblockCycles         144719                       # Number of cycles decode is unblocking
-system.cpu.dtb.accesses                      36599689                       # DTB accesses
-system.cpu.dtb.acv                                 39                       # DTB access violations
-system.cpu.dtb.hits                          36425481                       # DTB hits
-system.cpu.dtb.misses                          174208                       # DTB misses
+system.cpu.dtb.data_accesses                 36599689                       # DTB accesses
+system.cpu.dtb.data_acv                            39                       # DTB access violations
+system.cpu.dtb.data_hits                     36425481                       # DTB hits
+system.cpu.dtb.data_misses                     174208                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                 21541288                       # DTB read accesses
 system.cpu.dtb.read_acv                            37                       # DTB read access violations
 system.cpu.dtb.read_hits                     21383020                       # DTB read hits
@@ -319,10 +323,22 @@ system.cpu.iq.iqSquashedInstsExamined         9777311                       # Nu
 system.cpu.iq.iqSquashedInstsIssued             49841                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved            421                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined      6793875                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses                      13412237                       # ITB accesses
-system.cpu.itb.acv                                  0                       # ITB acv
-system.cpu.itb.hits                          13386072                       # ITB hits
-system.cpu.itb.misses                           26165                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses                13412237                       # ITB accesses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_hits                    13386072                       # ITB hits
+system.cpu.itb.fetch_misses                     26165                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.l2cache.ReadExReq_accesses          143494                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency 34337.379953                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31233.455754                       # average ReadExReq mshr miss latency
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
index 5a410e8c9..31e1868d0 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
@@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
 icache_port=system.membus.port[1]
 
 [system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu.tracer]
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
index 7f58d408c..cac080f34 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:31:50
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py long/50.vortex/alpha/tru64/simple-atomic
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:43:53
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
index 3b23e3386..25afd1229 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,17 +1,21 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                5386925                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 205832                       # Number of bytes of host memory used
-host_seconds                                    16.40                       # Real time elapsed on the host
-host_tick_rate                             2696520513                       # Simulator tick rate (ticks/s)
+host_inst_rate                                5274353                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 207596                       # Number of bytes of host memory used
+host_seconds                                    16.75                       # Real time elapsed on the host
+host_tick_rate                             2640164541                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_seconds                                  0.044221                       # Number of seconds simulated
 sim_ticks                                 44221003000                       # Number of ticks simulated
-system.cpu.dtb.accesses                      34987415                       # DTB accesses
-system.cpu.dtb.acv                                  0                       # DTB access violations
-system.cpu.dtb.hits                          34890015                       # DTB hits
-system.cpu.dtb.misses                           97400                       # DTB misses
+system.cpu.dtb.data_accesses                 34987415                       # DTB accesses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_hits                     34890015                       # DTB hits
+system.cpu.dtb.data_misses                      97400                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                 20366786                       # DTB read accesses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
 system.cpu.dtb.read_hits                     20276638                       # DTB read hits
@@ -21,10 +25,22 @@ system.cpu.dtb.write_acv                            0                       # DT
 system.cpu.dtb.write_hits                    14613377                       # DTB write hits
 system.cpu.dtb.write_misses                      7252                       # DTB write misses
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                      88442007                       # ITB accesses
-system.cpu.itb.acv                                  0                       # ITB acv
-system.cpu.itb.hits                          88438073                       # ITB hits
-system.cpu.itb.misses                            3934                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses                88442007                       # ITB accesses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_hits                    88438073                       # ITB hits
+system.cpu.itb.fetch_misses                      3934                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                         88442007                       # number of cpu cycles simulated
 system.cpu.num_insts                         88340673                       # Number of instructions executed
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
index 74756cd76..bec56725b 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu.l2cache]
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
index 9806a0cdd..621e65c84 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:32:07
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py long/50.vortex/alpha/tru64/simple-timing
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:30:03
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
index 66817a603..a690b2e36 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2514121                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 213276                       # Number of bytes of host memory used
-host_seconds                                    35.14                       # Real time elapsed on the host
-host_tick_rate                             3846798027                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2447162                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 215136                       # Number of bytes of host memory used
+host_seconds                                    36.10                       # Real time elapsed on the host
+host_tick_rate                             3744340356                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_seconds                                  0.135169                       # Number of seconds simulated
@@ -71,10 +71,14 @@ system.cpu.dcache.tagsinuse               4078.872537                       # Cy
 system.cpu.dcache.total_refs                 34685671                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              947635000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                   147714                       # number of writebacks
-system.cpu.dtb.accesses                      34987415                       # DTB accesses
-system.cpu.dtb.acv                                  0                       # DTB access violations
-system.cpu.dtb.hits                          34890015                       # DTB hits
-system.cpu.dtb.misses                           97400                       # DTB misses
+system.cpu.dtb.data_accesses                 34987415                       # DTB accesses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_hits                     34890015                       # DTB hits
+system.cpu.dtb.data_misses                      97400                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                 20366786                       # DTB read accesses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
 system.cpu.dtb.read_hits                     20276638                       # DTB read hits
@@ -137,10 +141,22 @@ system.cpu.icache.total_refs                 88361638                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                      88442008                       # ITB accesses
-system.cpu.itb.acv                                  0                       # ITB acv
-system.cpu.itb.hits                          88438074                       # ITB hits
-system.cpu.itb.misses                            3934                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses                88442008                       # ITB accesses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_hits                    88438074                       # ITB hits
+system.cpu.itb.fetch_misses                      3934                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.l2cache.ReadExReq_accesses          143578                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
index 5b764e1f0..f0c5c3a9b 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
@@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
 icache_port=system.membus.port[1]
 
 [system.cpu.dtb]
-type=SparcDTB
+type=SparcTLB
 size=64
 
 [system.cpu.itb]
-type=SparcITB
+type=SparcTLB
 size=64
 
 [system.cpu.tracer]
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
index 95b7d967f..9f2f0d730 100755
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:17:12
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:53:28
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py long/50.vortex/sparc/linux/simple-atomic
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:31:45
+M5 executing on maize
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
index be8f1d320..3f55620e8 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                3821272                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 206688                       # Number of bytes of host memory used
-host_seconds                                    35.63                       # Real time elapsed on the host
-host_tick_rate                             1912846403                       # Simulator tick rate (ticks/s)
+host_inst_rate                                3453262                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 208432                       # Number of bytes of host memory used
+host_seconds                                    39.42                       # Real time elapsed on the host
+host_tick_rate                             1728626295                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   136139203                       # Number of instructions simulated
 sim_seconds                                  0.068149                       # Number of seconds simulated
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
index 4e4bcb117..05ad8a083 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=SparcDTB
+type=SparcTLB
 size=64
 
 [system.cpu.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=SparcITB
+type=SparcTLB
 size=64
 
 [system.cpu.l2cache]
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
index 397f2cd80..dcc6d4681 100755
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 16 2009 00:51:12
-M5 revision 208de84f046d 6013 default tip
-M5 started Mar 16 2009 00:51:29
-M5 executing on zizzer
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:30:34
+M5 executing on maize
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
index 24dff0498..16a33a02d 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1347607                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 214288                       # Number of bytes of host memory used
-host_seconds                                   101.02                       # Real time elapsed on the host
-host_tick_rate                             2013168641                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1887759                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 215972                       # Number of bytes of host memory used
+host_seconds                                    72.12                       # Real time elapsed on the host
+host_tick_rate                             2820090693                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   136139203                       # Number of instructions simulated
 sim_seconds                                  0.203377                       # Number of seconds simulated
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
index 7014f9608..c5cc148d0 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
@@ -132,7 +132,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu.fuPool]
@@ -305,7 +305,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu.l2cache]
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
index 644c3eb5c..e092c3b04 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar  6 2009 18:15:46
-M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
-M5 started Mar  6 2009 18:18:05
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:33:27
 M5 executing on maize
-command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py long/60.bzip2/alpha/tru64/o3-timing
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
index 16f472fdf..3fa048f88 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 226973                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 205820                       # Number of bytes of host memory used
-host_seconds                                  7648.67                       # Real time elapsed on the host
-host_tick_rate                               97050740                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 226919                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 205788                       # Number of bytes of host memory used
+host_seconds                                  7650.48                       # Real time elapsed on the host
+host_tick_rate                               97027777                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1736043781                       # Number of instructions simulated
 sim_seconds                                  0.742309                       # Number of seconds simulated
@@ -131,10 +131,14 @@ system.cpu.decode.DECODE:RunCycles          549143104                       # Nu
 system.cpu.decode.DECODE:SquashCycles        93084202                       # Number of cycles decode is squashing
 system.cpu.decode.DECODE:SquashedInsts           1641                       # Number of squashed instructions handled by decode
 system.cpu.decode.DECODE:UnblockCycles        5133136                       # Number of cycles decode is unblocking
-system.cpu.dtb.accesses                     768331639                       # DTB accesses
-system.cpu.dtb.acv                                  0                       # DTB access violations
-system.cpu.dtb.hits                         752318838                       # DTB hits
-system.cpu.dtb.misses                        16012801                       # DTB misses
+system.cpu.dtb.data_accesses                768331639                       # DTB accesses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_hits                    752318838                       # DTB hits
+system.cpu.dtb.data_misses                   16012801                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                566617551                       # DTB read accesses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
 system.cpu.dtb.read_hits                    557381525                       # DTB read hits
@@ -327,10 +331,22 @@ system.cpu.iq.iqSquashedInstsExamined       739697610                       # Nu
 system.cpu.iq.iqSquashedInstsIssued           1501741                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved             14                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined    329349456                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses                     355180552                       # ITB accesses
-system.cpu.itb.acv                                  0                       # ITB acv
-system.cpu.itb.hits                         355180518                       # ITB hits
-system.cpu.itb.misses                              34                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses               355180552                       # ITB accesses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_hits                   355180518                       # ITB hits
+system.cpu.itb.fetch_misses                        34                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.l2cache.ReadExReq_accesses         1884731                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency 34610.251241                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31460.593787                       # average ReadExReq mshr miss latency
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
index 0a457f545..4a349e817 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
@@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
 icache_port=system.membus.port[1]
 
 [system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu.tracer]
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout
index 6942bb9c6..1fd03182d 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:32:58
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py long/60.bzip2/alpha/tru64/simple-atomic
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:44:24
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
index 8b9cdfecf..7215f3f82 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,17 +1,21 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                3629734                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 195600                       # Number of bytes of host memory used
-host_seconds                                   501.35                       # Real time elapsed on the host
-host_tick_rate                             1821446907                       # Simulator tick rate (ticks/s)
+host_inst_rate                                5417867                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 197364                       # Number of bytes of host memory used
+host_seconds                                   335.89                       # Real time elapsed on the host
+host_tick_rate                             2718753958                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_seconds                                  0.913189                       # Number of seconds simulated
 sim_ticks                                913189263000                       # Number of ticks simulated
-system.cpu.dtb.accesses                     611922547                       # DTB accesses
-system.cpu.dtb.acv                                  0                       # DTB access violations
-system.cpu.dtb.hits                         605324165                       # DTB hits
-system.cpu.dtb.misses                         6598382                       # DTB misses
+system.cpu.dtb.data_accesses                611922547                       # DTB accesses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_hits                    605324165                       # DTB hits
+system.cpu.dtb.data_misses                    6598382                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                449492741                       # DTB read accesses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
 system.cpu.dtb.read_hits                    444595663                       # DTB read hits
@@ -21,10 +25,22 @@ system.cpu.dtb.write_acv                            0                       # DT
 system.cpu.dtb.write_hits                   160728502                       # DTB write hits
 system.cpu.dtb.write_misses                   1701304                       # DTB write misses
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                    1826378527                       # ITB accesses
-system.cpu.itb.acv                                  0                       # ITB acv
-system.cpu.itb.hits                        1826378509                       # ITB hits
-system.cpu.itb.misses                              18                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses              1826378527                       # ITB accesses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_hits                  1826378509                       # ITB hits
+system.cpu.itb.fetch_misses                        18                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                       1826378527                       # number of cpu cycles simulated
 system.cpu.num_insts                       1819780127                       # Number of instructions executed
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
index c29e7b8cc..f8a290050 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu.l2cache]
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
index 2a7a491ad..a3ccdd7b3 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:36:09
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py long/60.bzip2/alpha/tru64/simple-timing
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:43:13
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
index b4009b3e6..6127ea9b9 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2148631                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 203048                       # Number of bytes of host memory used
-host_seconds                                   846.95                       # Real time elapsed on the host
-host_tick_rate                             3220962828                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2385042                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 204904                       # Number of bytes of host memory used
+host_seconds                                   763.00                       # Real time elapsed on the host
+host_tick_rate                             3575360927                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_seconds                                  2.727991                       # Number of seconds simulated
@@ -71,10 +71,14 @@ system.cpu.dcache.tagsinuse               4079.892573                       # Cy
 system.cpu.dcache.total_refs                596212431                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle            40991470000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                  2244708                       # number of writebacks
-system.cpu.dtb.accesses                     611922547                       # DTB accesses
-system.cpu.dtb.acv                                  0                       # DTB access violations
-system.cpu.dtb.hits                         605324165                       # DTB hits
-system.cpu.dtb.misses                         6598382                       # DTB misses
+system.cpu.dtb.data_accesses                611922547                       # DTB accesses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_hits                    605324165                       # DTB hits
+system.cpu.dtb.data_misses                    6598382                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                449492741                       # DTB read accesses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
 system.cpu.dtb.read_hits                    444595663                       # DTB read hits
@@ -137,10 +141,22 @@ system.cpu.icache.total_refs               1826377708                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                    1826378528                       # ITB accesses
-system.cpu.itb.acv                                  0                       # ITB acv
-system.cpu.itb.hits                        1826378510                       # ITB hits
-system.cpu.itb.misses                              18                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses              1826378528                       # ITB accesses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_hits                  1826378510                       # ITB hits
+system.cpu.itb.fetch_misses                        18                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.l2cache.ReadExReq_accesses         1889320                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini
index 5ffe1d191..8cd09b7fa 100644
--- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini
@@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
 icache_port=system.membus.port[1]
 
 [system.cpu.dtb]
-type=X86DTB
+type=X86TLB
 size=64
 
 [system.cpu.itb]
-type=X86ITB
+type=X86TLB
 size=64
 
 [system.cpu.tracer]
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout
index 66e6ec11e..8766090d3 100755
--- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 23 2009 23:45:19
-M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch
-M5 started Feb 23 2009 23:48:10
-M5 executing on tater
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py long/60.bzip2/x86/linux/simple-atomic
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 13:09:24
+M5 executing on maize
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
index a2ce3d743..051f5b326 100644
--- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1367500                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 197040                       # Number of bytes of host memory used
-host_seconds                                  3402.69                       # Real time elapsed on the host
-host_tick_rate                              831449663                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2554726                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 199616                       # Number of bytes of host memory used
+host_seconds                                  1821.40                       # Real time elapsed on the host
+host_tick_rate                             1553291459                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  4653176258                       # Number of instructions simulated
 sim_seconds                                  2.829164                       # Number of seconds simulated
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini
index 4d80734e6..8499b0423 100644
--- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=X86DTB
+type=X86TLB
 size=64
 
 [system.cpu.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=X86ITB
+type=X86TLB
 size=64
 
 [system.cpu.l2cache]
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout
index bdea83ec4..0d8772663 100755
--- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 24 2009 01:30:29
-M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch
-M5 started Feb 24 2009 01:30:32
-M5 executing on tater
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py long/60.bzip2/x86/linux/simple-timing
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 13:02:28
+M5 executing on maize
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt
index 55231f8a8..bca5f9f6d 100644
--- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 929786                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 204596                       # Number of bytes of host memory used
-host_seconds                                  5004.56                       # Real time elapsed on the host
-host_tick_rate                             1196520405                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1632111                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 207156                       # Number of bytes of host memory used
+host_seconds                                  2851.02                       # Real time elapsed on the host
+host_tick_rate                             2100325473                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  4653176258                       # Number of instructions simulated
 sim_seconds                                  5.988064                       # Number of seconds simulated
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
index 6fbd6e595..6e7be67dd 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
@@ -132,7 +132,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu.fuPool]
@@ -305,7 +305,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu.l2cache]
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
index 4f595ede7..dfd4eec8c 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar  6 2009 18:15:46
-M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
-M5 started Mar  6 2009 18:16:08
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:37:03
 M5 executing on maize
-command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py long/70.twolf/alpha/tru64/o3-timing
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index 21c5777d8..e30cf0c3d 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 205423                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 211084                       # Number of bytes of host memory used
-host_seconds                                   409.79                       # Real time elapsed on the host
-host_tick_rate                               99609545                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 205890                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 211060                       # Number of bytes of host memory used
+host_seconds                                   408.86                       # Real time elapsed on the host
+host_tick_rate                               99836021                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    84179709                       # Number of instructions simulated
 sim_seconds                                  0.040819                       # Number of seconds simulated
@@ -123,10 +123,14 @@ system.cpu.decode.DECODE:RunCycles           29917869                       # Nu
 system.cpu.decode.DECODE:SquashCycles         8071146                       # Number of cycles decode is squashing
 system.cpu.decode.DECODE:SquashedInsts          45156                       # Number of squashed instructions handled by decode
 system.cpu.decode.DECODE:UnblockCycles         189170                       # Number of cycles decode is unblocking
-system.cpu.dtb.accesses                      31911121                       # DTB accesses
-system.cpu.dtb.acv                                  0                       # DTB access violations
-system.cpu.dtb.hits                          31454022                       # DTB hits
-system.cpu.dtb.misses                          457099                       # DTB misses
+system.cpu.dtb.data_accesses                 31911121                       # DTB accesses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_hits                     31454022                       # DTB hits
+system.cpu.dtb.data_misses                     457099                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                 24718123                       # DTB read accesses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
 system.cpu.dtb.read_hits                     24262026                       # DTB read hits
@@ -319,10 +323,22 @@ system.cpu.iq.iqSquashedInstsExamined        50669408                       # Nu
 system.cpu.iq.iqSquashedInstsIssued            244059                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved             37                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined     47385393                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses                      19230073                       # ITB accesses
-system.cpu.itb.acv                                  0                       # ITB acv
-system.cpu.itb.hits                          19230003                       # ITB hits
-system.cpu.itb.misses                              70                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses                19230073                       # ITB accesses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_hits                    19230003                       # ITB hits
+system.cpu.itb.fetch_misses                        70                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.l2cache.ReadExReq_accesses            1735                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency 34685.302594                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31521.902017                       # average ReadExReq mshr miss latency
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
index 593992332..1107790b1 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
@@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
 icache_port=system.membus.port[1]
 
 [system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu.tracer]
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout
index d3d15e406..68a75cbd9 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:41:19
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py long/70.twolf/alpha/tru64/simple-atomic
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:36:46
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
index bce09d7dd..bf89ff397 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,17 +1,21 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                5743124                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 200524                       # Number of bytes of host memory used
-host_seconds                                    16.00                       # Real time elapsed on the host
-host_tick_rate                             2871531471                       # Simulator tick rate (ticks/s)
+host_inst_rate                                5529646                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 202292                       # Number of bytes of host memory used
+host_seconds                                    16.62                       # Real time elapsed on the host
+host_tick_rate                             2764786682                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_seconds                                  0.045952                       # Number of seconds simulated
 sim_ticks                                 45951567500                       # Number of ticks simulated
-system.cpu.dtb.accesses                      26497334                       # DTB accesses
-system.cpu.dtb.acv                                  0                       # DTB access violations
-system.cpu.dtb.hits                          26497301                       # DTB hits
-system.cpu.dtb.misses                              33                       # DTB misses
+system.cpu.dtb.data_accesses                 26497334                       # DTB accesses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_hits                     26497301                       # DTB hits
+system.cpu.dtb.data_misses                         33                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                 19996208                       # DTB read accesses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
 system.cpu.dtb.read_hits                     19996198                       # DTB read hits
@@ -21,10 +25,22 @@ system.cpu.dtb.write_acv                            0                       # DT
 system.cpu.dtb.write_hits                     6501103                       # DTB write hits
 system.cpu.dtb.write_misses                        23                       # DTB write misses
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                      91903136                       # ITB accesses
-system.cpu.itb.acv                                  0                       # ITB acv
-system.cpu.itb.hits                          91903089                       # ITB hits
-system.cpu.itb.misses                              47                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses                91903136                       # ITB accesses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_hits                    91903089                       # ITB hits
+system.cpu.itb.fetch_misses                        47                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                         91903136                       # number of cpu cycles simulated
 system.cpu.num_insts                         91903056                       # Number of instructions executed
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
index b166b9052..2164626a2 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu.l2cache]
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
index c9ffcf959..24227ac66 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:41:35
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py long/70.twolf/alpha/tru64/simple-timing
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:33:56
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
index c77e086b4..e5dfef14d 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2902114                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 207972                       # Number of bytes of host memory used
-host_seconds                                    31.67                       # Real time elapsed on the host
-host_tick_rate                             3749775750                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2783619                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 209832                       # Number of bytes of host memory used
+host_seconds                                    33.02                       # Real time elapsed on the host
+host_tick_rate                             3596666384                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_seconds                                  0.118747                       # Number of seconds simulated
@@ -71,10 +71,14 @@ system.cpu.dcache.tagsinuse               1442.022508                       # Cy
 system.cpu.dcache.total_refs                 26495078                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                      104                       # number of writebacks
-system.cpu.dtb.accesses                      26497334                       # DTB accesses
-system.cpu.dtb.acv                                  0                       # DTB access violations
-system.cpu.dtb.hits                          26497301                       # DTB hits
-system.cpu.dtb.misses                              33                       # DTB misses
+system.cpu.dtb.data_accesses                 26497334                       # DTB accesses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_hits                     26497301                       # DTB hits
+system.cpu.dtb.data_misses                         33                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                 19996208                       # DTB read accesses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
 system.cpu.dtb.read_hits                     19996198                       # DTB read hits
@@ -137,10 +141,22 @@ system.cpu.icache.total_refs                 91894580                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                      91903137                       # ITB accesses
-system.cpu.itb.acv                                  0                       # ITB acv
-system.cpu.itb.hits                          91903090                       # ITB hits
-system.cpu.itb.misses                              47                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses                91903137                       # ITB accesses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_hits                    91903090                       # ITB hits
+system.cpu.itb.fetch_misses                        47                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.l2cache.ReadExReq_accesses            1748                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
index 3d5e2c242..a9a96bdd5 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
@@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
 icache_port=system.membus.port[1]
 
 [system.cpu.dtb]
-type=SparcDTB
+type=SparcTLB
 size=64
 
 [system.cpu.itb]
-type=SparcITB
+type=SparcTLB
 size=64
 
 [system.cpu.tracer]
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout
index eb6462de2..bcecb77e1 100755
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:17:12
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:55:15
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic -re tests/run.py long/70.twolf/sparc/linux/simple-atomic
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:32:55
+M5 executing on maize
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
index 9b4c86591..2a0d5ef75 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2406877                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 202316                       # Number of bytes of host memory used
-host_seconds                                    80.37                       # Real time elapsed on the host
-host_tick_rate                             1203441627                       # Simulator tick rate (ticks/s)
+host_inst_rate                                3173092                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 204068                       # Number of bytes of host memory used
+host_seconds                                    60.96                       # Real time elapsed on the host
+host_tick_rate                             1586549351                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   193444769                       # Number of instructions simulated
 sim_seconds                                  0.096723                       # Number of seconds simulated
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
index 65aeb1d48..1c4d82608 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=SparcDTB
+type=SparcTLB
 size=64
 
 [system.cpu.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=SparcITB
+type=SparcTLB
 size=64
 
 [system.cpu.l2cache]
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
index b27d83682..bc529416a 100755
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
@@ -5,13 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 24 2009 01:30:29
-M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch
-M5 started Feb 24 2009 01:33:08
-M5 executing on tater
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re tests/run.py long/70.twolf/sparc/linux/simple-timing
-Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav
-Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:31:47
+M5 executing on maize
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
index f73a0dcbf..1993c7752 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 732316                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 209324                       # Number of bytes of host memory used
-host_seconds                                   264.15                       # Real time elapsed on the host
-host_tick_rate                             1024317022                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1944755                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 211604                       # Number of bytes of host memory used
+host_seconds                                    99.47                       # Real time elapsed on the host
+host_tick_rate                             2720193548                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   193444769                       # Number of instructions simulated
 sim_seconds                                  0.270578                       # Number of seconds simulated
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
index d0a878165..e88047c7b 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
@@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
 icache_port=system.membus.port[1]
 
 [system.cpu.dtb]
-type=X86DTB
+type=X86TLB
 size=64
 
 [system.cpu.itb]
-type=X86ITB
+type=X86TLB
 size=64
 
 [system.cpu.tracer]
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
index 100c59b7e..cba3e283b 100755
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
@@ -5,13 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 23 2009 23:45:19
-M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch
-M5 started Feb 23 2009 23:54:15
-M5 executing on tater
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re tests/run.py long/70.twolf/x86/linux/simple-atomic
-Couldn't unlink  build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav
-Couldn't unlink  build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:58:24
+M5 executing on maize
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
index f3c94835b..d349a3ec1 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 744144                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 204416                       # Number of bytes of host memory used
-host_seconds                                   293.75                       # Real time elapsed on the host
-host_tick_rate                              442578451                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2597593                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 206992                       # Number of bytes of host memory used
+host_seconds                                    84.15                       # Real time elapsed on the host
+host_tick_rate                             1544910141                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   218595300                       # Number of instructions simulated
 sim_seconds                                  0.130009                       # Number of seconds simulated
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
index c231a2f5e..8b6664da9 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=X86DTB
+type=X86TLB
 size=64
 
 [system.cpu.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=X86ITB
+type=X86TLB
 size=64
 
 [system.cpu.l2cache]
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
index 2a43627aa..71a382614 100755
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
@@ -5,13 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 24 2009 01:30:29
-M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch
-M5 started Feb 24 2009 01:58:47
-M5 executing on tater
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py long/70.twolf/x86/linux/simple-timing
-Couldn't unlink  build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sav
-Couldn't unlink  build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sv2
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 13:09:44
+M5 executing on maize
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
index 3d7cbb069..06ac4f668 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 660588                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 211972                       # Number of bytes of host memory used
-host_seconds                                   330.91                       # Real time elapsed on the host
-host_tick_rate                              758349031                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1718028                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 214564                       # Number of bytes of host memory used
+host_seconds                                   127.24                       # Real time elapsed on the host
+host_tick_rate                             1972277446                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   218595300                       # Number of instructions simulated
 sim_seconds                                  0.250945                       # Number of seconds simulated
diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
index 1a673fafa..4b84818cf 100644
--- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
+++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
@@ -77,14 +77,14 @@ dcache_port=system.membus.port[10]
 icache_port=system.membus.port[9]
 
 [system.cpu.dtb]
-type=SparcDTB
+type=SparcTLB
 size=64
 
 [system.cpu.interrupts]
 type=SparcInterrupts
 
 [system.cpu.itb]
-type=SparcITB
+type=SparcTLB
 size=64
 
 [system.cpu.tracer]
diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
index 177f45aa2..31a7bda45 100755
--- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
+++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 01:00:04
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 01:00:27
-M5 executing on zizzer
-command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py long/80.solaris-boot/sparc/solaris/t1000-simple-atomic
+M5 compiled Apr  8 2009 12:30:03
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:30:19
+M5 executing on maize
+command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic
 Global frequency set at 2000000000 ticks per second
 info: No kernel set for full system simulation. Assuming you know what you're doing...
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
index 74e0ebf1a..4fd5a8137 100644
--- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
+++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2534703                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 501600                       # Number of bytes of host memory used
-host_seconds                                   879.46                       # Real time elapsed on the host
-host_tick_rate                                2539952                       # Simulator tick rate (ticks/s)
+host_inst_rate                                3204133                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 503348                       # Number of bytes of host memory used
+host_seconds                                   695.71                       # Real time elapsed on the host
+host_tick_rate                                3210768                       # Simulator tick rate (ticks/s)
 sim_freq                                   2000000000                       # Frequency of simulated ticks
 sim_insts                                  2229160714                       # Number of instructions simulated
 sim_seconds                                  1.116889                       # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
index 46ef9d2b9..7eb74398a 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
@@ -132,7 +132,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu.fuPool]
@@ -305,7 +305,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu.l2cache]
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
index f448ee025..3b9bfb958 100755
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar  6 2009 18:15:46
-M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
-M5 started Mar  6 2009 18:22:19
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:44:12
 M5 executing on maize
-command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py quick/00.hello/alpha/linux/o3-timing
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
index 21437f2a4..b0e90083c 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  83921                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 202572                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
-host_tick_rate                              163392144                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  62049                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 202540                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
+host_tick_rate                              120907399                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        6386                       # Number of instructions simulated
 sim_seconds                                  0.000012                       # Number of seconds simulated
@@ -123,10 +123,14 @@ system.cpu.decode.DECODE:RunCycles               2366                       # Nu
 system.cpu.decode.DECODE:SquashCycles             897                       # Number of cycles decode is squashing
 system.cpu.decode.DECODE:SquashedInsts            209                       # Number of squashed instructions handled by decode
 system.cpu.decode.DECODE:UnblockCycles             54                       # Number of cycles decode is unblocking
-system.cpu.dtb.accesses                          2951                       # DTB accesses
-system.cpu.dtb.acv                                  0                       # DTB access violations
-system.cpu.dtb.hits                              2890                       # DTB hits
-system.cpu.dtb.misses                              61                       # DTB misses
+system.cpu.dtb.data_accesses                     2951                       # DTB accesses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_hits                         2890                       # DTB hits
+system.cpu.dtb.data_misses                         61                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                     1876                       # DTB read accesses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
 system.cpu.dtb.read_hits                         1840                       # DTB read hits
@@ -321,10 +325,22 @@ system.cpu.iq.iqSquashedInstsExamined            4189                       # Nu
 system.cpu.iq.iqSquashedInstsIssued                53                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved              7                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined         2547                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses                          1838                       # ITB accesses
-system.cpu.itb.acv                                  0                       # ITB acv
-system.cpu.itb.hits                              1802                       # ITB hits
-system.cpu.itb.misses                              36                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses                    1838                       # ITB accesses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_hits                        1802                       # ITB hits
+system.cpu.itb.fetch_misses                        36                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.l2cache.ReadExReq_accesses              73                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency 34547.945205                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31465.753425                       # average ReadExReq mshr miss latency
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
index 5b4a31473..adc37d29a 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
@@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
 icache_port=system.membus.port[1]
 
 [system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu.tracer]
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout
index 8975ff812..da206d16c 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:22:12
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re tests/run.py quick/00.hello/alpha/linux/simple-atomic
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:37:48
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt
index 93917b1eb..a6c36497f 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt
@@ -1,17 +1,21 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 122377                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 192524                       # Number of bytes of host memory used
+host_inst_rate                                 130449                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 194292                       # Number of bytes of host memory used
 host_seconds                                     0.05                       # Real time elapsed on the host
-host_tick_rate                               61135620                       # Simulator tick rate (ticks/s)
+host_tick_rate                               65193146                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        6404                       # Number of instructions simulated
 sim_seconds                                  0.000003                       # Number of seconds simulated
 sim_ticks                                     3215000                       # Number of ticks simulated
-system.cpu.dtb.accesses                          2060                       # DTB accesses
-system.cpu.dtb.acv                                  0                       # DTB access violations
-system.cpu.dtb.hits                              2050                       # DTB hits
-system.cpu.dtb.misses                              10                       # DTB misses
+system.cpu.dtb.data_accesses                     2060                       # DTB accesses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_hits                         2050                       # DTB hits
+system.cpu.dtb.data_misses                         10                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                     1192                       # DTB read accesses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
 system.cpu.dtb.read_hits                         1185                       # DTB read hits
@@ -21,10 +25,22 @@ system.cpu.dtb.write_acv                            0                       # DT
 system.cpu.dtb.write_hits                         865                       # DTB write hits
 system.cpu.dtb.write_misses                         3                       # DTB write misses
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                          6431                       # ITB accesses
-system.cpu.itb.acv                                  0                       # ITB acv
-system.cpu.itb.hits                              6414                       # ITB hits
-system.cpu.itb.misses                              17                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses                    6431                       # ITB accesses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_hits                        6414                       # ITB hits
+system.cpu.itb.fetch_misses                        17                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                             6431                       # number of cpu cycles simulated
 system.cpu.num_insts                             6404                       # Number of instructions executed
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
index 26edcc7cf..988a9a0ce 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu.l2cache]
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout
index 22d348b2d..fd7224cc6 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:22:12
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re tests/run.py quick/00.hello/alpha/linux/simple-timing
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:30:03
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt
index dc4411624..14eb9b58a 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 344098                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 199968                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
-host_tick_rate                             1795121173                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  14499                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 201828                       # Number of bytes of host memory used
+host_seconds                                     0.44                       # Real time elapsed on the host
+host_tick_rate                               76395737                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        6404                       # Number of instructions simulated
 sim_seconds                                  0.000034                       # Number of seconds simulated
@@ -71,10 +71,14 @@ system.cpu.dcache.tagsinuse                104.111261                       # Cy
 system.cpu.dcache.total_refs                     1882                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.dtb.accesses                          2060                       # DTB accesses
-system.cpu.dtb.acv                                  0                       # DTB access violations
-system.cpu.dtb.hits                              2050                       # DTB hits
-system.cpu.dtb.misses                              10                       # DTB misses
+system.cpu.dtb.data_accesses                     2060                       # DTB accesses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_hits                         2050                       # DTB hits
+system.cpu.dtb.data_misses                         10                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                     1192                       # DTB read accesses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
 system.cpu.dtb.read_hits                         1185                       # DTB read hits
@@ -137,10 +141,22 @@ system.cpu.icache.total_refs                     6136                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                          6432                       # ITB accesses
-system.cpu.itb.acv                                  0                       # ITB acv
-system.cpu.itb.hits                              6415                       # ITB hits
-system.cpu.itb.misses                              17                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses                    6432                       # ITB accesses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_hits                        6415                       # ITB hits
+system.cpu.itb.fetch_misses                        17                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.l2cache.ReadExReq_accesses              73                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
index 9abe15dfc..a1f81629d 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -132,7 +132,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu.fuPool]
@@ -305,7 +305,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu.l2cache]
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
index 038644e5f..19ff35ac6 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar  6 2009 18:15:46
-M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
-M5 started Mar  6 2009 18:16:36
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:44:10
 M5 executing on maize
-command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py quick/00.hello/alpha/tru64/o3-timing
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
index 14b605eaa..4b2eade71 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  39458                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 201572                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
-host_tick_rate                              118256203                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  53715                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 201548                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
+host_tick_rate                              160751052                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        2387                       # Number of instructions simulated
 sim_seconds                                  0.000007                       # Number of seconds simulated
@@ -123,10 +123,14 @@ system.cpu.decode.DECODE:RunCycles                929                       # Nu
 system.cpu.decode.DECODE:SquashCycles             331                       # Number of cycles decode is squashing
 system.cpu.decode.DECODE:SquashedInsts            284                       # Number of squashed instructions handled by decode
 system.cpu.decode.DECODE:UnblockCycles              1                       # Number of cycles decode is unblocking
-system.cpu.dtb.accesses                           971                       # DTB accesses
-system.cpu.dtb.acv                                  1                       # DTB access violations
-system.cpu.dtb.hits                               946                       # DTB hits
-system.cpu.dtb.misses                              25                       # DTB misses
+system.cpu.dtb.data_accesses                      971                       # DTB accesses
+system.cpu.dtb.data_acv                             1                       # DTB access violations
+system.cpu.dtb.data_hits                          946                       # DTB hits
+system.cpu.dtb.data_misses                         25                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                      611                       # DTB read accesses
 system.cpu.dtb.read_acv                             1                       # DTB read access violations
 system.cpu.dtb.read_hits                          600                       # DTB read hits
@@ -321,10 +325,22 @@ system.cpu.iq.iqSquashedInstsExamined            1447                       # Nu
 system.cpu.iq.iqSquashedInstsIssued                15                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved              2                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined          766                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses                           776                       # ITB accesses
-system.cpu.itb.acv                                  0                       # ITB acv
-system.cpu.itb.hits                               747                       # ITB hits
-system.cpu.itb.misses                              29                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses                     776                       # ITB accesses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_hits                         747                       # ITB hits
+system.cpu.itb.fetch_misses                        29                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.l2cache.ReadExReq_accesses              24                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency 34604.166667                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        31500                       # average ReadExReq mshr miss latency
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
index 8ca1fff45..255dbd855 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
@@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
 icache_port=system.membus.port[1]
 
 [system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu.tracer]
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
index 7c13e1d4c..fd4dcc4fc 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:22:12
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py quick/00.hello/alpha/tru64/simple-atomic
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:30:03
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
index ddfd1ad69..fc21ca705 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,17 +1,21 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 147781                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 191596                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
-host_tick_rate                               73371409                       # Simulator tick rate (ticks/s)
+host_inst_rate                                   7782                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 193364                       # Number of bytes of host memory used
+host_seconds                                     0.33                       # Real time elapsed on the host
+host_tick_rate                                3915244                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        2577                       # Number of instructions simulated
 sim_seconds                                  0.000001                       # Number of seconds simulated
 sim_ticks                                     1297500                       # Number of ticks simulated
-system.cpu.dtb.accesses                           717                       # DTB accesses
-system.cpu.dtb.acv                                  0                       # DTB access violations
-system.cpu.dtb.hits                               709                       # DTB hits
-system.cpu.dtb.misses                               8                       # DTB misses
+system.cpu.dtb.data_accesses                      717                       # DTB accesses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_hits                          709                       # DTB hits
+system.cpu.dtb.data_misses                          8                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                      419                       # DTB read accesses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
 system.cpu.dtb.read_hits                          415                       # DTB read hits
@@ -21,10 +25,22 @@ system.cpu.dtb.write_acv                            0                       # DT
 system.cpu.dtb.write_hits                         294                       # DTB write hits
 system.cpu.dtb.write_misses                         4                       # DTB write misses
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                          2596                       # ITB accesses
-system.cpu.itb.acv                                  0                       # ITB acv
-system.cpu.itb.hits                              2585                       # ITB hits
-system.cpu.itb.misses                              11                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses                    2596                       # ITB accesses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_hits                        2585                       # ITB hits
+system.cpu.itb.fetch_misses                        11                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                             2596                       # number of cpu cycles simulated
 system.cpu.num_insts                             2577                       # Number of instructions executed
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
index f0bdf09de..be492f6c5 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu.l2cache]
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
index 3560f6496..ac591190c 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:22:12
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py quick/00.hello/alpha/tru64/simple-timing
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:30:03
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
index 5c25b785f..da1cac32f 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  73131                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 199016                       # Number of bytes of host memory used
-host_seconds                                     0.04                       # Real time elapsed on the host
-host_tick_rate                              490513834                       # Simulator tick rate (ticks/s)
+host_inst_rate                                   6492                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 200880                       # Number of bytes of host memory used
+host_seconds                                     0.40                       # Real time elapsed on the host
+host_tick_rate                               43734802                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        2577                       # Number of instructions simulated
 sim_seconds                                  0.000017                       # Number of seconds simulated
@@ -71,10 +71,14 @@ system.cpu.dcache.tagsinuse                 47.575114                       # Cy
 system.cpu.dcache.total_refs                      627                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.dtb.accesses                           717                       # DTB accesses
-system.cpu.dtb.acv                                  0                       # DTB access violations
-system.cpu.dtb.hits                               709                       # DTB hits
-system.cpu.dtb.misses                               8                       # DTB misses
+system.cpu.dtb.data_accesses                      717                       # DTB accesses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_hits                          709                       # DTB hits
+system.cpu.dtb.data_misses                          8                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                      419                       # DTB read accesses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
 system.cpu.dtb.read_hits                          415                       # DTB read hits
@@ -137,10 +141,22 @@ system.cpu.icache.total_refs                     2423                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                          2597                       # ITB accesses
-system.cpu.itb.acv                                  0                       # ITB acv
-system.cpu.itb.hits                              2586                       # ITB hits
-system.cpu.itb.misses                              11                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses                    2597                       # ITB accesses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_hits                        2586                       # ITB hits
+system.cpu.itb.fetch_misses                        11                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.l2cache.ReadExReq_accesses              27                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
index 766c4f486..5d677c743 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
@@ -11,7 +11,7 @@ physmem=system.physmem
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tlb tracer workload
+children=dtb itb tracer workload
 CP0_Config=0
 CP0_Config1=0
 CP0_Config1_C2=false
@@ -66,7 +66,6 @@ CP0_PerfCtr_M=false
 CP0_PerfCtr_W=false
 CP0_SrsCtl_HSS=0
 CP0_WatchHi_M=false
-UnifiedTLB=true
 checker=Null
 clock=500
 cpu_id=0
@@ -87,7 +86,6 @@ progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
 system=system
-tlb=system.cpu.tlb
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
@@ -95,15 +93,11 @@ dcache_port=system.membus.port[2]
 icache_port=system.membus.port[1]
 
 [system.cpu.dtb]
-type=MipsDTB
+type=MipsTLB
 size=64
 
 [system.cpu.itb]
-type=MipsITB
-size=64
-
-[system.cpu.tlb]
-type=MipsUTB
+type=MipsTLB
 size=64
 
 [system.cpu.tracer]
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
index 7b1955a4b..4fee53c4d 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:16:15
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:16:42
-M5 executing on zizzer
-command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re tests/run.py quick/00.hello/mips/linux/simple-atomic
+M5 compiled Apr  8 2009 12:30:01
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:33:27
+M5 executing on maize
+command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
index 20921ce17..a50f65423 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  24803                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 193824                       # Number of bytes of host memory used
-host_seconds                                     0.23                       # Real time elapsed on the host
-host_tick_rate                               12384497                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 113529                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 195572                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
+host_tick_rate                               56492209                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5656                       # Number of instructions simulated
 sim_seconds                                  0.000003                       # Number of seconds simulated
@@ -31,24 +31,6 @@ system.cpu.not_idle_fraction                        1                       # Pe
 system.cpu.numCycles                             5657                       # number of cpu cycles simulated
 system.cpu.num_insts                             5656                       # Number of instructions executed
 system.cpu.num_refs                              2055                       # Number of memory references
-system.cpu.tlb.accesses                             0                       # DTB accesses
-system.cpu.tlb.accesses                             0                       # DTB accesses
-system.cpu.tlb.hits                                 0                       # DTB hits
-system.cpu.tlb.hits                                 0                       # DTB hits
-system.cpu.tlb.misses                               0                       # DTB misses
-system.cpu.tlb.misses                               0                       # DTB misses
-system.cpu.tlb.read_accesses                        0                       # DTB read accesses
-system.cpu.tlb.read_accesses                        0                       # DTB read accesses
-system.cpu.tlb.read_hits                            0                       # DTB read hits
-system.cpu.tlb.read_hits                            0                       # DTB read hits
-system.cpu.tlb.read_misses                          0                       # DTB read misses
-system.cpu.tlb.read_misses                          0                       # DTB read misses
-system.cpu.tlb.write_accesses                       0                       # DTB write accesses
-system.cpu.tlb.write_accesses                       0                       # DTB write accesses
-system.cpu.tlb.write_hits                           0                       # DTB write hits
-system.cpu.tlb.write_hits                           0                       # DTB write hits
-system.cpu.tlb.write_misses                         0                       # DTB write misses
-system.cpu.tlb.write_misses                         0                       # DTB write misses
 system.cpu.workload.PROG:num_syscalls              13                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
index d6fb3e91a..ac73fcc0d 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -11,7 +11,7 @@ physmem=system.physmem
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache tlb toL2Bus tracer workload
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
 CP0_Config=0
 CP0_Config1=0
 CP0_Config1_C2=false
@@ -66,7 +66,6 @@ CP0_PerfCtr_M=false
 CP0_PerfCtr_W=false
 CP0_SrsCtl_HSS=0
 CP0_WatchHi_M=false
-UnifiedTLB=true
 checker=Null
 clock=500
 cpu_id=0
@@ -85,7 +84,6 @@ numThreads=1
 phase=0
 progress_interval=0
 system=system
-tlb=system.cpu.tlb
 tracer=system.cpu.tracer
 workload=system.cpu.workload
 dcache_port=system.cpu.dcache.cpu_side
@@ -124,7 +122,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=MipsDTB
+type=MipsTLB
 size=64
 
 [system.cpu.icache]
@@ -160,7 +158,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=MipsITB
+type=MipsTLB
 size=64
 
 [system.cpu.l2cache]
@@ -195,10 +193,6 @@ write_buffers=8
 cpu_side=system.cpu.toL2Bus.port[2]
 mem_side=system.membus.port[1]
 
-[system.cpu.tlb]
-type=MipsUTB
-size=64
-
 [system.cpu.toL2Bus]
 type=Bus
 block_size=64
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
index a5bd2cd4d..77ad52898 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:16:15
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:16:42
-M5 executing on zizzer
-command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re tests/run.py quick/00.hello/mips/linux/simple-timing
+M5 compiled Apr  8 2009 12:30:01
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:30:04
+M5 executing on maize
+command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
index de10d4a74..c7fdc027e 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  26568                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 201268                       # Number of bytes of host memory used
-host_seconds                                     0.21                       # Real time elapsed on the host
-host_tick_rate                              151609105                       # Simulator tick rate (ticks/s)
+host_inst_rate                                   6063                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 203244                       # Number of bytes of host memory used
+host_seconds                                     0.93                       # Real time elapsed on the host
+host_tick_rate                               34635885                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5656                       # Number of instructions simulated
 sim_seconds                                  0.000032                       # Number of seconds simulated
@@ -218,24 +218,6 @@ system.cpu.not_idle_fraction                        1                       # Pe
 system.cpu.numCycles                            64644                       # number of cpu cycles simulated
 system.cpu.num_insts                             5656                       # Number of instructions executed
 system.cpu.num_refs                              2055                       # Number of memory references
-system.cpu.tlb.accesses                             0                       # DTB accesses
-system.cpu.tlb.accesses                             0                       # DTB accesses
-system.cpu.tlb.hits                                 0                       # DTB hits
-system.cpu.tlb.hits                                 0                       # DTB hits
-system.cpu.tlb.misses                               0                       # DTB misses
-system.cpu.tlb.misses                               0                       # DTB misses
-system.cpu.tlb.read_accesses                        0                       # DTB read accesses
-system.cpu.tlb.read_accesses                        0                       # DTB read accesses
-system.cpu.tlb.read_hits                            0                       # DTB read hits
-system.cpu.tlb.read_hits                            0                       # DTB read hits
-system.cpu.tlb.read_misses                          0                       # DTB read misses
-system.cpu.tlb.read_misses                          0                       # DTB read misses
-system.cpu.tlb.write_accesses                       0                       # DTB write accesses
-system.cpu.tlb.write_accesses                       0                       # DTB write accesses
-system.cpu.tlb.write_hits                           0                       # DTB write hits
-system.cpu.tlb.write_hits                           0                       # DTB write hits
-system.cpu.tlb.write_misses                         0                       # DTB write misses
-system.cpu.tlb.write_misses                         0                       # DTB write misses
 system.cpu.workload.PROG:num_syscalls              13                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
index 970388ae5..ade758841 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
@@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
 icache_port=system.membus.port[1]
 
 [system.cpu.dtb]
-type=SparcDTB
+type=SparcTLB
 size=64
 
 [system.cpu.itb]
-type=SparcITB
+type=SparcTLB
 size=64
 
 [system.cpu.tracer]
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout
index eefaf1737..c66e3090a 100755
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:17:12
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:17:34
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic -re tests/run.py quick/00.hello/sparc/linux/simple-atomic
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:32:53
+M5 executing on maize
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello World!Exiting @ tick 2701000 because target called exit()
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt
index b09b910ba..90590228c 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  25851                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 193720                       # Number of bytes of host memory used
-host_seconds                                     0.21                       # Real time elapsed on the host
-host_tick_rate                               13060676                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 179147                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 195464                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
+host_tick_rate                               89901478                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5340                       # Number of instructions simulated
 sim_seconds                                  0.000003                       # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
index f68b9582f..2bb5be9ae 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=SparcDTB
+type=SparcTLB
 size=64
 
 [system.cpu.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=SparcITB
+type=SparcTLB
 size=64
 
 [system.cpu.l2cache]
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
index fcae28521..b434e54e7 100755
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:17:12
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:17:34
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re tests/run.py quick/00.hello/sparc/linux/simple-timing
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:30:32
+M5 executing on maize
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello World!Exiting @ tick 29031000 because target called exit()
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
index cf7518d98..011b7eb96 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  21374                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 201092                       # Number of bytes of host memory used
-host_seconds                                     0.25                       # Real time elapsed on the host
-host_tick_rate                              116036277                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  18112                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 202936                       # Number of bytes of host memory used
+host_seconds                                     0.30                       # Real time elapsed on the host
+host_tick_rate                               98375821                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5340                       # Number of instructions simulated
 sim_seconds                                  0.000029                       # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
index 1a9a034e8..911046b97 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
@@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
 icache_port=system.membus.port[1]
 
 [system.cpu.dtb]
-type=X86DTB
+type=X86TLB
 size=64
 
 [system.cpu.itb]
-type=X86ITB
+type=X86TLB
 size=64
 
 [system.cpu.tracer]
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
index 60f35ee0f..4e7b9509a 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 23 2009 23:45:19
-M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch
-M5 started Feb 23 2009 23:59:09
-M5 executing on tater
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py quick/00.hello/x86/linux/simple-atomic
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:59:49
+M5 executing on maize
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
index 454f55a63..e01f452d4 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 165270                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 192880                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
-host_tick_rate                               95268287                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 250793                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 195416                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
+host_tick_rate                              144131714                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        9484                       # Number of instructions simulated
 sim_seconds                                  0.000005                       # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
index d1edd6c59..ff74f91e4 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=X86DTB
+type=X86TLB
 size=64
 
 [system.cpu.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=X86ITB
+type=X86TLB
 size=64
 
 [system.cpu.l2cache]
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
index a84f40e19..dbbe5f90a 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 24 2009 01:30:29
-M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch
-M5 started Feb 24 2009 01:37:33
-M5 executing on tater
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py quick/00.hello/x86/linux/simple-timing
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 13:09:24
+M5 executing on maize
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
index b8a17302a..dd6fe41f9 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 139542                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 200396                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
-host_tick_rate                              436046426                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 171022                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 202960                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
+host_tick_rate                              533375213                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        9484                       # Number of instructions simulated
 sim_seconds                                  0.000030                       # Number of seconds simulated
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
index 9c8da927d..fa7d3cfec 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
@@ -132,7 +132,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu.fuPool]
@@ -305,7 +305,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu.l2cache]
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
index 7101807df..46bfe60b8 100755
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar  6 2009 18:15:46
-M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
-M5 started Mar  6 2009 18:23:16
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:44:23
 M5 executing on maize
-command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
index 783867939..ae5c73ad7 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 106034                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 203088                       # Number of bytes of host memory used
-host_seconds                                     0.12                       # Real time elapsed on the host
-host_tick_rate                              118060043                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  98882                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 203072                       # Number of bytes of host memory used
+host_seconds                                     0.13                       # Real time elapsed on the host
+host_tick_rate                              110106309                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                       12773                       # Number of instructions simulated
 sim_seconds                                  0.000014                       # Number of seconds simulated
@@ -211,10 +211,14 @@ system.cpu.decode.DECODE:RunCycles               4878                       # Nu
 system.cpu.decode.DECODE:SquashCycles            2128                       # Number of cycles decode is squashing
 system.cpu.decode.DECODE:SquashedInsts            668                       # Number of squashed instructions handled by decode
 system.cpu.decode.DECODE:UnblockCycles            186                       # Number of cycles decode is unblocking
-system.cpu.dtb.accesses                          6300                       # DTB accesses
-system.cpu.dtb.acv                                  0                       # DTB access violations
-system.cpu.dtb.hits                              6155                       # DTB hits
-system.cpu.dtb.misses                             145                       # DTB misses
+system.cpu.dtb.data_accesses                     6300                       # DTB accesses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_hits                         6155                       # DTB hits
+system.cpu.dtb.data_misses                        145                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                     4144                       # DTB read accesses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
 system.cpu.dtb.read_hits                         4056                       # DTB read hits
@@ -551,10 +555,22 @@ system.cpu.iq.iqSquashedInstsExamined            9662                       # Nu
 system.cpu.iq.iqSquashedInstsIssued               105                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved             10                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined         5422                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses                          4162                       # ITB accesses
-system.cpu.itb.acv                                  0                       # ITB acv
-system.cpu.itb.hits                              4113                       # ITB hits
-system.cpu.itb.misses                              49                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses                    4162                       # ITB accesses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_hits                        4113                       # ITB hits
+system.cpu.itb.fetch_misses                        49                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.l2cache.ReadExReq_accesses             146                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses_0           146                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency_0 34643.835616                       # average ReadExReq miss latency
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
index 102ce19a3..cd894f5bd 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
@@ -132,7 +132,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=SparcDTB
+type=SparcTLB
 size=64
 
 [system.cpu.fuPool]
@@ -305,7 +305,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=SparcITB
+type=SparcTLB
 size=64
 
 [system.cpu.l2cache]
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
index f1994d462..642546f37 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar  6 2009 18:29:06
-M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
-M5 started Mar  6 2009 18:30:50
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:32:54
 M5 executing on maize
-command line: /n/blue/z/binkert/build/work/build/SPARC_SE/m5.fast -d /n/blue/z/binkert/build/work/build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py quick/02.insttest/sparc/linux/o3-timing
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Begining test of difficult SPARC instructions...
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
index 67e62423e..77ce05481 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  66771                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 203496                       # Number of bytes of host memory used
-host_seconds                                     0.22                       # Real time elapsed on the host
-host_tick_rate                              128111456                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  71088                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 203480                       # Number of bytes of host memory used
+host_seconds                                     0.20                       # Real time elapsed on the host
+host_tick_rate                              136384184                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                       14449                       # Number of instructions simulated
 sim_seconds                                  0.000028                       # Number of seconds simulated
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini
index c81ee3264..75d383c46 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini
@@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
 icache_port=system.membus.port[1]
 
 [system.cpu.dtb]
-type=SparcDTB
+type=SparcTLB
 size=64
 
 [system.cpu.itb]
-type=SparcITB
+type=SparcTLB
 size=64
 
 [system.cpu.tracer]
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout
index cb610b0c6..645f97a41 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:17:12
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:17:34
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic -re tests/run.py quick/02.insttest/sparc/linux/simple-atomic
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:30:34
+M5 executing on maize
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Begining test of difficult SPARC instructions...
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
index d9897842c..1ac975e6b 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  61727                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 193528                       # Number of bytes of host memory used
-host_seconds                                     0.25                       # Real time elapsed on the host
-host_tick_rate                               30956425                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 387939                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 195268                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
+host_tick_rate                              193638166                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                       15175                       # Number of instructions simulated
 sim_seconds                                  0.000008                       # Number of seconds simulated
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
index 8777df95f..2a3a9cb21 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=SparcDTB
+type=SparcTLB
 size=64
 
 [system.cpu.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=SparcITB
+type=SparcTLB
 size=64
 
 [system.cpu.l2cache]
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout
index 65fc22a94..788bf8fe4 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:17:12
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:17:34
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py quick/02.insttest/sparc/linux/simple-timing
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:30:40
+M5 executing on maize
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Begining test of difficult SPARC instructions...
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt
index 323f23c0d..81d91e476 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  71328                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 200972                       # Number of bytes of host memory used
-host_seconds                                     0.21                       # Real time elapsed on the host
-host_tick_rate                              200611199                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  11404                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 202820                       # Number of bytes of host memory used
+host_seconds                                     1.33                       # Real time elapsed on the host
+host_tick_rate                               32108089                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                       15175                       # Number of instructions simulated
 sim_seconds                                  0.000043                       # Number of seconds simulated
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
index 56dec3815..ef33d965f 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
@@ -97,7 +97,7 @@ cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.port[2]
 
 [system.cpu0.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu0.icache]
@@ -136,7 +136,7 @@ mem_side=system.toL2Bus.port[1]
 type=AlphaInterrupts
 
 [system.cpu0.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu0.tracer]
@@ -206,7 +206,7 @@ cpu_side=system.cpu1.dcache_port
 mem_side=system.toL2Bus.port[4]
 
 [system.cpu1.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu1.icache]
@@ -245,7 +245,7 @@ mem_side=system.toL2Bus.port[3]
 type=AlphaInterrupts
 
 [system.cpu1.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu1.tracer]
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
index 8c40366bc..a95a79ffc 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:15:24
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:15:50
-M5 executing on zizzer
-command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:30:04
+M5 executing on maize
+command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
index 8ed468432..a781e9d48 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2804596                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 292704                       # Number of bytes of host memory used
-host_seconds                                    22.52                       # Real time elapsed on the host
-host_tick_rate                            83058483755                       # Simulator tick rate (ticks/s)
+host_inst_rate                                4473904                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 294520                       # Number of bytes of host memory used
+host_seconds                                    14.12                       # Real time elapsed on the host
+host_tick_rate                           132494065933                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    63154034                       # Number of instructions simulated
 sim_seconds                                  1.870336                       # Number of seconds simulated
@@ -67,10 +67,14 @@ system.cpu0.dcache.tagsinuse               504.827058                       # Cy
 system.cpu0.dcache.total_refs                13123502                       # Total number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle              10840000                       # Cycle when the warmup percentage was hit.
 system.cpu0.dcache.writebacks                  396793                       # number of writebacks
-system.cpu0.dtb.accesses                       698037                       # DTB accesses
-system.cpu0.dtb.acv                               251                       # DTB access violations
-system.cpu0.dtb.hits                         15091429                       # DTB hits
-system.cpu0.dtb.misses                           7805                       # DTB misses
+system.cpu0.dtb.data_accesses                  698037                       # DTB accesses
+system.cpu0.dtb.data_acv                          251                       # DTB access violations
+system.cpu0.dtb.data_hits                    15091429                       # DTB hits
+system.cpu0.dtb.data_misses                      7805                       # DTB misses
+system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu0.dtb.fetch_acv                           0                       # ITB acv
+system.cpu0.dtb.fetch_hits                          0                       # ITB hits
+system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.read_accesses                  508987                       # DTB read accesses
 system.cpu0.dtb.read_acv                          152                       # DTB read access violations
 system.cpu0.dtb.read_hits                     9154530                       # DTB read hits
@@ -127,10 +131,22 @@ system.cpu0.icache.total_refs                56345132                       # To
 system.cpu0.icache.warmup_cycle            9786576500                       # Cycle when the warmup percentage was hit.
 system.cpu0.icache.writebacks                       0                       # number of writebacks
 system.cpu0.idle_fraction                    0.984700                       # Percentage of idle cycles
-system.cpu0.itb.accesses                      3859041                       # ITB accesses
-system.cpu0.itb.acv                               127                       # ITB acv
-system.cpu0.itb.hits                          3855556                       # ITB hits
-system.cpu0.itb.misses                           3485                       # ITB misses
+system.cpu0.itb.data_accesses                       0                       # DTB accesses
+system.cpu0.itb.data_acv                            0                       # DTB access violations
+system.cpu0.itb.data_hits                           0                       # DTB hits
+system.cpu0.itb.data_misses                         0                       # DTB misses
+system.cpu0.itb.fetch_accesses                3859041                       # ITB accesses
+system.cpu0.itb.fetch_acv                         127                       # ITB acv
+system.cpu0.itb.fetch_hits                    3855556                       # ITB hits
+system.cpu0.itb.fetch_misses                     3485                       # ITB misses
+system.cpu0.itb.read_accesses                       0                       # DTB read accesses
+system.cpu0.itb.read_acv                            0                       # DTB read access violations
+system.cpu0.itb.read_hits                           0                       # DTB read hits
+system.cpu0.itb.read_misses                         0                       # DTB read misses
+system.cpu0.itb.write_accesses                      0                       # DTB write accesses
+system.cpu0.itb.write_acv                           0                       # DTB write access violations
+system.cpu0.itb.write_hits                          0                       # DTB write hits
+system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.kern.callpal                       183291                       # number of callpals executed
 system.cpu0.kern.callpal_cserve                     1      0.00%      0.00% # number of callpals executed
 system.cpu0.kern.callpal_wripir                   110      0.06%      0.06% # number of callpals executed
@@ -283,10 +299,14 @@ system.cpu1.dcache.tagsinuse               391.951263                       # Cy
 system.cpu1.dcache.total_refs                 1834544                       # Total number of references to valid blocks.
 system.cpu1.dcache.warmup_cycle          1851267520500                       # Cycle when the warmup percentage was hit.
 system.cpu1.dcache.writebacks                   30848                       # number of writebacks
-system.cpu1.dtb.accesses                       323622                       # DTB accesses
-system.cpu1.dtb.acv                               116                       # DTB access violations
-system.cpu1.dtb.hits                          1914885                       # DTB hits
-system.cpu1.dtb.misses                           3692                       # DTB misses
+system.cpu1.dtb.data_accesses                  323622                       # DTB accesses
+system.cpu1.dtb.data_acv                          116                       # DTB access violations
+system.cpu1.dtb.data_hits                     1914885                       # DTB hits
+system.cpu1.dtb.data_misses                      3692                       # DTB misses
+system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu1.dtb.fetch_acv                           0                       # ITB acv
+system.cpu1.dtb.fetch_hits                          0                       # ITB hits
+system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.read_accesses                  220342                       # DTB read accesses
 system.cpu1.dtb.read_acv                           58                       # DTB read access violations
 system.cpu1.dtb.read_hits                     1163439                       # DTB read hits
@@ -343,10 +363,22 @@ system.cpu1.icache.total_refs                 5832136                       # To
 system.cpu1.icache.warmup_cycle          1868933059000                       # Cycle when the warmup percentage was hit.
 system.cpu1.icache.writebacks                       0                       # number of writebacks
 system.cpu1.idle_fraction                    0.998413                       # Percentage of idle cycles
-system.cpu1.itb.accesses                      1469938                       # ITB accesses
-system.cpu1.itb.acv                                57                       # ITB acv
-system.cpu1.itb.hits                          1468399                       # ITB hits
-system.cpu1.itb.misses                           1539                       # ITB misses
+system.cpu1.itb.data_accesses                       0                       # DTB accesses
+system.cpu1.itb.data_acv                            0                       # DTB access violations
+system.cpu1.itb.data_hits                           0                       # DTB hits
+system.cpu1.itb.data_misses                         0                       # DTB misses
+system.cpu1.itb.fetch_accesses                1469938                       # ITB accesses
+system.cpu1.itb.fetch_acv                          57                       # ITB acv
+system.cpu1.itb.fetch_hits                    1468399                       # ITB hits
+system.cpu1.itb.fetch_misses                     1539                       # ITB misses
+system.cpu1.itb.read_accesses                       0                       # DTB read accesses
+system.cpu1.itb.read_acv                            0                       # DTB read access violations
+system.cpu1.itb.read_hits                           0                       # DTB read hits
+system.cpu1.itb.read_misses                         0                       # DTB read misses
+system.cpu1.itb.write_accesses                      0                       # DTB write accesses
+system.cpu1.itb.write_acv                           0                       # DTB write access violations
+system.cpu1.itb.write_hits                          0                       # DTB write hits
+system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.kern.callpal                        32131                       # number of callpals executed
 system.cpu1.kern.callpal_cserve                     1      0.00%      0.00% # number of callpals executed
 system.cpu1.kern.callpal_wripir                     8      0.02%      0.03% # number of callpals executed
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
index 15e3ec649..511baadf2 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
@@ -97,7 +97,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.toL2Bus.port[2]
 
 [system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu.icache]
@@ -136,7 +136,7 @@ mem_side=system.toL2Bus.port[1]
 type=AlphaInterrupts
 
 [system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu.tracer]
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
index 778e7a3b4..b5820599c 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:15:24
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:15:52
-M5 executing on zizzer
-command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:30:05
+M5 executing on maize
+command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
index 749efa0bc..9c2b9013b 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2844723                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 291452                       # Number of bytes of host memory used
-host_seconds                                    21.11                       # Real time elapsed on the host
-host_tick_rate                            86676065750                       # Simulator tick rate (ticks/s)
+host_inst_rate                                4520875                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 293196                       # Number of bytes of host memory used
+host_seconds                                    13.28                       # Real time elapsed on the host
+host_tick_rate                           137745560508                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    60038305                       # Number of instructions simulated
 sim_seconds                                  1.829332                       # Number of seconds simulated
@@ -67,10 +67,14 @@ system.cpu.dcache.tagsinuse                511.997802                       # Cy
 system.cpu.dcache.total_refs                 14038433                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               10840000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                   428893                       # number of writebacks
-system.cpu.dtb.accesses                       1020787                       # DTB accesses
-system.cpu.dtb.acv                                367                       # DTB access violations
-system.cpu.dtb.hits                          16062925                       # DTB hits
-system.cpu.dtb.misses                           11471                       # DTB misses
+system.cpu.dtb.data_accesses                  1020787                       # DTB accesses
+system.cpu.dtb.data_acv                           367                       # DTB access violations
+system.cpu.dtb.data_hits                     16062925                       # DTB hits
+system.cpu.dtb.data_misses                      11471                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                   728856                       # DTB read accesses
 system.cpu.dtb.read_acv                           210                       # DTB read access violations
 system.cpu.dtb.read_hits                      9710427                       # DTB read hits
@@ -127,10 +131,22 @@ system.cpu.icache.total_refs                 59129922                       # To
 system.cpu.icache.warmup_cycle             9686972500                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                     0.983585                       # Percentage of idle cycles
-system.cpu.itb.accesses                       4979654                       # ITB accesses
-system.cpu.itb.acv                                184                       # ITB acv
-system.cpu.itb.hits                           4974648                       # ITB hits
-system.cpu.itb.misses                            5006                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses                 4979654                       # ITB accesses
+system.cpu.itb.fetch_acv                          184                       # ITB acv
+system.cpu.itb.fetch_hits                     4974648                       # ITB hits
+system.cpu.itb.fetch_misses                      5006                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.kern.callpal                        192180                       # number of callpals executed
 system.cpu.kern.callpal_cserve                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal_wrmces                      1      0.00%      0.00% # number of callpals executed
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index f8e47e1b8..97b65b05c 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
@@ -94,7 +94,7 @@ cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.port[2]
 
 [system.cpu0.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu0.icache]
@@ -133,7 +133,7 @@ mem_side=system.toL2Bus.port[1]
 type=AlphaInterrupts
 
 [system.cpu0.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu0.tracer]
@@ -200,7 +200,7 @@ cpu_side=system.cpu1.dcache_port
 mem_side=system.toL2Bus.port[4]
 
 [system.cpu1.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu1.icache]
@@ -239,7 +239,7 @@ mem_side=system.toL2Bus.port[3]
 type=AlphaInterrupts
 
 [system.cpu1.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu1.tracer]
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
index 6b56db972..3ba004aee 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:15:24
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:15:51
-M5 executing on zizzer
-command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:30:05
+M5 executing on maize
+command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
index 4a6754053..fa370386c 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1382701                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 289788                       # Number of bytes of host memory used
-host_seconds                                    42.97                       # Real time elapsed on the host
-host_tick_rate                            45890646030                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2075727                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 291612                       # Number of bytes of host memory used
+host_seconds                                    28.63                       # Real time elapsed on the host
+host_tick_rate                            68891569254                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    59420593                       # Number of instructions simulated
 sim_seconds                                  1.972135                       # Number of seconds simulated
@@ -95,10 +95,14 @@ system.cpu0.dcache.tagsinuse               503.609177                       # Cy
 system.cpu0.dcache.total_refs                13378935                       # Total number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle              84055000                       # Cycle when the warmup percentage was hit.
 system.cpu0.dcache.writebacks                  403520                       # number of writebacks
-system.cpu0.dtb.accesses                       719860                       # DTB accesses
-system.cpu0.dtb.acv                               289                       # DTB access violations
-system.cpu0.dtb.hits                         14704826                       # DTB hits
-system.cpu0.dtb.misses                           8485                       # DTB misses
+system.cpu0.dtb.data_accesses                  719860                       # DTB accesses
+system.cpu0.dtb.data_acv                          289                       # DTB access violations
+system.cpu0.dtb.data_hits                    14704826                       # DTB hits
+system.cpu0.dtb.data_misses                      8485                       # DTB misses
+system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu0.dtb.fetch_acv                           0                       # ITB acv
+system.cpu0.dtb.fetch_hits                          0                       # ITB hits
+system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.read_accesses                  524201                       # DTB read accesses
 system.cpu0.dtb.read_acv                          174                       # DTB read access violations
 system.cpu0.dtb.read_hits                     8664724                       # DTB read hits
@@ -161,10 +165,22 @@ system.cpu0.icache.total_refs                53248092                       # To
 system.cpu0.icache.warmup_cycle           39455749000                       # Cycle when the warmup percentage was hit.
 system.cpu0.icache.writebacks                       0                       # number of writebacks
 system.cpu0.idle_fraction                    0.933160                       # Percentage of idle cycles
-system.cpu0.itb.accesses                      3953747                       # ITB accesses
-system.cpu0.itb.acv                               143                       # ITB acv
-system.cpu0.itb.hits                          3949906                       # ITB hits
-system.cpu0.itb.misses                           3841                       # ITB misses
+system.cpu0.itb.data_accesses                       0                       # DTB accesses
+system.cpu0.itb.data_acv                            0                       # DTB access violations
+system.cpu0.itb.data_hits                           0                       # DTB hits
+system.cpu0.itb.data_misses                         0                       # DTB misses
+system.cpu0.itb.fetch_accesses                3953747                       # ITB accesses
+system.cpu0.itb.fetch_acv                         143                       # ITB acv
+system.cpu0.itb.fetch_hits                    3949906                       # ITB hits
+system.cpu0.itb.fetch_misses                     3841                       # ITB misses
+system.cpu0.itb.read_accesses                       0                       # DTB read accesses
+system.cpu0.itb.read_acv                            0                       # DTB read access violations
+system.cpu0.itb.read_hits                           0                       # DTB read hits
+system.cpu0.itb.read_misses                         0                       # DTB read misses
+system.cpu0.itb.write_accesses                      0                       # DTB write accesses
+system.cpu0.itb.write_acv                           0                       # DTB write access violations
+system.cpu0.itb.write_hits                          0                       # DTB write hits
+system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.kern.callpal                       188012                       # number of callpals executed
 system.cpu0.kern.callpal_cserve                     1      0.00%      0.00% # number of callpals executed
 system.cpu0.kern.callpal_wripir                    91      0.05%      0.05% # number of callpals executed
@@ -345,10 +361,14 @@ system.cpu1.dcache.tagsinuse               388.878897                       # Cy
 system.cpu1.dcache.total_refs                 1631272                       # Total number of references to valid blocks.
 system.cpu1.dcache.warmup_cycle          1954643578000                       # Cycle when the warmup percentage was hit.
 system.cpu1.dcache.writebacks                   26831                       # number of writebacks
-system.cpu1.dtb.accesses                       302878                       # DTB accesses
-system.cpu1.dtb.acv                                84                       # DTB access violations
-system.cpu1.dtb.hits                          1693851                       # DTB hits
-system.cpu1.dtb.misses                           3106                       # DTB misses
+system.cpu1.dtb.data_accesses                  302878                       # DTB accesses
+system.cpu1.dtb.data_acv                           84                       # DTB access violations
+system.cpu1.dtb.data_hits                     1693851                       # DTB hits
+system.cpu1.dtb.data_misses                      3106                       # DTB misses
+system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu1.dtb.fetch_acv                           0                       # ITB acv
+system.cpu1.dtb.fetch_hits                          0                       # ITB hits
+system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.read_accesses                  205838                       # DTB read accesses
 system.cpu1.dtb.read_acv                           36                       # DTB read access violations
 system.cpu1.dtb.read_hits                     1029710                       # DTB read hits
@@ -411,10 +431,22 @@ system.cpu1.icache.total_refs                 5180706                       # To
 system.cpu1.icache.warmup_cycle          1967880295000                       # Cycle when the warmup percentage was hit.
 system.cpu1.icache.writebacks                       0                       # number of writebacks
 system.cpu1.idle_fraction                    0.994655                       # Percentage of idle cycles
-system.cpu1.itb.accesses                      1397517                       # ITB accesses
-system.cpu1.itb.acv                                41                       # ITB acv
-system.cpu1.itb.hits                          1396271                       # ITB hits
-system.cpu1.itb.misses                           1246                       # ITB misses
+system.cpu1.itb.data_accesses                       0                       # DTB accesses
+system.cpu1.itb.data_acv                            0                       # DTB access violations
+system.cpu1.itb.data_hits                           0                       # DTB hits
+system.cpu1.itb.data_misses                         0                       # DTB misses
+system.cpu1.itb.fetch_accesses                1397517                       # ITB accesses
+system.cpu1.itb.fetch_acv                          41                       # ITB acv
+system.cpu1.itb.fetch_hits                    1396271                       # ITB hits
+system.cpu1.itb.fetch_misses                     1246                       # ITB misses
+system.cpu1.itb.read_accesses                       0                       # DTB read accesses
+system.cpu1.itb.read_acv                            0                       # DTB read access violations
+system.cpu1.itb.read_hits                           0                       # DTB read hits
+system.cpu1.itb.read_misses                         0                       # DTB read misses
+system.cpu1.itb.write_accesses                      0                       # DTB write accesses
+system.cpu1.itb.write_acv                           0                       # DTB write access violations
+system.cpu1.itb.write_hits                          0                       # DTB write hits
+system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.kern.callpal                        29503                       # number of callpals executed
 system.cpu1.kern.callpal_cserve                     1      0.00%      0.00% # number of callpals executed
 system.cpu1.kern.callpal_wripir                     6      0.02%      0.02% # number of callpals executed
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index 468bf0248..a7d96b196 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -94,7 +94,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.toL2Bus.port[2]
 
 [system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu.icache]
@@ -133,7 +133,7 @@ mem_side=system.toL2Bus.port[1]
 type=AlphaInterrupts
 
 [system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu.tracer]
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
index ba86a45b9..0edc8e974 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:15:24
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:15:52
-M5 executing on zizzer
-command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:30:04
+M5 executing on maize
+command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
index cbf231e85..7b42fa0e8 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1953289                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 288556                       # Number of bytes of host memory used
-host_seconds                                    28.78                       # Real time elapsed on the host
-host_tick_rate                            67077404616                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2046881                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 290296                       # Number of bytes of host memory used
+host_seconds                                    27.46                       # Real time elapsed on the host
+host_tick_rate                            70291420604                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    56205703                       # Number of instructions simulated
 sim_seconds                                  1.930165                       # Number of seconds simulated
@@ -95,10 +95,14 @@ system.cpu.dcache.tagsinuse                511.984142                       # Cy
 system.cpu.dcache.total_refs                 14056658                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               84139000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                   430459                       # number of writebacks
-system.cpu.dtb.accesses                       1020784                       # DTB accesses
-system.cpu.dtb.acv                                367                       # DTB access violations
-system.cpu.dtb.hits                          15429793                       # DTB hits
-system.cpu.dtb.misses                           11466                       # DTB misses
+system.cpu.dtb.data_accesses                  1020784                       # DTB accesses
+system.cpu.dtb.data_acv                           367                       # DTB access violations
+system.cpu.dtb.data_hits                     15429793                       # DTB hits
+system.cpu.dtb.data_misses                      11466                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                   728853                       # DTB read accesses
 system.cpu.dtb.read_acv                           210                       # DTB read access violations
 system.cpu.dtb.read_hits                      9069700                       # DTB read hits
@@ -161,10 +165,22 @@ system.cpu.icache.total_refs                 55286436                       # To
 system.cpu.icache.warmup_cycle            39055604000                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                     0.929209                       # Percentage of idle cycles
-system.cpu.itb.accesses                       4982987                       # ITB accesses
-system.cpu.itb.acv                                184                       # ITB acv
-system.cpu.itb.hits                           4977977                       # ITB hits
-system.cpu.itb.misses                            5010                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses                 4982987                       # ITB accesses
+system.cpu.itb.fetch_acv                          184                       # ITB acv
+system.cpu.itb.fetch_hits                     4977977                       # ITB hits
+system.cpu.itb.fetch_misses                      5010                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.kern.callpal                        193221                       # number of callpals executed
 system.cpu.kern.callpal_cserve                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal_wrmces                      1      0.00%      0.00% # number of callpals executed
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
index 014feb13e..d9595cbc3 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
@@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
 icache_port=system.membus.port[1]
 
 [system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu.tracer]
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout
index 103b40a61..b2ea6d6e3 100755
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:22:12
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic -re tests/run.py quick/20.eio-short/alpha/eio/simple-atomic
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:38:04
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 main dictionary has 1245 entries
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
index 1e8dfa007..ca25b214e 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
@@ -1,17 +1,21 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                4171159                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 191588                       # Number of bytes of host memory used
-host_seconds                                     0.12                       # Real time elapsed on the host
-host_tick_rate                             2080999983                       # Simulator tick rate (ticks/s)
+host_inst_rate                                4651388                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 193356                       # Number of bytes of host memory used
+host_seconds                                     0.11                       # Real time elapsed on the host
+host_tick_rate                             2320975678                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                      500001                       # Number of instructions simulated
 sim_seconds                                  0.000250                       # Number of seconds simulated
 sim_ticks                                   250015500                       # Number of ticks simulated
-system.cpu.dtb.accesses                        180793                       # DTB accesses
-system.cpu.dtb.acv                                  0                       # DTB access violations
-system.cpu.dtb.hits                            180775                       # DTB hits
-system.cpu.dtb.misses                              18                       # DTB misses
+system.cpu.dtb.data_accesses                   180793                       # DTB accesses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_hits                       180775                       # DTB hits
+system.cpu.dtb.data_misses                         18                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                   124443                       # DTB read accesses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
 system.cpu.dtb.read_hits                       124435                       # DTB read hits
@@ -21,10 +25,22 @@ system.cpu.dtb.write_acv                            0                       # DT
 system.cpu.dtb.write_hits                       56340                       # DTB write hits
 system.cpu.dtb.write_misses                        10                       # DTB write misses
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                        500032                       # ITB accesses
-system.cpu.itb.acv                                  0                       # ITB acv
-system.cpu.itb.hits                            500019                       # ITB hits
-system.cpu.itb.misses                              13                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses                  500032                       # ITB accesses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_hits                      500019                       # ITB hits
+system.cpu.itb.fetch_misses                        13                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                           500032                       # number of cpu cycles simulated
 system.cpu.num_insts                           500001                       # Number of instructions executed
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
index 84839b10d..c3b0ede0c 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu.l2cache]
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout
index d93e92292..a040a467d 100755
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:22:12
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing -re tests/run.py quick/20.eio-short/alpha/eio/simple-timing
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:34:29
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 main dictionary has 1245 entries
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
index 66e101984..a1d2c7b35 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1619389                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 199040                       # Number of bytes of host memory used
-host_seconds                                     0.31                       # Real time elapsed on the host
-host_tick_rate                             2386410783                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2409922                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 200896                       # Number of bytes of host memory used
+host_seconds                                     0.21                       # Real time elapsed on the host
+host_tick_rate                             3549730180                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                      500001                       # Number of instructions simulated
 sim_seconds                                  0.000737                       # Number of seconds simulated
@@ -71,10 +71,14 @@ system.cpu.dcache.tagsinuse                286.463742                       # Cy
 system.cpu.dcache.total_refs                   180321                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.dtb.accesses                        180793                       # DTB accesses
-system.cpu.dtb.acv                                  0                       # DTB access violations
-system.cpu.dtb.hits                            180775                       # DTB hits
-system.cpu.dtb.misses                              18                       # DTB misses
+system.cpu.dtb.data_accesses                   180793                       # DTB accesses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_hits                       180775                       # DTB hits
+system.cpu.dtb.data_misses                         18                       # DTB misses
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.read_accesses                   124443                       # DTB read accesses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
 system.cpu.dtb.read_hits                       124435                       # DTB read hits
@@ -137,10 +141,22 @@ system.cpu.icache.total_refs                   499617                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.accesses                        500033                       # ITB accesses
-system.cpu.itb.acv                                  0                       # ITB acv
-system.cpu.itb.hits                            500020                       # ITB hits
-system.cpu.itb.misses                              13                       # ITB misses
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.fetch_accesses                  500033                       # ITB accesses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_hits                      500020                       # ITB hits
+system.cpu.itb.fetch_misses                        13                       # ITB misses
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.l2cache.ReadExReq_accesses             139                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
index af926f81c..97cda243a 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
@@ -71,7 +71,7 @@ cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.port[2]
 
 [system.cpu0.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu0.icache]
@@ -107,7 +107,7 @@ cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.port[1]
 
 [system.cpu0.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu0.tracer]
@@ -185,7 +185,7 @@ cpu_side=system.cpu1.dcache_port
 mem_side=system.toL2Bus.port[4]
 
 [system.cpu1.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu1.icache]
@@ -221,7 +221,7 @@ cpu_side=system.cpu1.icache_port
 mem_side=system.toL2Bus.port[3]
 
 [system.cpu1.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu1.tracer]
@@ -299,7 +299,7 @@ cpu_side=system.cpu2.dcache_port
 mem_side=system.toL2Bus.port[6]
 
 [system.cpu2.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu2.icache]
@@ -335,7 +335,7 @@ cpu_side=system.cpu2.icache_port
 mem_side=system.toL2Bus.port[5]
 
 [system.cpu2.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu2.tracer]
@@ -413,7 +413,7 @@ cpu_side=system.cpu3.dcache_port
 mem_side=system.toL2Bus.port[8]
 
 [system.cpu3.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu3.icache]
@@ -449,7 +449,7 @@ cpu_side=system.cpu3.icache_port
 mem_side=system.toL2Bus.port[7]
 
 [system.cpu3.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu3.tracer]
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
index 0c841053d..6504ffb9c 100755
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:22:11
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py quick/30.eio-mp/alpha/eio/simple-atomic-mp
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:38:03
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 main dictionary has 1245 entries
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
index aecd60ac7..9d21b6bf4 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                4658528                       # Simulator instruction rate (inst/s)
-host_mem_usage                                1123612                       # Number of bytes of host memory used
-host_seconds                                     0.43                       # Real time elapsed on the host
-host_tick_rate                              582033733                       # Simulator tick rate (ticks/s)
+host_inst_rate                                4748415                       # Simulator instruction rate (inst/s)
+host_mem_usage                                1125700                       # Number of bytes of host memory used
+host_seconds                                     0.42                       # Real time elapsed on the host
+host_tick_rate                              593193174                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                     2000004                       # Number of instructions simulated
 sim_seconds                                  0.000250                       # Number of seconds simulated
@@ -59,10 +59,14 @@ system.cpu0.dcache.tagsinuse               276.872320                       # Cy
 system.cpu0.dcache.total_refs                  180312                       # Total number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu0.dcache.writebacks                      29                       # number of writebacks
-system.cpu0.dtb.accesses                       180793                       # DTB accesses
-system.cpu0.dtb.acv                                 0                       # DTB access violations
-system.cpu0.dtb.hits                           180775                       # DTB hits
-system.cpu0.dtb.misses                             18                       # DTB misses
+system.cpu0.dtb.data_accesses                  180793                       # DTB accesses
+system.cpu0.dtb.data_acv                            0                       # DTB access violations
+system.cpu0.dtb.data_hits                      180775                       # DTB hits
+system.cpu0.dtb.data_misses                        18                       # DTB misses
+system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu0.dtb.fetch_acv                           0                       # ITB acv
+system.cpu0.dtb.fetch_hits                          0                       # ITB hits
+system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.read_accesses                  124443                       # DTB read accesses
 system.cpu0.dtb.read_acv                            0                       # DTB read access violations
 system.cpu0.dtb.read_hits                      124435                       # DTB read hits
@@ -119,10 +123,22 @@ system.cpu0.icache.total_refs                  499556                       # To
 system.cpu0.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu0.icache.writebacks                       0                       # number of writebacks
 system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu0.itb.accesses                       500032                       # ITB accesses
-system.cpu0.itb.acv                                 0                       # ITB acv
-system.cpu0.itb.hits                           500019                       # ITB hits
-system.cpu0.itb.misses                             13                       # ITB misses
+system.cpu0.itb.data_accesses                       0                       # DTB accesses
+system.cpu0.itb.data_acv                            0                       # DTB access violations
+system.cpu0.itb.data_hits                           0                       # DTB hits
+system.cpu0.itb.data_misses                         0                       # DTB misses
+system.cpu0.itb.fetch_accesses                 500032                       # ITB accesses
+system.cpu0.itb.fetch_acv                           0                       # ITB acv
+system.cpu0.itb.fetch_hits                     500019                       # ITB hits
+system.cpu0.itb.fetch_misses                       13                       # ITB misses
+system.cpu0.itb.read_accesses                       0                       # DTB read accesses
+system.cpu0.itb.read_acv                            0                       # DTB read access violations
+system.cpu0.itb.read_hits                           0                       # DTB read hits
+system.cpu0.itb.read_misses                         0                       # DTB read misses
+system.cpu0.itb.write_accesses                      0                       # DTB write accesses
+system.cpu0.itb.write_acv                           0                       # DTB write access violations
+system.cpu0.itb.write_hits                          0                       # DTB write hits
+system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu0.numCycles                          500032                       # number of cpu cycles simulated
 system.cpu0.num_insts                          500001                       # Number of instructions executed
@@ -179,10 +195,14 @@ system.cpu1.dcache.tagsinuse               276.872320                       # Cy
 system.cpu1.dcache.total_refs                  180312                       # Total number of references to valid blocks.
 system.cpu1.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu1.dcache.writebacks                      29                       # number of writebacks
-system.cpu1.dtb.accesses                       180793                       # DTB accesses
-system.cpu1.dtb.acv                                 0                       # DTB access violations
-system.cpu1.dtb.hits                           180775                       # DTB hits
-system.cpu1.dtb.misses                             18                       # DTB misses
+system.cpu1.dtb.data_accesses                  180793                       # DTB accesses
+system.cpu1.dtb.data_acv                            0                       # DTB access violations
+system.cpu1.dtb.data_hits                      180775                       # DTB hits
+system.cpu1.dtb.data_misses                        18                       # DTB misses
+system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu1.dtb.fetch_acv                           0                       # ITB acv
+system.cpu1.dtb.fetch_hits                          0                       # ITB hits
+system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.read_accesses                  124443                       # DTB read accesses
 system.cpu1.dtb.read_acv                            0                       # DTB read access violations
 system.cpu1.dtb.read_hits                      124435                       # DTB read hits
@@ -239,10 +259,22 @@ system.cpu1.icache.total_refs                  499556                       # To
 system.cpu1.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu1.icache.writebacks                       0                       # number of writebacks
 system.cpu1.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu1.itb.accesses                       500032                       # ITB accesses
-system.cpu1.itb.acv                                 0                       # ITB acv
-system.cpu1.itb.hits                           500019                       # ITB hits
-system.cpu1.itb.misses                             13                       # ITB misses
+system.cpu1.itb.data_accesses                       0                       # DTB accesses
+system.cpu1.itb.data_acv                            0                       # DTB access violations
+system.cpu1.itb.data_hits                           0                       # DTB hits
+system.cpu1.itb.data_misses                         0                       # DTB misses
+system.cpu1.itb.fetch_accesses                 500032                       # ITB accesses
+system.cpu1.itb.fetch_acv                           0                       # ITB acv
+system.cpu1.itb.fetch_hits                     500019                       # ITB hits
+system.cpu1.itb.fetch_misses                       13                       # ITB misses
+system.cpu1.itb.read_accesses                       0                       # DTB read accesses
+system.cpu1.itb.read_acv                            0                       # DTB read access violations
+system.cpu1.itb.read_hits                           0                       # DTB read hits
+system.cpu1.itb.read_misses                         0                       # DTB read misses
+system.cpu1.itb.write_accesses                      0                       # DTB write accesses
+system.cpu1.itb.write_acv                           0                       # DTB write access violations
+system.cpu1.itb.write_hits                          0                       # DTB write hits
+system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu1.numCycles                          500032                       # number of cpu cycles simulated
 system.cpu1.num_insts                          500001                       # Number of instructions executed
@@ -299,10 +331,14 @@ system.cpu2.dcache.tagsinuse               276.872320                       # Cy
 system.cpu2.dcache.total_refs                  180312                       # Total number of references to valid blocks.
 system.cpu2.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu2.dcache.writebacks                      29                       # number of writebacks
-system.cpu2.dtb.accesses                       180793                       # DTB accesses
-system.cpu2.dtb.acv                                 0                       # DTB access violations
-system.cpu2.dtb.hits                           180775                       # DTB hits
-system.cpu2.dtb.misses                             18                       # DTB misses
+system.cpu2.dtb.data_accesses                  180793                       # DTB accesses
+system.cpu2.dtb.data_acv                            0                       # DTB access violations
+system.cpu2.dtb.data_hits                      180775                       # DTB hits
+system.cpu2.dtb.data_misses                        18                       # DTB misses
+system.cpu2.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu2.dtb.fetch_acv                           0                       # ITB acv
+system.cpu2.dtb.fetch_hits                          0                       # ITB hits
+system.cpu2.dtb.fetch_misses                        0                       # ITB misses
 system.cpu2.dtb.read_accesses                  124443                       # DTB read accesses
 system.cpu2.dtb.read_acv                            0                       # DTB read access violations
 system.cpu2.dtb.read_hits                      124435                       # DTB read hits
@@ -359,10 +395,22 @@ system.cpu2.icache.total_refs                  499556                       # To
 system.cpu2.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu2.icache.writebacks                       0                       # number of writebacks
 system.cpu2.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu2.itb.accesses                       500032                       # ITB accesses
-system.cpu2.itb.acv                                 0                       # ITB acv
-system.cpu2.itb.hits                           500019                       # ITB hits
-system.cpu2.itb.misses                             13                       # ITB misses
+system.cpu2.itb.data_accesses                       0                       # DTB accesses
+system.cpu2.itb.data_acv                            0                       # DTB access violations
+system.cpu2.itb.data_hits                           0                       # DTB hits
+system.cpu2.itb.data_misses                         0                       # DTB misses
+system.cpu2.itb.fetch_accesses                 500032                       # ITB accesses
+system.cpu2.itb.fetch_acv                           0                       # ITB acv
+system.cpu2.itb.fetch_hits                     500019                       # ITB hits
+system.cpu2.itb.fetch_misses                       13                       # ITB misses
+system.cpu2.itb.read_accesses                       0                       # DTB read accesses
+system.cpu2.itb.read_acv                            0                       # DTB read access violations
+system.cpu2.itb.read_hits                           0                       # DTB read hits
+system.cpu2.itb.read_misses                         0                       # DTB read misses
+system.cpu2.itb.write_accesses                      0                       # DTB write accesses
+system.cpu2.itb.write_acv                           0                       # DTB write access violations
+system.cpu2.itb.write_hits                          0                       # DTB write hits
+system.cpu2.itb.write_misses                        0                       # DTB write misses
 system.cpu2.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu2.numCycles                          500032                       # number of cpu cycles simulated
 system.cpu2.num_insts                          500001                       # Number of instructions executed
@@ -419,10 +467,14 @@ system.cpu3.dcache.tagsinuse               276.872320                       # Cy
 system.cpu3.dcache.total_refs                  180312                       # Total number of references to valid blocks.
 system.cpu3.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu3.dcache.writebacks                      29                       # number of writebacks
-system.cpu3.dtb.accesses                       180793                       # DTB accesses
-system.cpu3.dtb.acv                                 0                       # DTB access violations
-system.cpu3.dtb.hits                           180775                       # DTB hits
-system.cpu3.dtb.misses                             18                       # DTB misses
+system.cpu3.dtb.data_accesses                  180793                       # DTB accesses
+system.cpu3.dtb.data_acv                            0                       # DTB access violations
+system.cpu3.dtb.data_hits                      180775                       # DTB hits
+system.cpu3.dtb.data_misses                        18                       # DTB misses
+system.cpu3.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu3.dtb.fetch_acv                           0                       # ITB acv
+system.cpu3.dtb.fetch_hits                          0                       # ITB hits
+system.cpu3.dtb.fetch_misses                        0                       # ITB misses
 system.cpu3.dtb.read_accesses                  124443                       # DTB read accesses
 system.cpu3.dtb.read_acv                            0                       # DTB read access violations
 system.cpu3.dtb.read_hits                      124435                       # DTB read hits
@@ -479,10 +531,22 @@ system.cpu3.icache.total_refs                  499556                       # To
 system.cpu3.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu3.icache.writebacks                       0                       # number of writebacks
 system.cpu3.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu3.itb.accesses                       500032                       # ITB accesses
-system.cpu3.itb.acv                                 0                       # ITB acv
-system.cpu3.itb.hits                           500019                       # ITB hits
-system.cpu3.itb.misses                             13                       # ITB misses
+system.cpu3.itb.data_accesses                       0                       # DTB accesses
+system.cpu3.itb.data_acv                            0                       # DTB access violations
+system.cpu3.itb.data_hits                           0                       # DTB hits
+system.cpu3.itb.data_misses                         0                       # DTB misses
+system.cpu3.itb.fetch_accesses                 500032                       # ITB accesses
+system.cpu3.itb.fetch_acv                           0                       # ITB acv
+system.cpu3.itb.fetch_hits                     500019                       # ITB hits
+system.cpu3.itb.fetch_misses                       13                       # ITB misses
+system.cpu3.itb.read_accesses                       0                       # DTB read accesses
+system.cpu3.itb.read_acv                            0                       # DTB read access violations
+system.cpu3.itb.read_hits                           0                       # DTB read hits
+system.cpu3.itb.read_misses                         0                       # DTB read misses
+system.cpu3.itb.write_accesses                      0                       # DTB write accesses
+system.cpu3.itb.write_acv                           0                       # DTB write access violations
+system.cpu3.itb.write_hits                          0                       # DTB write hits
+system.cpu3.itb.write_misses                        0                       # DTB write misses
 system.cpu3.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu3.numCycles                          500032                       # number of cpu cycles simulated
 system.cpu3.num_insts                          500001                       # Number of instructions executed
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
index 2d269877c..e871dcaff 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.port[2]
 
 [system.cpu0.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu0.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.port[1]
 
 [system.cpu0.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu0.tracer]
@@ -179,7 +179,7 @@ cpu_side=system.cpu1.dcache_port
 mem_side=system.toL2Bus.port[4]
 
 [system.cpu1.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu1.icache]
@@ -215,7 +215,7 @@ cpu_side=system.cpu1.icache_port
 mem_side=system.toL2Bus.port[3]
 
 [system.cpu1.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu1.tracer]
@@ -290,7 +290,7 @@ cpu_side=system.cpu2.dcache_port
 mem_side=system.toL2Bus.port[6]
 
 [system.cpu2.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu2.icache]
@@ -326,7 +326,7 @@ cpu_side=system.cpu2.icache_port
 mem_side=system.toL2Bus.port[5]
 
 [system.cpu2.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu2.tracer]
@@ -401,7 +401,7 @@ cpu_side=system.cpu3.dcache_port
 mem_side=system.toL2Bus.port[8]
 
 [system.cpu3.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [system.cpu3.icache]
@@ -437,7 +437,7 @@ cpu_side=system.cpu3.icache_port
 mem_side=system.toL2Bus.port[7]
 
 [system.cpu3.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [system.cpu3.tracer]
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
index edab14950..974e2e1d0 100755
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:22:12
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py quick/30.eio-mp/alpha/eio/simple-timing-mp
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:44:10
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 main dictionary has 1245 entries
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
index 1fb750134..78b7525ed 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1521087                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 206108                       # Number of bytes of host memory used
-host_seconds                                     1.32                       # Real time elapsed on the host
-host_tick_rate                              561475161                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2309817                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 208124                       # Number of bytes of host memory used
+host_seconds                                     0.87                       # Real time elapsed on the host
+host_tick_rate                              852520777                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                     1999941                       # Number of instructions simulated
 sim_seconds                                  0.000738                       # Number of seconds simulated
@@ -71,10 +71,14 @@ system.cpu0.dcache.tagsinuse               272.914158                       # Cy
 system.cpu0.dcache.total_refs                  180308                       # Total number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu0.dcache.writebacks                      29                       # number of writebacks
-system.cpu0.dtb.accesses                       180789                       # DTB accesses
-system.cpu0.dtb.acv                                 0                       # DTB access violations
-system.cpu0.dtb.hits                           180771                       # DTB hits
-system.cpu0.dtb.misses                             18                       # DTB misses
+system.cpu0.dtb.data_accesses                  180789                       # DTB accesses
+system.cpu0.dtb.data_acv                            0                       # DTB access violations
+system.cpu0.dtb.data_hits                      180771                       # DTB hits
+system.cpu0.dtb.data_misses                        18                       # DTB misses
+system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu0.dtb.fetch_acv                           0                       # ITB acv
+system.cpu0.dtb.fetch_hits                          0                       # ITB hits
+system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.read_accesses                  124440                       # DTB read accesses
 system.cpu0.dtb.read_acv                            0                       # DTB read access violations
 system.cpu0.dtb.read_hits                      124432                       # DTB read hits
@@ -137,10 +141,22 @@ system.cpu0.icache.total_refs                  499537                       # To
 system.cpu0.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu0.icache.writebacks                       0                       # number of writebacks
 system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu0.itb.accesses                       500013                       # ITB accesses
-system.cpu0.itb.acv                                 0                       # ITB acv
-system.cpu0.itb.hits                           500000                       # ITB hits
-system.cpu0.itb.misses                             13                       # ITB misses
+system.cpu0.itb.data_accesses                       0                       # DTB accesses
+system.cpu0.itb.data_acv                            0                       # DTB access violations
+system.cpu0.itb.data_hits                           0                       # DTB hits
+system.cpu0.itb.data_misses                         0                       # DTB misses
+system.cpu0.itb.fetch_accesses                 500013                       # ITB accesses
+system.cpu0.itb.fetch_acv                           0                       # ITB acv
+system.cpu0.itb.fetch_hits                     500000                       # ITB hits
+system.cpu0.itb.fetch_misses                       13                       # ITB misses
+system.cpu0.itb.read_accesses                       0                       # DTB read accesses
+system.cpu0.itb.read_acv                            0                       # DTB read access violations
+system.cpu0.itb.read_hits                           0                       # DTB read hits
+system.cpu0.itb.read_misses                         0                       # DTB read misses
+system.cpu0.itb.write_accesses                      0                       # DTB write accesses
+system.cpu0.itb.write_acv                           0                       # DTB write access violations
+system.cpu0.itb.write_hits                          0                       # DTB write hits
+system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu0.numCycles                         1476774                       # number of cpu cycles simulated
 system.cpu0.num_insts                          499981                       # Number of instructions executed
@@ -209,10 +225,14 @@ system.cpu1.dcache.tagsinuse               272.910830                       # Cy
 system.cpu1.dcache.total_refs                  180305                       # Total number of references to valid blocks.
 system.cpu1.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu1.dcache.writebacks                      29                       # number of writebacks
-system.cpu1.dtb.accesses                       180786                       # DTB accesses
-system.cpu1.dtb.acv                                 0                       # DTB access violations
-system.cpu1.dtb.hits                           180768                       # DTB hits
-system.cpu1.dtb.misses                             18                       # DTB misses
+system.cpu1.dtb.data_accesses                  180786                       # DTB accesses
+system.cpu1.dtb.data_acv                            0                       # DTB access violations
+system.cpu1.dtb.data_hits                      180768                       # DTB hits
+system.cpu1.dtb.data_misses                        18                       # DTB misses
+system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu1.dtb.fetch_acv                           0                       # ITB acv
+system.cpu1.dtb.fetch_hits                          0                       # ITB hits
+system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.read_accesses                  124437                       # DTB read accesses
 system.cpu1.dtb.read_acv                            0                       # DTB read access violations
 system.cpu1.dtb.read_hits                      124429                       # DTB read hits
@@ -275,10 +295,22 @@ system.cpu1.icache.total_refs                  499531                       # To
 system.cpu1.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu1.icache.writebacks                       0                       # number of writebacks
 system.cpu1.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu1.itb.accesses                       500007                       # ITB accesses
-system.cpu1.itb.acv                                 0                       # ITB acv
-system.cpu1.itb.hits                           499994                       # ITB hits
-system.cpu1.itb.misses                             13                       # ITB misses
+system.cpu1.itb.data_accesses                       0                       # DTB accesses
+system.cpu1.itb.data_acv                            0                       # DTB access violations
+system.cpu1.itb.data_hits                           0                       # DTB hits
+system.cpu1.itb.data_misses                         0                       # DTB misses
+system.cpu1.itb.fetch_accesses                 500007                       # ITB accesses
+system.cpu1.itb.fetch_acv                           0                       # ITB acv
+system.cpu1.itb.fetch_hits                     499994                       # ITB hits
+system.cpu1.itb.fetch_misses                       13                       # ITB misses
+system.cpu1.itb.read_accesses                       0                       # DTB read accesses
+system.cpu1.itb.read_acv                            0                       # DTB read access violations
+system.cpu1.itb.read_hits                           0                       # DTB read hits
+system.cpu1.itb.read_misses                         0                       # DTB read misses
+system.cpu1.itb.write_accesses                      0                       # DTB write accesses
+system.cpu1.itb.write_acv                           0                       # DTB write access violations
+system.cpu1.itb.write_hits                          0                       # DTB write hits
+system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu1.numCycles                         1476774                       # number of cpu cycles simulated
 system.cpu1.num_insts                          499975                       # Number of instructions executed
@@ -347,10 +379,14 @@ system.cpu2.dcache.tagsinuse               272.921161                       # Cy
 system.cpu2.dcache.total_refs                  180312                       # Total number of references to valid blocks.
 system.cpu2.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu2.dcache.writebacks                      29                       # number of writebacks
-system.cpu2.dtb.accesses                       180793                       # DTB accesses
-system.cpu2.dtb.acv                                 0                       # DTB access violations
-system.cpu2.dtb.hits                           180775                       # DTB hits
-system.cpu2.dtb.misses                             18                       # DTB misses
+system.cpu2.dtb.data_accesses                  180793                       # DTB accesses
+system.cpu2.dtb.data_acv                            0                       # DTB access violations
+system.cpu2.dtb.data_hits                      180775                       # DTB hits
+system.cpu2.dtb.data_misses                        18                       # DTB misses
+system.cpu2.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu2.dtb.fetch_acv                           0                       # ITB acv
+system.cpu2.dtb.fetch_hits                          0                       # ITB hits
+system.cpu2.dtb.fetch_misses                        0                       # ITB misses
 system.cpu2.dtb.read_accesses                  124443                       # DTB read accesses
 system.cpu2.dtb.read_acv                            0                       # DTB read access violations
 system.cpu2.dtb.read_hits                      124435                       # DTB read hits
@@ -413,10 +449,22 @@ system.cpu2.icache.total_refs                  499557                       # To
 system.cpu2.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu2.icache.writebacks                       0                       # number of writebacks
 system.cpu2.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu2.itb.accesses                       500033                       # ITB accesses
-system.cpu2.itb.acv                                 0                       # ITB acv
-system.cpu2.itb.hits                           500020                       # ITB hits
-system.cpu2.itb.misses                             13                       # ITB misses
+system.cpu2.itb.data_accesses                       0                       # DTB accesses
+system.cpu2.itb.data_acv                            0                       # DTB access violations
+system.cpu2.itb.data_hits                           0                       # DTB hits
+system.cpu2.itb.data_misses                         0                       # DTB misses
+system.cpu2.itb.fetch_accesses                 500033                       # ITB accesses
+system.cpu2.itb.fetch_acv                           0                       # ITB acv
+system.cpu2.itb.fetch_hits                     500020                       # ITB hits
+system.cpu2.itb.fetch_misses                       13                       # ITB misses
+system.cpu2.itb.read_accesses                       0                       # DTB read accesses
+system.cpu2.itb.read_acv                            0                       # DTB read access violations
+system.cpu2.itb.read_hits                           0                       # DTB read hits
+system.cpu2.itb.read_misses                         0                       # DTB read misses
+system.cpu2.itb.write_accesses                      0                       # DTB write accesses
+system.cpu2.itb.write_acv                           0                       # DTB write access violations
+system.cpu2.itb.write_hits                          0                       # DTB write hits
+system.cpu2.itb.write_misses                        0                       # DTB write misses
 system.cpu2.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu2.numCycles                         1476774                       # number of cpu cycles simulated
 system.cpu2.num_insts                          500001                       # Number of instructions executed
@@ -485,10 +533,14 @@ system.cpu3.dcache.tagsinuse               272.916356                       # Cy
 system.cpu3.dcache.total_refs                  180309                       # Total number of references to valid blocks.
 system.cpu3.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu3.dcache.writebacks                      29                       # number of writebacks
-system.cpu3.dtb.accesses                       180790                       # DTB accesses
-system.cpu3.dtb.acv                                 0                       # DTB access violations
-system.cpu3.dtb.hits                           180772                       # DTB hits
-system.cpu3.dtb.misses                             18                       # DTB misses
+system.cpu3.dtb.data_accesses                  180790                       # DTB accesses
+system.cpu3.dtb.data_acv                            0                       # DTB access violations
+system.cpu3.dtb.data_hits                      180772                       # DTB hits
+system.cpu3.dtb.data_misses                        18                       # DTB misses
+system.cpu3.dtb.fetch_accesses                      0                       # ITB accesses
+system.cpu3.dtb.fetch_acv                           0                       # ITB acv
+system.cpu3.dtb.fetch_hits                          0                       # ITB hits
+system.cpu3.dtb.fetch_misses                        0                       # ITB misses
 system.cpu3.dtb.read_accesses                  124441                       # DTB read accesses
 system.cpu3.dtb.read_acv                            0                       # DTB read access violations
 system.cpu3.dtb.read_hits                      124433                       # DTB read hits
@@ -551,10 +603,22 @@ system.cpu3.icache.total_refs                  499540                       # To
 system.cpu3.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu3.icache.writebacks                       0                       # number of writebacks
 system.cpu3.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu3.itb.accesses                       500016                       # ITB accesses
-system.cpu3.itb.acv                                 0                       # ITB acv
-system.cpu3.itb.hits                           500003                       # ITB hits
-system.cpu3.itb.misses                             13                       # ITB misses
+system.cpu3.itb.data_accesses                       0                       # DTB accesses
+system.cpu3.itb.data_acv                            0                       # DTB access violations
+system.cpu3.itb.data_hits                           0                       # DTB hits
+system.cpu3.itb.data_misses                         0                       # DTB misses
+system.cpu3.itb.fetch_accesses                 500016                       # ITB accesses
+system.cpu3.itb.fetch_acv                           0                       # ITB acv
+system.cpu3.itb.fetch_hits                     500003                       # ITB hits
+system.cpu3.itb.fetch_misses                       13                       # ITB misses
+system.cpu3.itb.read_accesses                       0                       # DTB read accesses
+system.cpu3.itb.read_acv                            0                       # DTB read access violations
+system.cpu3.itb.read_hits                           0                       # DTB read hits
+system.cpu3.itb.read_misses                         0                       # DTB read misses
+system.cpu3.itb.write_accesses                      0                       # DTB write accesses
+system.cpu3.itb.write_acv                           0                       # DTB write access violations
+system.cpu3.itb.write_hits                          0                       # DTB write hits
+system.cpu3.itb.write_misses                        0                       # DTB write misses
 system.cpu3.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu3.numCycles                         1476774                       # number of cpu cycles simulated
 system.cpu3.num_insts                          499984                       # Number of instructions executed
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout
index 9d66255a0..84934c75f 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:22:11
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest -re tests/run.py quick/50.memtest/alpha/linux/memtest
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:34:30
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 268915439 because maximum number of loads reached
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt
index 7f0400045..2fa4194ff 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt
@@ -1,8 +1,8 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 326140                       # Number of bytes of host memory used
-host_seconds                                   207.97                       # Real time elapsed on the host
-host_tick_rate                                1293031                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 328212                       # Number of bytes of host memory used
+host_seconds                                   135.65                       # Real time elapsed on the host
+host_tick_rate                                1982429                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_seconds                                  0.000269                       # Number of seconds simulated
 sim_ticks                                   268915439                       # Number of ticks simulated
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
index a2a52df64..42e1d38a7 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
@@ -14,7 +14,7 @@ kernel=/dist/m5/system/binaries/vmlinux
 mem_mode=atomic
 pal=/dist/m5/system/binaries/ts_osfpal
 physmem=drivesys.physmem
-readfile=/z/stever/hg/m5/configs/boot/netperf-server.rcS
+readfile=/n/blue/z/binkert/work/m5/work/configs/boot/netperf-server.rcS
 symbolfile=
 system_rev=1024
 system_type=34
@@ -65,14 +65,14 @@ dcache_port=drivesys.membus.port[3]
 icache_port=drivesys.membus.port[2]
 
 [drivesys.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [drivesys.cpu.interrupts]
 type=AlphaInterrupts
 
 [drivesys.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [drivesys.cpu.tracer]
@@ -718,7 +718,7 @@ kernel=/dist/m5/system/binaries/vmlinux
 mem_mode=atomic
 pal=/dist/m5/system/binaries/ts_osfpal
 physmem=testsys.physmem
-readfile=/z/stever/hg/m5/configs/boot/netperf-stream-client.rcS
+readfile=/n/blue/z/binkert/work/m5/work/configs/boot/netperf-stream-client.rcS
 symbolfile=
 system_rev=1024
 system_type=34
@@ -769,14 +769,14 @@ dcache_port=testsys.membus.port[3]
 icache_port=testsys.membus.port[2]
 
 [testsys.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
 size=64
 
 [testsys.cpu.interrupts]
 type=AlphaInterrupts
 
 [testsys.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
 size=48
 
 [testsys.cpu.tracer]
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
index 70f17d877..69dfeb8ac 100755
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:15:24
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:15:51
-M5 executing on zizzer
-command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
+M5 compiled Apr  8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr  8 2009 12:30:05
+M5 executing on maize
+command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: kernel located at: /dist/m5/system/binaries/vmlinux
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
index 267fa9175..f97003767 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
@@ -1,9 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-drivesys.cpu.dtb.accesses                      401302                       # DTB accesses
-drivesys.cpu.dtb.acv                               40                       # DTB access violations
-drivesys.cpu.dtb.hits                          624235                       # DTB hits
-drivesys.cpu.dtb.misses                           569                       # DTB misses
+drivesys.cpu.dtb.data_accesses                 401302                       # DTB accesses
+drivesys.cpu.dtb.data_acv                          40                       # DTB access violations
+drivesys.cpu.dtb.data_hits                     624235                       # DTB hits
+drivesys.cpu.dtb.data_misses                      569                       # DTB misses
+drivesys.cpu.dtb.fetch_accesses                     0                       # ITB accesses
+drivesys.cpu.dtb.fetch_acv                          0                       # ITB acv
+drivesys.cpu.dtb.fetch_hits                         0                       # ITB hits
+drivesys.cpu.dtb.fetch_misses                       0                       # ITB misses
 drivesys.cpu.dtb.read_accesses                 268057                       # DTB read accesses
 drivesys.cpu.dtb.read_acv                          30                       # DTB read access violations
 drivesys.cpu.dtb.read_hits                     393500                       # DTB read hits
@@ -13,10 +17,22 @@ drivesys.cpu.dtb.write_acv                         10                       # DT
 drivesys.cpu.dtb.write_hits                    230735                       # DTB write hits
 drivesys.cpu.dtb.write_misses                      82                       # DTB write misses
 drivesys.cpu.idle_fraction                   1.000000                       # Percentage of idle cycles
-drivesys.cpu.itb.accesses                     1337980                       # ITB accesses
-drivesys.cpu.itb.acv                               22                       # ITB acv
-drivesys.cpu.itb.hits                         1337786                       # ITB hits
-drivesys.cpu.itb.misses                           194                       # ITB misses
+drivesys.cpu.itb.data_accesses                      0                       # DTB accesses
+drivesys.cpu.itb.data_acv                           0                       # DTB access violations
+drivesys.cpu.itb.data_hits                          0                       # DTB hits
+drivesys.cpu.itb.data_misses                        0                       # DTB misses
+drivesys.cpu.itb.fetch_accesses               1337980                       # ITB accesses
+drivesys.cpu.itb.fetch_acv                         22                       # ITB acv
+drivesys.cpu.itb.fetch_hits                   1337786                       # ITB hits
+drivesys.cpu.itb.fetch_misses                     194                       # ITB misses
+drivesys.cpu.itb.read_accesses                      0                       # DTB read accesses
+drivesys.cpu.itb.read_acv                           0                       # DTB read access violations
+drivesys.cpu.itb.read_hits                          0                       # DTB read hits
+drivesys.cpu.itb.read_misses                        0                       # DTB read misses
+drivesys.cpu.itb.write_accesses                     0                       # DTB write accesses
+drivesys.cpu.itb.write_acv                          0                       # DTB write access violations
+drivesys.cpu.itb.write_hits                         0                       # DTB write hits
+drivesys.cpu.itb.write_misses                       0                       # DTB write misses
 drivesys.cpu.kern.callpal                        4443                       # number of callpals executed
 drivesys.cpu.kern.callpal_swpctx                   70      1.58%      1.58% # number of callpals executed
 drivesys.cpu.kern.callpal_tbi                       5      0.11%      1.69% # number of callpals executed
@@ -139,18 +155,22 @@ drivesys.tsunami.ethernet.txPPS                    25                       # Pa
 drivesys.tsunami.ethernet.txPackets                 5                       # Number of Packets Transmitted
 drivesys.tsunami.ethernet.txTcpChecksums            2                       # Number of tx TCP Checksums done by device
 drivesys.tsunami.ethernet.txUdpChecksums            0                       # Number of tx UDP Checksums done by device
-host_inst_rate                              151383583                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 478624                       # Number of bytes of host memory used
-host_seconds                                     1.81                       # Real time elapsed on the host
-host_tick_rate                           110738300112                       # Simulator tick rate (ticks/s)
+host_inst_rate                              239279638                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 480276                       # Number of bytes of host memory used
+host_seconds                                     1.14                       # Real time elapsed on the host
+host_tick_rate                           175028279617                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   273374833                       # Number of instructions simulated
 sim_seconds                                  0.200001                       # Number of seconds simulated
 sim_ticks                                200000789468                       # Number of ticks simulated
-testsys.cpu.dtb.accesses                       335402                       # DTB accesses
-testsys.cpu.dtb.acv                               161                       # DTB access violations
-testsys.cpu.dtb.hits                          1163288                       # DTB hits
-testsys.cpu.dtb.misses                           3815                       # DTB misses
+testsys.cpu.dtb.data_accesses                  335402                       # DTB accesses
+testsys.cpu.dtb.data_acv                          161                       # DTB access violations
+testsys.cpu.dtb.data_hits                     1163288                       # DTB hits
+testsys.cpu.dtb.data_misses                      3815                       # DTB misses
+testsys.cpu.dtb.fetch_accesses                      0                       # ITB accesses
+testsys.cpu.dtb.fetch_acv                           0                       # ITB acv
+testsys.cpu.dtb.fetch_hits                          0                       # ITB hits
+testsys.cpu.dtb.fetch_misses                        0                       # ITB misses
 testsys.cpu.dtb.read_accesses                  225414                       # DTB read accesses
 testsys.cpu.dtb.read_acv                           80                       # DTB read access violations
 testsys.cpu.dtb.read_hits                      658435                       # DTB read hits
@@ -160,10 +180,22 @@ testsys.cpu.dtb.write_acv                          81                       # DT
 testsys.cpu.dtb.write_hits                     504853                       # DTB write hits
 testsys.cpu.dtb.write_misses                      528                       # DTB write misses
 testsys.cpu.idle_fraction                    0.999999                       # Percentage of idle cycles
-testsys.cpu.itb.accesses                      1249822                       # ITB accesses
-testsys.cpu.itb.acv                                69                       # ITB acv
-testsys.cpu.itb.hits                          1248325                       # ITB hits
-testsys.cpu.itb.misses                           1497                       # ITB misses
+testsys.cpu.itb.data_accesses                       0                       # DTB accesses
+testsys.cpu.itb.data_acv                            0                       # DTB access violations
+testsys.cpu.itb.data_hits                           0                       # DTB hits
+testsys.cpu.itb.data_misses                         0                       # DTB misses
+testsys.cpu.itb.fetch_accesses                1249822                       # ITB accesses
+testsys.cpu.itb.fetch_acv                          69                       # ITB acv
+testsys.cpu.itb.fetch_hits                    1248325                       # ITB hits
+testsys.cpu.itb.fetch_misses                     1497                       # ITB misses
+testsys.cpu.itb.read_accesses                       0                       # DTB read accesses
+testsys.cpu.itb.read_acv                            0                       # DTB read access violations
+testsys.cpu.itb.read_hits                           0                       # DTB read hits
+testsys.cpu.itb.read_misses                         0                       # DTB read misses
+testsys.cpu.itb.write_accesses                      0                       # DTB write accesses
+testsys.cpu.itb.write_acv                           0                       # DTB write access violations
+testsys.cpu.itb.write_hits                          0                       # DTB write hits
+testsys.cpu.itb.write_misses                        0                       # DTB write misses
 testsys.cpu.kern.callpal                        13122                       # number of callpals executed
 testsys.cpu.kern.callpal_swpctx                   438      3.34%      3.34% # number of callpals executed
 testsys.cpu.kern.callpal_tbi                       20      0.15%      3.49% # number of callpals executed
@@ -300,10 +332,14 @@ testsys.tsunami.ethernet.txUdpChecksums             0                       # Nu
 ---------- End Simulation Statistics   ----------
 
 ---------- Begin Simulation Statistics ----------
-drivesys.cpu.dtb.accesses                           0                       # DTB accesses
-drivesys.cpu.dtb.acv                                0                       # DTB access violations
-drivesys.cpu.dtb.hits                               0                       # DTB hits
-drivesys.cpu.dtb.misses                             0                       # DTB misses
+drivesys.cpu.dtb.data_accesses                      0                       # DTB accesses
+drivesys.cpu.dtb.data_acv                           0                       # DTB access violations
+drivesys.cpu.dtb.data_hits                          0                       # DTB hits
+drivesys.cpu.dtb.data_misses                        0                       # DTB misses
+drivesys.cpu.dtb.fetch_accesses                     0                       # ITB accesses
+drivesys.cpu.dtb.fetch_acv                          0                       # ITB acv
+drivesys.cpu.dtb.fetch_hits                         0                       # ITB hits
+drivesys.cpu.dtb.fetch_misses                       0                       # ITB misses
 drivesys.cpu.dtb.read_accesses                      0                       # DTB read accesses
 drivesys.cpu.dtb.read_acv                           0                       # DTB read access violations
 drivesys.cpu.dtb.read_hits                          0                       # DTB read hits
@@ -313,10 +349,22 @@ drivesys.cpu.dtb.write_acv                          0                       # DT
 drivesys.cpu.dtb.write_hits                         0                       # DTB write hits
 drivesys.cpu.dtb.write_misses                       0                       # DTB write misses
 drivesys.cpu.idle_fraction                          1                       # Percentage of idle cycles
-drivesys.cpu.itb.accesses                           0                       # ITB accesses
-drivesys.cpu.itb.acv                                0                       # ITB acv
-drivesys.cpu.itb.hits                               0                       # ITB hits
-drivesys.cpu.itb.misses                             0                       # ITB misses
+drivesys.cpu.itb.data_accesses                      0                       # DTB accesses
+drivesys.cpu.itb.data_acv                           0                       # DTB access violations
+drivesys.cpu.itb.data_hits                          0                       # DTB hits
+drivesys.cpu.itb.data_misses                        0                       # DTB misses
+drivesys.cpu.itb.fetch_accesses                     0                       # ITB accesses
+drivesys.cpu.itb.fetch_acv                          0                       # ITB acv
+drivesys.cpu.itb.fetch_hits                         0                       # ITB hits
+drivesys.cpu.itb.fetch_misses                       0                       # ITB misses
+drivesys.cpu.itb.read_accesses                      0                       # DTB read accesses
+drivesys.cpu.itb.read_acv                           0                       # DTB read access violations
+drivesys.cpu.itb.read_hits                          0                       # DTB read hits
+drivesys.cpu.itb.read_misses                        0                       # DTB read misses
+drivesys.cpu.itb.write_accesses                     0                       # DTB write accesses
+drivesys.cpu.itb.write_acv                          0                       # DTB write access violations
+drivesys.cpu.itb.write_hits                         0                       # DTB write hits
+drivesys.cpu.itb.write_misses                       0                       # DTB write misses
 drivesys.cpu.kern.inst.arm                          0                       # number of arm instructions executed
 drivesys.cpu.kern.inst.hwrei                        0                       # number of hwrei instructions executed
 drivesys.cpu.kern.inst.quiesce                      0                       # number of quiesce instructions executed
@@ -381,18 +429,22 @@ drivesys.tsunami.ethernet.totalSwi                  0                       # to
 drivesys.tsunami.ethernet.totalTxDesc               0                       # total number of TxDesc written to ISR
 drivesys.tsunami.ethernet.totalTxIdle               0                       # total number of TxIdle written to ISR
 drivesys.tsunami.ethernet.totalTxOk                 0                       # total number of TxOk written to ISR
-host_inst_rate                           133483805176                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 478624                       # Number of bytes of host memory used
+host_inst_rate                           135334075743                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 480276                       # Number of bytes of host memory used
 host_seconds                                     0.00                       # Real time elapsed on the host
-host_tick_rate                              360871442                       # Simulator tick rate (ticks/s)
+host_tick_rate                              369524213                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   273374833                       # Number of instructions simulated
 sim_seconds                                  0.000001                       # Number of seconds simulated
 sim_ticks                                      785978                       # Number of ticks simulated
-testsys.cpu.dtb.accesses                            0                       # DTB accesses
-testsys.cpu.dtb.acv                                 0                       # DTB access violations
-testsys.cpu.dtb.hits                                0                       # DTB hits
-testsys.cpu.dtb.misses                              0                       # DTB misses
+testsys.cpu.dtb.data_accesses                       0                       # DTB accesses
+testsys.cpu.dtb.data_acv                            0                       # DTB access violations
+testsys.cpu.dtb.data_hits                           0                       # DTB hits
+testsys.cpu.dtb.data_misses                         0                       # DTB misses
+testsys.cpu.dtb.fetch_accesses                      0                       # ITB accesses
+testsys.cpu.dtb.fetch_acv                           0                       # ITB acv
+testsys.cpu.dtb.fetch_hits                          0                       # ITB hits
+testsys.cpu.dtb.fetch_misses                        0                       # ITB misses
 testsys.cpu.dtb.read_accesses                       0                       # DTB read accesses
 testsys.cpu.dtb.read_acv                            0                       # DTB read access violations
 testsys.cpu.dtb.read_hits                           0                       # DTB read hits
@@ -402,10 +454,22 @@ testsys.cpu.dtb.write_acv                           0                       # DT
 testsys.cpu.dtb.write_hits                          0                       # DTB write hits
 testsys.cpu.dtb.write_misses                        0                       # DTB write misses
 testsys.cpu.idle_fraction                           1                       # Percentage of idle cycles
-testsys.cpu.itb.accesses                            0                       # ITB accesses
-testsys.cpu.itb.acv                                 0                       # ITB acv
-testsys.cpu.itb.hits                                0                       # ITB hits
-testsys.cpu.itb.misses                              0                       # ITB misses
+testsys.cpu.itb.data_accesses                       0                       # DTB accesses
+testsys.cpu.itb.data_acv                            0                       # DTB access violations
+testsys.cpu.itb.data_hits                           0                       # DTB hits
+testsys.cpu.itb.data_misses                         0                       # DTB misses
+testsys.cpu.itb.fetch_accesses                      0                       # ITB accesses
+testsys.cpu.itb.fetch_acv                           0                       # ITB acv
+testsys.cpu.itb.fetch_hits                          0                       # ITB hits
+testsys.cpu.itb.fetch_misses                        0                       # ITB misses
+testsys.cpu.itb.read_accesses                       0                       # DTB read accesses
+testsys.cpu.itb.read_acv                            0                       # DTB read access violations
+testsys.cpu.itb.read_hits                           0                       # DTB read hits
+testsys.cpu.itb.read_misses                         0                       # DTB read misses
+testsys.cpu.itb.write_accesses                      0                       # DTB write accesses
+testsys.cpu.itb.write_acv                           0                       # DTB write access violations
+testsys.cpu.itb.write_hits                          0                       # DTB write hits
+testsys.cpu.itb.write_misses                        0                       # DTB write misses
 testsys.cpu.kern.inst.arm                           0                       # number of arm instructions executed
 testsys.cpu.kern.inst.hwrei                         0                       # number of hwrei instructions executed
 testsys.cpu.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-- 
cgit v1.2.3