From 46a79f7d10f7b8eabd4e3bb45ff50959d04a2571 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Wed, 31 Oct 2018 14:57:30 +0000 Subject: arch-arm: Refactor ISA::clear by adding a ISA::clear32 method The patch is also moving some initialization code to be used by AArch64 as well since the registers are mapped to AArch64 ones. Change-Id: I0089df25275434172c6e0e9cb125ee535c04d1b8 Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/c/13997 Maintainer: Andreas Sandberg --- src/arch/arm/isa.cc | 67 ++++++++++++++++++++++++++++------------------------- src/arch/arm/isa.hh | 1 + 2 files changed, 36 insertions(+), 32 deletions(-) diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 22d275d52..a849d04da 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -124,38 +124,6 @@ ISA::clear() // AArch32 or AArch64 initID64(p); - miscRegs[MISCREG_ID_ISAR5] = insertBits( - miscRegs[MISCREG_ID_ISAR5], 19, 4, - haveCrypto ? 0x1112 : 0x0); - - if (FullSystem && system->highestELIs64()) { - // Initialize AArch64 state - clear64(p); - return; - } - - // Initialize AArch32 state... - - CPSR cpsr = 0; - cpsr.mode = MODE_USER; - miscRegs[MISCREG_CPSR] = cpsr; - updateRegMap(cpsr); - - SCTLR sctlr = 0; - sctlr.te = (bool) sctlr_rst.te; - sctlr.nmfi = (bool) sctlr_rst.nmfi; - sctlr.v = (bool) sctlr_rst.v; - sctlr.u = 1; - sctlr.xp = 1; - sctlr.rao2 = 1; - sctlr.rao3 = 1; - sctlr.rao4 = 0xf; // SCTLR[6:3] - sctlr.uci = 1; - sctlr.dze = 1; - miscRegs[MISCREG_SCTLR_NS] = sctlr; - miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; - miscRegs[MISCREG_HCPTR] = 0; - // Start with an event in the mailbox miscRegs[MISCREG_SEV_MAILBOX] = 1; @@ -199,6 +167,7 @@ ISA::clear() (2 << 4) | // 5:4 (1 << 2) | // 3:2 0; // 1:0 + miscRegs[MISCREG_NMRR_NS] = (1 << 30) | // 31:30 (0 << 26) | // 27:26 @@ -216,6 +185,40 @@ ISA::clear() (0 << 2) | // 3:2 0; // 1:0 + if (FullSystem && system->highestELIs64()) { + // Initialize AArch64 state + clear64(p); + return; + } + + // Initialize AArch32 state... + clear32(p, sctlr_rst); +} + +void +ISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst) +{ + CPSR cpsr = 0; + cpsr.mode = MODE_USER; + + miscRegs[MISCREG_CPSR] = cpsr; + updateRegMap(cpsr); + + SCTLR sctlr = 0; + sctlr.te = (bool) sctlr_rst.te; + sctlr.nmfi = (bool) sctlr_rst.nmfi; + sctlr.v = (bool) sctlr_rst.v; + sctlr.u = 1; + sctlr.xp = 1; + sctlr.rao2 = 1; + sctlr.rao3 = 1; + sctlr.rao4 = 0xf; // SCTLR[6:3] + sctlr.uci = 1; + sctlr.dze = 1; + miscRegs[MISCREG_SCTLR_NS] = sctlr; + miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; + miscRegs[MISCREG_HCPTR] = 0; + miscRegs[MISCREG_CPACR] = 0; miscRegs[MISCREG_FPSID] = p->fpsid; diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 885190c68..89c673e4b 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -412,6 +412,7 @@ namespace ArmISA void clear(); protected: + void clear32(const ArmISAParams *p, const SCTLR &sctlr_rst); void clear64(const ArmISAParams *p); void initID32(const ArmISAParams *p); void initID64(const ArmISAParams *p); -- cgit v1.2.3