From 47326f54222af99d96ab57508449d1bb62d03842 Mon Sep 17 00:00:00 2001 From: Karthik Sangaiah Date: Wed, 15 Jul 2015 14:43:35 +0100 Subject: arm: Bootloader fix for v8 over 16 cores Previous code used a smaller 4 bit mask to test the MPIDR-EL1 register. The bitmask was extended to support greater than 16 cores. --- system/arm/aarch64_bootloader/boot.S | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/system/arm/aarch64_bootloader/boot.S b/system/arm/aarch64_bootloader/boot.S index 78d9710d4..933d7ee8a 100644 --- a/system/arm/aarch64_bootloader/boot.S +++ b/system/arm/aarch64_bootloader/boot.S @@ -34,8 +34,12 @@ _start: * registers. */ mrs x0, mpidr_el1 - tst x0, #15 - b.ne 1f // secondary CPU + // ARM MPIDR_EL1 bytes: Aff3 (AArch64), Stuff, Aff2, Aff1, Aff0 + // Test the the MPIDR_EL1 register against 0xff00ffffff to + // extract the primary CPU. + ldr x1, =0xff00ffffff + tst x0, x1 // check for cpuid==zero + b.ne 1f // secondary CPU ldr x1, =GIC_DIST_BASE // GICD_CTLR mov w0, #3 // EnableGrp0 | EnableGrp1 @@ -77,8 +81,13 @@ start_ns: mov x3, xzr mrs x4, mpidr_el1 - tst x4, #15 - b.eq 2f + // ARM MPIDR_EL1 bytes: Aff3 (AArch64), Stuff, Aff2, Aff1, Aff0 + // Test the the MPIDR_EL1 register against 0xff00ffffff to + // extract the primary CPU. + ldr x1, =0xff00ffffff + tst x4, x1 // check for cpuid==zero + mov x1, xzr // load previous 'xzr' value back to x1 + b.eq 2f // secondary CPU /* * Secondary CPUs -- cgit v1.2.3