From 50f1570352a036aed49a078b17fa1af54d0a1787 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Tue, 21 Apr 2009 15:40:25 -0700 Subject: arm: Unify the ARM tlb. We forgot about this when we did the rest. This code compiles, but there are no tests still --- src/arch/arm/ArmTLB.py | 19 +---------- src/arch/arm/tlb.cc | 85 ++++++-------------------------------------------- src/arch/arm/tlb.hh | 39 ++++------------------- src/cpu/BaseCPU.py | 6 ++-- 4 files changed, 20 insertions(+), 129 deletions(-) diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py index fa9faaddf..3dd2560fe 100644 --- a/src/arch/arm/ArmTLB.py +++ b/src/arch/arm/ArmTLB.py @@ -32,23 +32,6 @@ from m5.SimObject import SimObject from m5.params import * class ArmTLB(SimObject): - abstract = True type = 'ArmTLB' cxx_class = 'ArmISA::TLB' - size = Param.Int("TLB size") - -class ArmDTB(ArmTLB): - type = 'ArmDTB' - cxx_class = 'ArmISA::DTB' - size = 64 - -class ArmITB(ArmTLB): - type = 'ArmITB' - cxx_class = 'ArmISA::ITB' - size = 64 - -class ArmUTB(ArmTLB): - type = 'ArmUTB' - cxx_class = 'ArmISA::UTB' - size = 64 - + size = Param.Int(64, "TLB size") diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index 78eebddfe..8cce5c152 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -36,20 +36,17 @@ #include #include +#include "arch/arm/faults.hh" #include "arch/arm/pagetable.hh" #include "arch/arm/tlb.hh" -#include "arch/arm/faults.hh" #include "arch/arm/utility.hh" #include "base/inifile.hh" #include "base/str.hh" #include "base/trace.hh" #include "cpu/thread_context.hh" -#include "sim/process.hh" #include "mem/page_table.hh" -#include "params/ArmDTB.hh" -#include "params/ArmITB.hh" #include "params/ArmTLB.hh" -#include "params/ArmUTB.hh" +#include "sim/process.hh" using namespace std; @@ -279,7 +276,7 @@ TLB::regStats() } Fault -ITB::translateAtomic(RequestPtr req, ThreadContext *tc) +TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) { #if !FULL_SYSTEM Process * p = tc->getProcessPtr(); @@ -290,68 +287,18 @@ ITB::translateAtomic(RequestPtr req, ThreadContext *tc) return NoFault; #else - fatal("ITB translate not yet implemented\n"); + fatal("translate atomic not yet implemented\n"); #endif } void -ITB::translateTiming(RequestPtr req, ThreadContext *tc, - Translation *translation) +TLB::translateTiming(RequestPtr req, ThreadContext *tc, + Translation *translation, Mode mode) { assert(translation); - translation->finish(translateAtomic(req, tc), req, tc, false); -} - - -Fault -DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write) -{ -#if !FULL_SYSTEM - Process * p = tc->getProcessPtr(); - - Fault fault = p->pTable->translate(req); - if(fault != NoFault) - return fault; - - return NoFault; -#else - fatal("DTB translate not yet implemented\n"); -#endif + translation->finish(translateAtomic(req, tc, mode), req, tc, mode); } -void -DTB::translateTiming(RequestPtr req, ThreadContext *tc, - Translation *translation, bool write) -{ - assert(translation); - translation->finish(translateAtomic(req, tc, write), req, tc, write); -} - -/////////////////////////////////////////////////////////////////////// -// -// Arm ITB -// -ITB::ITB(const Params *p) - : TLB(p) -{} - - -/////////////////////////////////////////////////////////////////////// -// -// Arm DTB -// -DTB::DTB(const Params *p) - : TLB(p) -{} - -/////////////////////////////////////////////////////////////////////// -// -// Arm UTB -// -UTB::UTB(const Params *p) - : ITB(p), DTB(p) -{} - ArmISA::PTE & TLB::index(bool advance) { @@ -363,20 +310,8 @@ TLB::index(bool advance) return *pte; } -ArmISA::ITB * -ArmITBParams::create() -{ - return new ArmISA::ITB(this); -} - -ArmISA::DTB * -ArmDTBParams::create() -{ - return new ArmISA::DTB(this); -} - -ArmISA::UTB * -ArmUTBParams::create() +ArmISA::TLB * +ArmTLBParams::create() { - return new ArmISA::UTB(this); + return new ArmISA::TLB(this); } diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index fea317ef3..d2c035b31 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -43,8 +43,7 @@ #include "arch/arm/pagetable.hh" #include "base/statistics.hh" #include "mem/request.hh" -#include "params/ArmDTB.hh" -#include "params/ArmITB.hh" +#include "params/ArmTLB.hh" #include "sim/faults.hh" #include "sim/tlb.hh" @@ -135,6 +134,10 @@ class TLB : public BaseTLB static Fault checkCacheability(RequestPtr &req); + Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); + void translateTiming(RequestPtr req, ThreadContext *tc, + Translation *translation, Mode mode); + // Checkpointing void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); @@ -142,36 +145,6 @@ class TLB : public BaseTLB void regStats(); }; -class ITB : public TLB -{ - public: - typedef ArmTLBParams Params; - ITB(const Params *p); - - Fault translateAtomic(RequestPtr req, ThreadContext *tc); - void translateTiming(RequestPtr req, ThreadContext *tc, - Translation *translation); -}; - -class DTB : public TLB -{ - public: - typedef ArmTLBParams Params; - DTB(const Params *p); - - Fault translateAtomic(RequestPtr req, ThreadContext *tc, bool write); - void translateTiming(RequestPtr req, ThreadContext *tc, - Translation *translation, bool write); -}; - -class UTB : public ITB, public DTB -{ - public: - typedef ArmTLBParams Params; - UTB(const Params *p); - -}; - -} +/* namespace ArmISA */ } #endif // __ARCH_ARM_TLB_HH__ diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 3aa9b87bb..4661375ba 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -54,7 +54,7 @@ elif build_env['TARGET_ISA'] == 'mips': if build_env['FULL_SYSTEM']: from MipsInterrupts import MipsInterrupts elif build_env['TARGET_ISA'] == 'arm': - from ArmTLB import ArmDTB + from ArmTLB import ArmTLB if build_env['FULL_SYSTEM']: from ArmInterrupts import ArmInterrupts @@ -109,8 +109,8 @@ class BaseCPU(MemObject): MipsInterrupts(), "Interrupt Controller") elif build_env['TARGET_ISA'] == 'arm': UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") - dtb = Param.ArmTLB(ArmDTB(), "Data TLB") - itb = Param.ArmTLB(ArmITB(), "Instruction TLB") + dtb = Param.ArmTLB(ArmTLB(), "Data TLB") + itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") if build_env['FULL_SYSTEM']: interrupts = Param.ArmInterrupts( ArmInterrupts(), "Interrupt Controller") -- cgit v1.2.3