From 52c8ae5187cb6ba8d15a8de6526f56defe541f5b Mon Sep 17 00:00:00 2001 From: Ali Jafri Date: Fri, 6 Nov 2015 03:26:37 -0500 Subject: mem: Enforce insertion order on the cache response path This patch enforces insertion order transmission of packets on the response path in the cache. Note that the logic to enforce order is already present in the packet queue, this patch simply turns it on for queues in the response path. Without this patch, there are corner cases where a request-response is faster than a response-response forwarded through the cache. This violation of queuing order causes problems in the snoop filter leaving it with inaccurate information. This causes assert failures in the snoop filter later on. A follow on patch relaxes the order enforcement in the packet queue to limit the performance impact. --- src/mem/cache/cache.cc | 6 +++--- src/mem/dram_ctrl.cc | 2 +- src/mem/qport.hh | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc index aa95d5604..a03790abc 100644 --- a/src/mem/cache/cache.cc +++ b/src/mem/cache/cache.cc @@ -666,7 +666,7 @@ Cache::recvTimingReq(PacketPtr pkt) // lat, neglecting responseLatency, modelling hit latency // just as lookupLatency or or the value of lat overriden // by access(), that calls accessBlock() function. - cpuSidePort->schedTimingResp(pkt, request_time); + cpuSidePort->schedTimingResp(pkt, request_time, true); } else { // queue the packet for deletion, as the sending cache is // still relying on it; if the block is found in access(), @@ -723,7 +723,7 @@ Cache::recvTimingReq(PacketPtr pkt) std::memset(pkt->getPtr(), 0xFF, pkt->getSize()); // request_time is used here, taking into account lat and the delay // charged if the packet comes from the xbar. - cpuSidePort->schedTimingResp(pkt, request_time); + cpuSidePort->schedTimingResp(pkt, request_time, true); // If an outstanding request is in progress (we found an // MSHR) this is set to null @@ -1330,7 +1330,7 @@ Cache::recvTimingResp(PacketPtr pkt) } // Reset the bus additional time as it is now accounted for tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0; - cpuSidePort->schedTimingResp(tgt_pkt, completion_time); + cpuSidePort->schedTimingResp(tgt_pkt, completion_time, true); break; case MSHR::Target::FromPrefetcher: diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc index abf570910..2364834e3 100644 --- a/src/mem/dram_ctrl.cc +++ b/src/mem/dram_ctrl.cc @@ -860,7 +860,7 @@ DRAMCtrl::accessAndRespond(PacketPtr pkt, Tick static_latency) // queue the packet in the response queue to be sent out after // the static latency has passed - port.schedTimingResp(pkt, response_time); + port.schedTimingResp(pkt, response_time, true); } else { // @todo the packet is going to be deleted, and the DRAMPacket // is still having a pointer to it diff --git a/src/mem/qport.hh b/src/mem/qport.hh index 94bcc53fd..b15bdfec2 100644 --- a/src/mem/qport.hh +++ b/src/mem/qport.hh @@ -88,8 +88,8 @@ class QueuedSlavePort : public SlavePort * @param pkt Packet to send * @param when Absolute time (in ticks) to send packet */ - void schedTimingResp(PacketPtr pkt, Tick when) - { respQueue.schedSendTiming(pkt, when); } + void schedTimingResp(PacketPtr pkt, Tick when, bool force_order = false) + { respQueue.schedSendTiming(pkt, when, force_order); } /** Check the list of buffered packets against the supplied * functional request. */ -- cgit v1.2.3